Sanechips Technology Patente

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Provided is a clock calibration circuit. The circuit includes: a first sampling circuit; and a second sampling circuit in series with the first sampling circuit; the first sampling circuit comprises: a phase-locked loop (PLL); a first duty cycle calibrator (DCC) connected in series with the PLL; a first phase interpolator (PI) connected in series with the first DCC; a first clock tree connected in series with the first PI; a first data serializer connected in series with the first clock tree; a first transmit driver connected in series with the first data serializer; a second data serializer connected in series with the first DCC; and a second transmit driver connected in series with the second data serializer; the PLL is configured to output a clock signal to drive the first data serializer to transmit data to be transmitted to the first transmit driver, and drive the second data serializer to transmit a feedforward clock signal to the second transmit driver; and the second transmit driver is configured to transmit the feedforward clock signal to a first receive driver in the second sampling circuit, to determine the feedforward clock signal as a sampling clock for the second sampling circuit.

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Provided are a TTI storage method and apparatus, an electronic device and a computer readable storage medium. The method includes: acquiring a plurality of storage units with consecutive index numbers; wherein each of the storage units comprises a first storage space and a second storage space; acquiring a target TTI from absolute transmission time intervals (TTI) in a resource pool to be stored; wherein the absolute TTI refers to an arbitrary TTI in the resource pool; sequentially storing the absolute TTIs into the first storage spaces of the plurality of storage units according to an order within a System Frame Number (SNF) cycle; the first storage space comprises a plurality of bits and represents a TTI respectively; for each bit, a bit identifier indicates the target TTI or a non-target TTI; counting a total number of the target TTls stored in all storage units having index numbers less than a respective index number of each of the storage units; and storing the total number of the target TTIs into the second storage space of a corresponding storage unit.

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Provided in the present application are a data processing method, a data processing apparatus, a communication device, and a computer-readable storage medium. The data processing method comprises: acquiring service data of currently activated k component carriers, wherein k is an integer greater than or equal to 1; forming an arrangement-period data pattern on the basis of the service data of the currently activated k component carriers, wherein the arrangement-period data pattern comprises at least some of the service data of the currently activated k component carriers; and forming a first data frame on the basis of the arrangement-period data pattern, wherein the payload of the first data frame comprises N arrangement-period data patterns, and N is an integer greater than or equal to 1.

Embodiments of the present disclosure provide a routing information processing method and apparatus for asymmetric routing. The method includes: acquiring a destination bandwidth and a source bandwidth of a first-stage switch fabric SF1; determining a first weight coefficient on the basis of the destination bandwidth and the source bandwidth, and allocating the destination bandwidth to a source switch access, SA, according to the first weight coefficient; and determining a second weight coefficient on the basis of the duty ratio of an efficient link of the source SA, and according to the second weight coefficient, allocating the destination bandwidth, which is allocated to the source SA to the efficient link of the source SA, so as to realize the routing information processing process.

Provided in the embodiments of the present disclosure are an instruction processing method and device, and a storage medium and an electronic device. The method comprises: on the basis of a preset instruction code, determining from among a plurality of instructions to be processed a first-type instruction to be processed; using an update mode corresponding to said first-type instruction to update a first vector parameter to a second vector parameter; and on the basis of the second vector parameter, splitting into a plurality of micro-operations a long vector instruction in the other instructions to be processed, and performing renaming processing on said other instructions on the basis of the plurality of micro-operations, wherein said other instructions are instructions among the plurality of instructions to be processed other than said first-type instruction. By means of the present disclosure, the problems in the related art of an execution part circuit in a processor being excessively complex and having an excessively large area and an enormous power consumption overhead due to the occurrence of a long vector in vector instructions are solved.

The present disclosure provides a cache, including at least two layer structures, each of the at least two layer structures includes: a first cache unit and a second cache unit, first cache access instructions of different layer structures enter different pipelines to access the first cache units in corresponding layer structures, and second cache access instructions of the different layer structures enter different pipelines to access the second cache units in corresponding layer structures.

The present disclosure provides a data storage method, applied to a data processing apparatus. A first linked list used for managing on-chip storage and a second linked list used for managing off-chip storage are configured in the data processing apparatus; the first linked list and the second linked list comprise queue information and node switching information; the queue information of the first linked list comprises a storage mark; and the storage mark is used for representing that a data storage mode is on-chip storage or off-chip storage. The method comprises: determining a first storage mode of data to be stored, and determining a second storage mode of previous data storage on the basis of a storage mark; and when the first storage mode is different from the second storage mode, determining a target node for the previous data storage, updating node switching information of the target node in a linked list corresponding to the target node, and updating the storage mark. The present disclosure further provides a data reading method, a data processing apparatus, and a readable medium.

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