Semiconductor Manufacturing International (Beijing) Patente

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The present invention provides D flip-flops (100) and signal driving methods (fig. 8) using D flip-flops thereof. An exemplary D flip-flop includes a pulse signal generating circuit (10) configured to input a first clock signal (CP), a first data signal (D), a second data signal (Q) and a third data signal (Qb) and generate a clock pulse signal (CP_Pulse). The clock pulse signal (CP_Pulse) responds a raising-edge and a falling-edge of the first clock signal (CP). The pulse clock signal (CP_Pulse) is a pulse signal when the first data signal (D) is opposite to the second data signal (Q). The D flip-flop also includes a latching circuit (20) configured to sample and transfer the first data signal (D) and a data signal opposite to the first data signal (Db) to be used as the second signal (Q) and a fourth data (third data Qb) signal respectively when the clock signal (CP_Pulse) is at the high level.

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An input-output "I/O" receiver includes a receiving terminal (PAD), a first N-type metal-oxide-semiconductor "NMOS" transistor (N1), a reformation circuit (202), and a compensation unit (201). The receiving terminal (PAD) is coupled with an external voltage signal. The first NMOS transistor (N1) has a source electrode coupled with the receiving terminal and a gate electrode coupled with a first power supply voltage (VDD1). The reformation circuit (202) is configured to reform a voltage signal transmitted from a drain electrode of the first NMOS transistor. The compensation unit (201) includes a first PMOS transistor (P1), a second PMOS transistor (P2), and a second NMOS transistor (N2). Moreover, the compensation unit (201) is configured to provide a compensation voltage to a voltage signal (B) at the drain electrode of the first NMOS transistor thereby a maximum level of the voltage signal at the drain electrode of the first NMOS transistor (N1) reaches the first power supply voltage (VDD1).

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A flash memory device includes a substrate, an electrode layer on a portion of the substrate, the electrode layer being a work function adjusting layer or a metal silicide layer, and a memory cell. The memory cell includes a channel structure on the electrode layer and having, from the inside to the outside in this order, a channel layer in contact with the electrode layer, a tunneling insulator layer surrounding the channel layer, a charge trapping layer surrounding the tunneling insulator layer, and a barrier layer surrounding the charge trapping layer, and a plurality of gate structures surrounding the channel structure along an axial direction of the channel structure. The flash memory device may be formed on a dielectric layer, and its fabrication process is thus compatible with back end of line processes.

A substrate alignment device includes a plurality of state detection units, each of which is configured to move from a standby position to a detection position for detecting a positional state of a substrate and return back from the detection position back to the standby position, and a multidimensional robot arm configured to receive and support the substrate, transfer the substrate to a substrate detection site, and adjust the substrate in at least one orientation or position according to the detected positional state of the substrate to position the substrate to a target position for overlay mark measurements.

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A memory and a reference circuit calibration method are provided. The memory includes: a memory array including a plurality of memory cells; a reference circuit including a reference memory cell and a reference connection terminal, wherein the reference memory cell is a same as the memory cell; a calibration circuit including a calibration connection terminal, and a mirror circuit including a first mirror terminal and a second mirror terminal, wherein the first mirror terminal is connected to the reference connection terminal, and the second mirror terminal is connected to the calibration connection terminal; a clamp circuit, configured to set one of a voltage of the reference connection terminal and a voltage of the calibration connection terminal as a preset voltage and to set the other thereof as a comparison voltage; and a comparison circuit configured to input the comparison voltage and the preset voltage, and to output a comparison result.

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Semiconductor devices and fabrication methods thereof are provided. An exemplary fabrication method includes providing a semiconductor substrate; forming a plurality of fins on a surface of the semiconductor substrate; forming an isolation flowable layer covering the plurality of fins over the semiconductor substrate; performing a first annealing process to turn the isolation flowable layer into an isolation film; and forming first well regions and second well regions in the fins and the semiconductor substrate. The second well regions are at two sides of the first well regions and contact with the first well regions; the first well regions have a first type of well ions; the second well regions have a second type of well ions; and the first type is opposite to the second type in the conductivities.

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The present invention provides CMOS image sensors and fabrication methods thereof. An exemplary fabrication process of a CMOS image sensor includes providing a substrate having a first region and a second region connecting with the first region at a first end of the first region; forming a transfer transistor on surface of the substrate in the second region; forming a first implanting region in the substrate in the first region using a first mask; forming a second implanting region in the first implanting region by, the first implanting region being separated into a third implanting region on the second implanting region and a fourth implanting region under the second implanting region; forming a fifth region in the second region at the first end using a second mask, connecting the third implanting region with the fourth implanting region.

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The present invention provides semiconductor structures and fabrication methods thereof. An exemplary semiconductor structure includes an insulation material layer having a top semiconductor layer having transistor regions formed on a top surface of the insulation material layer; isolation structures formed in the top semiconductor layer between adjacent transistor regions; a first dielectric layer formed over the top semiconductor layer; a first heat-conducting layer having a thermal conductivity higher than a thermal conductivity of the isolation structure and passing through the insulation material layer, the top semiconductor layer and the first dielectric layer; a second dielectric layer formed over the first dielectric layer; an interconnect structure formed in the second dielectric layer; and a bottom layer conductive via passing through the heat-conducting layer and a partial thickness of the second dielectric layer, and electrically connected with the interconnect structure.

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