STMicroelectronics International

A stream-triggered multi-thread accelerator includes a data streaming interface, a memory, vector processing circuitry and scheduling circuitry. The data streaming interface, in operation, receives and transmits data streams of a plurality of data streaming channels. The memory, in operation, stores a plurality of instruction threads. The plurality of instruction threads include wait-for-trigger instructions specifying streaming data trigger thresholds, and instructions having data streaming channels of the plurality of data streaming channels as operands. The vector processing circuitry is coupled to the memory and to the data streaming interface. The vector processing circuitry, in operation, executes instruction threads of the plurality of instruction threads. The scheduling circuitry, in operation, schedules execution of instruction threads of the plurality of instruction threads by the vector processing circuitry based on the streaming data trigger thresholds of the wait-for-trigger instructions.

A hardware accelerator includes a stream switch, a programmable component and multi-context control circuitry. The stream switch streams a data stream to the programmable component and to the multi-context control circuitry. The multi-context control circuitry, in a configured context mode of operation, counts valid data transactions of the data stream streamed to the programmable component, and controls a sequence of processing operations to be performed on the data of the data stream by the programmable component based on the counting of the valid data transactions of the data stream and on stored configured-context mode configuration information. The multi-context control circuitry, in a hybrid context mode of operation, monitors the data stream to read embedded context tags, and controls a sequence of processing operations to be performed on the data based on the embedded context tags, on the counting of the valid data transactions, and stored hybrid-context mode configuration information.

According to an embodiment, a wireless power receiving device (120) includes a demodulator (212) that generates carrier cycle data (SYS_CNT) from a received frequency-shift keying modulated signal (FSK_IN) with dithering. A highpass filtering circuit (404) extracts offset values from the carrier cycle data. A polyphase filtering circuit (406) includes multiple smoothing filters (704) and distributes the extracted offset values among these filters based on a dithering pattern length. A compensation circuit (408) stores smoothed offset values from the polyphase filtering circuit (406) in a dithering table (802) during an evaluation window and applies these stored values to compensate carrier cycle data during subsequent demodulation.

A neural processing unit implements a neural network and includes a decompression unit including a plurality of decompression cores. During operation of the neural network, compressed kernel data is streamed from an onboard storage to the decompression unit. The decompression unit includes multiple decompression cores. The decompression unit selectively configures the decompression cores to utilize a plurality of decompression algorithms and switches between the multiple decompression algorithms on-the-fly to properly decompress the compressed kernel data in a lossless manner.

La présente description concerne un transistor (43) HEMT comportant : - une première couche semiconductrice (13) ; et - une grille (45) disposée sur une première face de la première couche semiconductrice (13), dans lequel la grille (45) comprend une alternance d'au moins deux premières couches (451) et d'au moins trois deuxièmes couches (453), les premières couches (451) étant dopées en magnésium et en au moins l'un des éléments dopants choisi parmi le silicium et l'oxygène et les premières couches (451) ayant une concentration en éléments dopants supérieure à la concentration en éléments dopants dans les deuxièmes couches (453).

Microelectromechanical -MEMS- device (35) formed by a first substrate (1'), having a first and a second main face (35A, 1B) and accommodating integrated electrical components (10) and external connection vias (33) extending through the first substrate (1'); a second substrate (2'), having a first and a second main face (2A, 25B) and accommodating conductive vias (17) extending between the first and second main surfaces of the second substrate, the first main face (25B) of the second substrate (2') coupled to the second main face (1B) of the first substrate (1') and the conductive vias (17) coupled to the external connection vias (33); and a third substrate (3'), having a main face (3A) and accommodating MEMS structures (19), the main face (3A) of the third substrate (3') coupled to the second main face (25B) of the second substrate (2'). The conductive vias (17) and the external connection vias (33) electrically couple the first face (35A) of the first substrate (1') to the MEMS structures (19).

La présente description concerne un circuit de calcul (100) comprenant :- au moins un cœur de calcul (102) basé sur une architecture sur une architecture en pipeline à ordinateur à jeu d'instructions réduit, RISC-V ;- un ou plusieurs circuits de mémoire (128) configurés pour mettre en œuvre un calcul en mémoire, IMC ;et dans lequel le cœur de calcul comprend un étage d'exécution (108) configuré pour utiliser lesdits un ou plusieurs circuits de mémoire pour mettre en œuvre l'IMC.

A voltage comparison circuit (20, 30) is disclosed. A measurement circuit (20) is configured to generate a measurement signal (V_S) indicative of an input voltage (V_IN), wherein the measurement circuit (20) comprises a voltage divider (RA, RB). The collectors of a first npn bipolar transistor (Q1) and a second npn bipolar transistor (Q2) are coupled to a supply voltage (VDD), and the bases of the first npn bipolar transistor (Q1) and the second npn bipolar transistor (Q2) are coupled to an intermediate node (A) of the voltage divider (RA, RB). A first resistance (R1) is connected between the emitter of the first npn bipolar transistor (Q1) and ground (102), and a second resistance (R2) is connected between the emitter of the second npn bipolar transistor (Q2) and the emitter of the first npn bipolar transistor (Q1). An emitter area of the second bipolar transistor (Q2) is greater than an emitter area of the first bipolar transistor (Q1).A comparison circuit (32, 34, 36, 40) is configured to generate a comparison signal (PG) as a function of a first current (I_Q1) flowing through the collector of the first npn bipolar transistor (Q1) and a second current (I_Q2) flowing through the collector of the second npn bipolar transistor (Q2). Specifically, in response to determining that the first current (I_Q1) is greater than the second current (I_Q2), the comparison circuit (32, 34, 36, 40) asserts the comparison signal (PG).According to various embodiments, the voltage comparison circuit (20, 30) comprises an n-channel FET (M0) having a drain connected to the intermediate node (A), a source connected to the bases of the first npn bipolar transistor (Q1) and the second npn bipolar transistor (Q2) and a gate connected to a bias voltage (V_B), wherein the bias voltage (V_B) corresponds to or is smaller than the supply voltage (VDD).

A process for manufacturing a power electronic device (100) having a plurality of elementary cells, envisages: providing a substrate (2), having a first electrical conductivity (n) and a first doping value and defining a front surface (1a); forming first CSL - Current Spreading Layer - regions (6) in a deep position of the substrate (2) at a distance from the front surface (1a), having the first electrical conductivity (n) and a second doping value, greater than the first doping value; forming first doped regions (10) of elementary cells of the power electronic device (100) above the first current spreading regions (6), having a second conductivity type (p) and separated from each other in a direction (x) parallel to the front surface (1a) by intercell regions (2') of the power electronic device (100); forming second CSL - Current Spreading Layer - regions (16) at the intercell regions (2'), having the first electrical conductivity (n) and distinct and independent characteristics with respect to the first current spreading regions (6).

A voltage-regulator (50) provides regulated-voltage to a digital circuit (60) from a supply-voltage input (VDD). The regulator (50) includes an amplifier (51) comparing a reference-voltage (Vbg) with the regulated-voltage to control a source-gate voltage of an output-transistor (MP1). A source-gate voltage-boosting circuit improves the response of the regulator (50) for operations with high current-demands like high-frequency digital-interface communication. The boosting-circuit includes a capacitor (C) switchable connected between the supply-voltage (VDD) and either a bias current source (IB3) or the gate of the output-transistor (MP1). A phase-generator (57) controls two switches (S1, S2) through non-overlapping control-signals (φint, φsh), implementing an integration-phase and a sharing-phase. During integration, the capacitor (C) charges to a voltage above the source-to-gate voltage of the output-transistor (MP1). During sharing, this charged capacitor (C) connects to the gate of the transistor (MP1), boosting the source-to-gate voltage to increase current sourcing capability during high-frequency digital circuit operation. A clock-gating circuit (55) enables the phase-generator (57) in response to clock activation, synchronizing the boost operation with periods of increased current demand.