Samsung Electronics

A semiconductor nanoparticle, a method of preparing the semiconductor nanoparticle, and a display device including the semiconductor nanoparticle. The semiconductor nanoparticle includes silver, indium, gallium, and sulfur, and as a radial concentration distribution of silver, indium, and gallium is measured, the semiconductor nanoparticle exhibits a maximum value of a mole ratio of gallium to a total of indium and gallium in a first zone, and in the first zone, a mole ratio of silver to the total of indium and gallium is greater than or equal to about 0.18:1 and less than 1.5:1, and the semiconductor nanoparticle exhibits a quantum yield of greater than or equal to about 85%.

A display apparatus includes a display layer including a plurality of light-emitting devices, and a drive layer configured to drive the plurality of light-emitting devices, where at least one of the plurality of light-emitting devices includes a light-emitting structure including a first light-emitting element, a second light-emitting element, and a third light-emitting element sequentially and monolithically stacked from the drive layer in a first direction, each of the first light-emitting element, the second light-emitting element, and the third light-emitting element including a p-type semiconductor layer, an active layer, and an n-type semiconductor layer, where the n-type semiconductor layer of the first light-emitting element includes AlGaN and a doping amount of an n-type dopant in the n-type semiconductor layer of the first light-emitting element is 2E+19/cm<3> or more.

Provided are systems (100), methods, and apparatuses for data replication in memory devices (115). In one or more examples, the systems (100), devices, and methods include providing an allocation of memory resources of a memory pool appliance to a host (105); selecting a first memory module of multiple memory modules of the memory pool appliance as a primary memory resource of the allocation; selecting at least a second memory module of the multiple memory modules as a secondary memory resource of the allocation; configuring, in a memory switch of the memory pool appliance and for the allocation, a virtual memory module as an interface between the host (105) and memory modules of the allocation; and executing a first command, received at the virtual memory module and from the host (105), to read data based on the allocation.

The present disclosure relates to an image sensor and a method of operating the image sensor. An example image sensor include a first sub-pixel group (PGs11) including a first plurality of photodiodes (PD1 - PD8) arranged in a plurality of rows and a plurality of columns and sharing a first floating diffusion node (FD1), a second sub-pixel group (PGs12) adjacent to the first sub-pixel group (PGs11), and including a second plurality of photodiodes (PD9 - PD16) arranged in a plurality of rows and a plurality of columns and sharing a second floating diffusion node (FD2) separate from the first floating diffusion node (FD1), a color filter (CF1), at least a portion of which is disposed on the first sub-pixel group (PGs11) and the second sub-pixel group (PGs12), and a first lens (MLb), at least a portion of which is overlapped planarly with the first sub-pixel group (PGs11) and the second sub-pixel group (PGs12).

An example semiconductor device is a SiC semiconductor device, including a buffer layer, a first conductivity type semiconductor layer on a first surface of the buffer layer, a second conductivity type well region in the first conductivity type semiconductor layer, a first conductivity type well region in the second conductivity type well region, a gate electrode adjacent to the second conductivity type well region, a gate insulating layer between the gate electrode and the second conductivity type well region, a first electrode on the first conductivity type well region, and a second electrode on a second surface of the buffer layer, the second surface being opposite the first surface. The buffer layer includes a first buffer layer including a first element homologous to Si, and, in the first buffer layer, the content of the first element is 10 at% to 50 at%.

A three-dimensional semiconductor memory device includes a first peripheral circuit structure (PS1) and a second peripheral circuit structure (PS2) sequentially provided on a first substrate (10). The second peripheral circuit structure includes a second substrate (100) having a first surface (100a) and a second surface (100b) facing the first surface, a transistor array (TA) including transistors (TR2) on the first surface of the second substrate, an insulating layer (40) on the second surface of the second substrate, a conductive line (CL) extending in the insulating layer in a first direction parallel to the first surface of the second substrate, and a conductive contact (CT) between the conductive line and the second surface of the second substrate.

A semiconductor device includes: a bit line on a substrate and extending in a first direction parallel to an upper surface of the substrate; a semiconductor pattern on the bit line and extending in a direction perpendicular to the upper surface of the substrate; a gate electrode on a side surface of the semiconductor pattern and extending in a second direction intersecting the first direction; a storage node contact on an upper surface of the semiconductor pattern; an upper insulating layer covering a side surface of the storage node contact; and a capping pattern between the upper insulating layer and the gate electrode. The upper insulating layer is on an upper surface of the capping pattern. The upper surface of the semiconductor pattern and the upper surface the capping pattern each have a concave profile.

A memory device (200) includes a memory cell array (210) including one or more banks, a power gating switch (231) disposed on a power path for transmitting a power supply voltage (VDD, VPP) inside the memory device (200), a power gating controller (232) configured to turn on or off a power gating operation of the power gating switch (231) based on a temperature of the memory device (200,) and a frequency of an access to the memory device (200), and a control logic circuit (240) configured to provide, to the power gating controller (232), temperature information (Temp) indicating the temperature of the memory device (200) and a counting value indicating the frequency of the access, wherein when the power gating operation is turned on, the power gating switch (231) toggles in response to the access to the memory device (200), and when the power gating operation is turned off, the power gating switch (231) remains turned on regardless of the access to the memory device (200).

A low molecular weight compound represented by Chemical Formula (1) or Chemical Formula (2), each of which is described herein; a composition including the low molecular weight compound and a salt compound, the salt compound including a borate anion represented by Chemical Formula (3), which is described herein, and an iodonium cation; an organic film prepared by curing the composition and a carboxyl-containing compound; and an electroluminescent device including the organic film are disclosed.

A memory device (30b) includes a plurality of planes (31, 32) and a control circuit. The plurality of planes (31, 32) may be included in a chip, and each of which may include a cell array and a page buffer. The control circuit, in a first mode, may enable or disable at least one first plane (31) among the plurality of planes (31, 32) based on a signal (nCE1) received through a first chip enable pad (P01) and output a signal (RnB1) that indicates a state of the at least one first plane (31) through a first ready/busy pad (P02). The control circuit may also enable or disable at least one second plane (32) among the plurality of planes (31, 32) based on a signal (nCE2) received through a second chip enable pad (P05) and output a signal (RnB2) that indicates a state of the at least one second plane (32) through a second ready/busy pad (P06).