Yangtze Memory Technologies

A memory device, a memory system, and a method for data calculation with the memory device are provided. The memory device includes an array of memory cells and a peripheral circuit coupled to the memory cells is provided. The peripheral circuit includes a control logic configured to program first data and second data into different banks of the banks of memory cells, at least one process unit configured to perform calculation based on the first data and the second data, and a data-path bus coupled to the control logic and the at least one process unit to transmit the first date and the second data.

The present disclosure provides a decoder, a decoding method, , wherein the decoder is configured to perform layered iterative decoding based on a check matrix corresponding to a codeword to be decoded, and the decoder comprises: a first memory and a message updating circuit; the first memory is configured to store a posterior probability message; the message updating circuit is configured to: sequentially read a posterior probability message corresponding to each non-zero sub-matrix of a current layer from the first memory in a first reading order; the first reading order is determined according to a position of each non-zero sub-matrix of the current layer; obtain an updated posterior probability message corresponding to each non-zero sub-matrix of the current layer based on the posterior probability message corresponding to each non-zero sub-matrix of the current layer in a current iteration; sequentially write the updated posterior probability message corresponding to each non-zero sub-matrix of the current layer into the first memory in a first writing order; the first writing order is determined according to the first reading order.

A memory device, a memory system, and a method for data calculation with the memory device are provided. The memory device includes an array of memory cells and a peripheral circuit coupled to the memory cells is provided. The peripheral circuit includes a static random-access memory (SRAM) configured to obtain first data transmitted from a data interface of the memory device, page buffers configured to sense second data from the array of memory cells, and at least one process unit coupled to the SRAM and the page buffers via a data-path bus of the peripheral circuit. At least one process unit is configured to perform calculation based on the first data and the second data. The peripheral circuit further includes a control logic configured to program the second data into the array of memory cells.

A non-volatile memory device and a control method are provided e disclosed. The non-volatile memory device includes a memory array, a bit line, a plurality of word lines, a first control circuit, and second control circuit. The bit line is connected to a first memory string of the memory array. The plurality of word lines are connected to memory cells of the first memory string and each word line is connected to a respective memory cell. The first control circuit is configured to apply a bit line pre-pulse signal to the bit line during a pre-charge period. The second control circuit is configured to apply a word line signal to a selected word line and apply a plurality of word line pre-pulse signals to word lines disposed between a select gate line and the selected word line. Voltage levels of the plurality of word line pre-pulse signals are incremental.

Embodiments of 3D memory devices and methods for forming the same are disclosed. In one example, a 3D memory device includes a multi-layer stacked structure, where the multi-layer stacked structure includes a plurality of alternately stacked conductive layers and dielectric layers. The 3D memory device further includes a semiconductor layer over the multi-layer stacked structure, and a plurality of channel structures penetrating into the multi-layer stacked structure and the semiconductor layer. A first end of each channel structure is located within the semiconductor layer, and the first ends of the channel structures are aligned with one another.

The present disclosure provides a method for forming a three-dimensional (3D) memory device. The method includes disposing an alternating dielectric stack over a substrate, wherein the alternating dielectric stack includes first dielectric layers and second dielectric layers alternatingly stacked on the substrate. The method also includes forming a channel structure penetrating through the alternating dielectric stack and extending into the substrate, wherein the channel structure includes a channel layer disposed on a sidewall of a memory film. The method further includes removing the substrate and a portion of the memory film that extends into the substrate to expose a portion of the channel layer; and disposing an array common source (ACS) on the exposed portion of the channel layer.

Examples of the present disclosure provide a computational storage system, an operating method thereof, and an electronic system, the computational storage system includes a controller, a first memory coupled to the controller, and a computing processing component configured to execute a program; the first memory includes a respective storage area configured for input data / output data in a process of executing the program by the computing processing component; the controller is configured to: refresh the input data / output data in the process of executing the program into the respective storage area in batches sequentially; and a size of the input data / output data in the process of executing the program is greater than a capacity size of the respective storage area

Examples of the present disclosure provide a computational storage system, an operating method thereof, and an electronic system, the computational storage system comprises a controller, a first memory coupled to the controller, and a computing processing component configured to execute a program; the controller is configured to: receive a command sent by a host coupled to the computational storage system, wherein the command is to instruct the computing processing component to execute the program, and the command is to define association information of a respective address of at least one of input data or output data in a process of executing the program in the first memory; and obtain the respective address of at least one of input data or output data in the process of executing the program in the first memory from the host according to the association information.

A double data rate circuit includes a clock generator, a clock divider and a multiplexer. The clock generator is used to receive a source clock signal to generate a pair of complementary clock signals. The clock divider is coupled to the clock generator, and used to generate four multiphase clock signals using only single-edge transitions of the pair of complementary clock signals. The four multiphase clock signals are successively out-of-phase by 90°. The multiplexer is coupled to the clock divider, and used to multiplex multiple data bits into an output data stream by sequentially selecting and deselecting each data bit of the multiple data bits upon a first edge transition of and a second edge transition of two of the four multiphase clock signals, respectively, and outputting each selected data bit as the output data stream.

In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes an array of memory cells, a first peripheral circuit of the array of memory cells, and a polysilicon layer between the array of memory cells and the first peripheral circuit. The first peripheral circuit includes a first transistor. The second semiconductor structure includes a second peripheral circuit of the array of memory cells. The second peripheral circuit includes a second transistor.