imec

According to an aspect there is provided a device for mechanical phenotyping of cells, said device comprising:a sample vessel configured to accommodate a sample fluid comprising cells at an analysis position;an ultrasound generation unit integrated with the sample vessel,wherein the ultrasound generation unit is configured to generate an acoustic wave and to transmit the acoustic wave into the sample vessel at the analysis position for causing the acoustic wave to interact with the sample fluid forming a response acoustic wave being affected by the sample fluid; andan ultrasound detection unit integrated with the sample vessel, wherein the ultrasound detection unit is configured to detect the response acoustic wave and to generate a signal representing information of a cell in the sample fluid.

According to an aspect, there is provided a method for forming a memory structure for a 3D NAND flash memory, the method comprising: forming a layer stack over a substrate, the layer stack comprising an alternating sequence of gate layers and inter-gate spacer layers; forming recessed areas in a sidewall surrounding a memory hole in the layer stack by laterally etching back the gate layers relative to the inter-gate spacer layers from the memory hole; forming an initial charge trap layer in each recessed area; depositing a tunneling oxide layer in the memory hole; depositing a channel layer on the tunneling oxide layer; forming an access trench in the layer stack; forming gate cavities in the layer stack by laterally etching back the gate layers from the access trench in a direction towards the memory hole, wherein the gate cavities expose the initial charge trap layers; oxidizing a portion of the initial charge trap layer in each gate cavity such that the oxidized portion forms a blocking oxide layer and a non-oxidized portion of the initial charge trap layer remains to form a final charge trap layer between the blocking oxide and the memory hole; and subsequent to forming the blocking oxide layer and the final charge trap layers, forming gate layers in the gate cavities by depositing gate material in the gate cavities via the access trench.

A semiconductor structure, comprising: a semiconductor-based substrate; a barrier layer disposed on the substrate; an electroplating seed layer disposed on the barrier layer; wherein the barrier layer is configured for mitigating atom diffusion from the seed layer into the substrate; a capping layer disposed on the seed layer and configured for resisting oxidation of the seed layer; and a solder bump disposed on the capping layer.

The disclosure relates to an integrated optical structure (10). The integrated optical structure (10) comprises an optical waveguide structure (11); a beam structure (12) which is suspended at a first distance to the optical waveguide structure (11), wherein the beam structure (12) comprises a first section (12A) of a first material and a second section (12B) of a second material, wherein the first material is a conductive material and the second material is a non-conductive material or a semiconductor; an electrode structure (21) arranged at a second distance to the beam structure (12); and an electrical contact structure configured to apply a voltage between the electrode structure (21) and the first section (12A) of the beam structure (12) inducing an electrostatic force acting between the electrode structure (21) and the first section (12A); wherein the beam structure (12) is designed to be elastically bent towards or away from the optical waveguide structure (11) by the electrostatic force causing a change in an optical property, in particular a phase, of an optical signal propagating through the optical waveguide structure (11).

A method for forming a memory structure for a 3D NAND flash memory, the method comprising:forming a layer stack over a substrate, the layer stack comprising an alternating sequence of gate layers and inter-gate spacer layers;forming recessed areas in a sidewall surrounding a memory hole in the layer stack by laterally etching back the gate layers relative to the inter-gate spacer layers from the memory hole;forming a discrete blocking oxide layer in each recessed area, wherein a thickness of each blocking oxide layer in a lateral direction is less than a depth of each recessed area in the lateral direction;conformally depositing a continuous liner layer on exposed surfaces in the memory hole, wherein the liner layer covers the blocking oxide layer in each recessed area;depositing a continuous sacrificial layer on the liner layer;etching back the sacrificial layer such that the liner layer is exposed outside the recessed areas and discrete portions of the sacrificial layer remain in the recessed areas;removing exposed portions of the liner layer while using the discrete sacrificial layer portions as an etch mask such that discrete portions of the liner layer covered by the discrete sacrificial layer portions remain in the recessed areas;removing the discrete portions of the sacrificial layer in the recessed areas;forming a discrete charge trap layer in each recessed area, wherein each charge trap layer is deposited on the discrete liner layer portion remaining in each recessed area by a first area-selective deposition process while using the discrete liner layer portion as a seeding layer;subsequent to forming the charge trap layers, depositing a tunneling oxide layer in the memory hole; anddepositing a channel layer on the tunneling oxide layer.

A target layer (25) that needs to be patterned is formed on a support substrate (26). An etch stop layer (27) and a first mask layer (28) are produced in that order on the target layer. According to embodiments of the invention, the first mask layer is patterned into a regular 2-dimensional array of openings (30). In a first directional etching step, the openings in the first mask layer are enlarged to thereby form a pattern of parallel first trenches (31) in the first mask layer (28). A second mask layer (32) is produced, possibly after thinning the patterned first mask layer. The second mask layer is patterned into the same regular array of openings (30) and thereafter the second mask layer is subjected to a second directional etching step, which enlarges the openings in the second mask layer to thereby form second parallel trenches (33) extending in a direction that crosses the direction of the first trenches,. The second directional etching also removes exposed portions of the first mask layer (28), so that the latter is eventually patterned into a pattern of pillars (34). After stripping the second mask layer (32) relative to said pillars, the pattern of pillars is transferred to the target layer (25).

This disclosure relates to droplet manipulation and sensing of a capacitive value of an electrode element used for the droplet manipulation. To this end, the disclosure presents an input-controlled oscillator circuit connectable to the electrode element. A node of the oscillator circuit is connectable to the electrode element. The oscillator circuit comprises an input stage connected to the node for providing a current or current pulse for charging an electrode of an electrode pair of the electrode element based on a control input. The oscillator circuit also comprises an oscillator core circuit connected to the node for cyclically discharging the electrode of the electrode element, to generate an oscillation with a frequency depending on the electrode element capacitance. The oscillator core circuit produces a voltage signal at an output node, which is based on a capacitance value of the electrode element and on the control input shifting the oscillation frequency.

A method for forming a microfluidic device includes: providing a substrate with electrodes having distal ends buried in the substrate; forming interconnect and dielectric layers; exposing the substrate surface by forming a hole through layers; filling the hole with sacrificial material; forming a composite layer with a first structure as a placeholder for a microfluidic compartment and a second structure enclosing the first structure; selectively etching the substrate to expose electrodes and filled hole surface; and removing sacrificial material, thereby forming a through-hole and a microfluidic compartment fluidically connected. The electrodes form a ring around the hole with the hole positioned within the ring boundary, enabling culturing of three-dimensional biological cell structures.

The disclosure relates to a NAND flash memory device (10). The NAND flash memory device (10) comprises: a semiconductor channel layer (12) extending along a first axis; a first dielectric layer (13) arranged above the semiconductor channel layer (12); a charge storage layer (14) arranged on the first dielectric layer (13); a second dielectric layer (15) arranged on the charge storage layer (14); and a plurality of gate structures (19) arranged above the second dielectric layer (15) and along the first axis; wherein each gate structure (19) comprises a first section (16) and a second section (17), wherein the first section (16) and the second section (17) are designed to have different work functions, and wherein the first section (16) and the second section (17) are arranged next to each other along the first axis.

The present disclosure relates to an isolator device, which is realized by employing non-reciprocal coupling of electromagnetic modes of a transmission line. A device and method are presented, which enable broadband isolation in a bandwidth of interest. This is achieved by controlling a multitude of controllable impedance elements, which are distributed along a transmission line, to generate a set of impedance modulations in the transmission line, and with the impedance modulations new tones in the electromagnetic waves propagating supported by a first subset of modes in the transmission line. Depending on the direction of propagation of the electromagnetic waves, the new tones may constructively or destructively interfere, respectively leading to or preventing parametric coupling from the first subset of modes to a second subset of modes of the transmission line.