imec

The disclosure relates to an integrated photonic chip (10) for optical coupling. The photonic chip comprises a substrate (11), a spot size converter (12) formed on a frontside surface of the substrate (11), a mirror (13) formed on the frontside surface of the substrate, and a meta-lens (14) formed in or on a backside surface of the substrate (11). The spot size converter (12) enlarges a diameter of a light beam in the photonic chip (10) from a smaller mode size to a larger mode size. The mirror receives the larger mode size light beam (15a) from the spot size converter (12), and reflects the light beam at an angle into the substrate. The meta-lens collimates the light beam (15b) reflected by the mirror and expanded when passing through the substrate, and outputs the collimated light beam (15c) towards the optical device.

A layer (28) is produced on an etch stop layer (27) formed on a support substrate. The layer is patterned by forming at least one opening (30) having upright sidewalls through the full thickness of the layer. The opening is enlarged by a sequence of directional etch steps wherein the angle of incidence of the applied plasma beam (8) is increased at every subsequent step compared to the previous step, so that the plasma beam impinges on the full height of the sidewall of the opening (30) or enlarged opening (31) at every step. Subsequent directional etch steps can be performed in the same scanning direction at each step, or the scanning direction can be changed at every step or combinations of equal and differing scanning directions can be applied, enabling thereby to obtain various shapes of pattern features. The adjustment of the angle of incidence enables a higher etch rate in the scanning direction and thereby a higher obtainable elongation compared to methods wherein repeated directional etch steps are performed applying he same angle of incidence at each step.

A stack of alternatingly applied etch stop layers (27) and mask layers (28) is produced on a target layer (25) present on a support substrate (26). The target layer is to be patterned according to a pattern comprising parallel line features (34,34'). The top mask layer is patterned according to a pattern of openings (30) and thereafter these openings are elongated by directional etching relative to the etch stop layer, to form a pattern of elongated openings (31,31'). This pattern is transferred to the subsequent mask layer (28) and in said subsequent mask layer, the elongated openings are further elongated by directional etching. This sequence is repeated down to the bottom mask layer. In said bottom mask layer, the pattern of openings has been elongated to a set of lines (34,34'), which are then transferred to the target layer. By repeating the elongation process a number of times, the obtainable elongation is increased compared to a process wherein only one directional etch step is applied.

The method comprises the steps of producing a stack of at least two layers (30,31,32) on a support substrate (25), by lithography and anisotropic etching, producing an opening (33) through said stack of at least two layers, and thereafter applying at least a first directional etching process step, using an etch beam configured to remove the material of one or more upper layers (32) of the stack selectively with respect to the layer or layers (30,31) directly underneath said one or more upper layers, to thereby enlarge the opening in the one or more upper layers (32) while essentially maintaining the in-plane dimensions of the opening in the layer or layers (30,31) directly underneath the one or more upper layers (32). The method can be applied to a stack of several layers which can be enlarged stepwise with respect to further underlying layers of the stack. Directional etching can be done in two opposite directions, possibly applying different etch chemistries in the two directions, to thereby enable the creation of complex three-dimensional structures without requiring expensive multiple lithography steps.

A pattern is produced in a die area (25) of a layer (30,33) formed on a support substrate (32) by at least two process sequences, each comprising a lithography step and an etch step, performed in adjacent subportions of the die area. One or more parallel line shaped features (28) of the pattern extend from the first subportion (25a) of the die area to the second subportion (25b), i.e. across the border (27) between the die areas. Mutually aligned and spaced apart first and second parts of the line features are printed in the respective process sequence steps and transferred to the layer in the form of negative or positive pattern features in the patterned layer, i.e. in the form of trenches (28'a,28'b) in the layer or in the form of lines separated by mutually aligned trenches (37a;37b). In either case, directional etching is thereafter applied to stretch the aligned trenches and thereby obtain the desired line features (28) extending from one subportion of the die area to the other subportion.

An imaging system (100) for medical imaging is provided. The imaging system comprises at least one training device (101), and at least one imaging device (102) operably coupled to the at least one training device (101), wherein the at least one imaging device (102) being configured to be attached to the skin of a person at a predefined location. In this regard, the at least one imaging device (102), in combination with the at least one training device (101), is configured to generate a first set of images corresponding to the predefined location, whereby the at least one training device (101) is configured to generate training data corresponding to the predefined location based on the first set of images. Furthermore, the at least one imaging device (102) is further configured to exclusively generate a second set of images corresponding to the predefined location based on the training data.

In an aspect there is provided a computer-implemented method for designing an IC comprising CFET devices. The method comprises obtaining a functional description of the integrated circuit, and generating, based on the functional description, a layout of the integrated circuit. The layout defines first and second cell rows extending in parallel in a horizontal direction of the layout, and having equal row heights in a vertical direction of the layout. Generating the layout comprises placing first and second cells of a standard cell library in the layout. Each cell has a cell height equal to the row height, and comprises first and second cell edges extending in parallel in the horizontal direction. Each cell further comprises at least one CFET device having an active pattern extending in the horizontal direction. Each cell further comprises at least one local interconnect (LI) disposed on the second cell edge and configured to connect to a top and/or bottom S/D of a CFET device of the cell. The first and second cells are placed in the first and second cell rows, respectively, such that: the first cell edge of the first cell aligns with a first row boundary, the first cell edge of the second cell aligns with a second row boundary, and the second cell edges of the first and second cells align with and abut each other along a third row boundary between the first and second cell rows. The placement of the first and second cells is constrained such that the local interconnects of the first and second cells do not overlap.

The invention relates to a bicelle entity comprising a bicelle structure with a rim and first and second amphiphilic compounds, the first having a longer hydrophobic chain, and at least one extension configured to bind a DNA origami envelope or its extension. It further relates to a DNA origami envelope adapted for such binding and to a complex formed by their assembly. A kit comprising the bicelle entity and the DNA origami envelope is also provided. The invention additionally concerns a hybrid pore device incorporating the complex with a solid-state pore. Methods are disclosed for manufacturing the complex by assembling the bicelle entity and DNA origami envelope, and for producing the hybrid pore device by integrating the complex with the solid-state pore.

A device for delivering charged entities into biological cells of a biological cellular material, comprising a microelectrode array for supporting the biological cellular material, the microelectrode array comprising individually addressable electrodes made of an electrically-conductive CMOS-compatible material having an oxide top layer, and the charged entities electrostatically coupled to the oxide top layer. The oxide top layer may be a native oxide top layer. The charged entities can be negatively charged entities electrostatically attached to positively charged carriers directly attached to the oxide top layer, or positively charged entities encapsulated in a negatively charged carrier electrostatically coupled to the native oxide top layer. The electrically-conductive CMOS-compatible material can be a metal, metal nitride, or metal oxide. Charged entities differing in their characteristics may be electrostatically coupled to distinct electrodes of the microelectrode.

A method for screening entities with different characteristics for their effect on biological cells of a biological cellular material, comprising: laterally constraining said entities having different characteristics in different locations of said biological cellular material, thereby preventing mixing of said entities having different characteristics; applying a transfection activation field to said different locations to allow said entities to be delivered into said biological cells, thereby allowing said entities to have an effect on said biological cells; and detecting said effect.