imec

The present disclosure relates to a semiconductor structure for a 3D DRAM comprising one 1T1C memory cell architecture and vertical bit lines. The semiconductor structure comprises a stack of semiconductor layers and dielectric layers alternatingly arranged along a first axis. Further, a first and second pillar of memory cells arranged displaced along a second axis and extending along the first axis through the stack. Each memory cell comprises a part of one of the semiconductor layers, and one transistor structure and one capacitor with a semiconductor channel and a metal gate that at least partly surrounds the semiconductor channel. The metal gates of memory cells in the same pillar are isolated from each other, and metal gates of memory cells that comprise parts of the same semiconductor layer form an integral metal structure.

A magnetic memory cell (100) includes a magnetic memory element (110) with at least one magnetic layer (111), configured to store information in distinct magnetization states. The magnetic layer (111) generates a stray magnetic field corresponding to its magnetization state. A magnetic field detection device (120) is positioned in proximity to the magnetic memory element (110) to detect variations in the stray magnetic field. The detection device (120) comprises a magnetostrictive (121) and piezoelectric (122) or a piezomagnetic (121) and piezoelectric (122) layer assembly. The magnetostrictive (121) or piezomagnetic (121) layer undergoes mechanical deformation in response to stray field changes, while the piezoelectric layer (122) generates an electrical signal representing the stored information. A writing mechanism (130) is configured to alter the magnetization state of the magnetic layer (111), enabling reliable data storage and retrieval.

A device (1) comprising: a first electrode (4) comprising a first electrode material of a type that, if oxidized by an oxidizing agent, is electrically insulating, a second electrode (2) comprising a second electrode material of a type that, if oxidized by said oxidizing agent, is electrically conducting, and a threshold switch layer (3) between the first electrode (4) and the second electrode (2), the threshold switch layer (3) comprising a material being switchable from an electrically insulating state to an electrically conducting state by a voltage between the first (4) and second electrode (2) crossing a threshold voltage, and a first electrode interface (40) between the threshold switch layer (3) and the first electrode (4), and a second electrode interface (20) between the threshold switch layer (3) and the second electrode (2), wherein the device (1) comprises the oxidizing agent suitable for being moveable between the first electrode (4) and the second electrode (2), the threshold switch layer (3) providing a passage for moving the oxidizing agent between the first electrode (4) and the second electrode (2).

This disclosure relates generally to a ferroelectric field effect transistor (FeFET) device suitable for probabilistic computing. The FeFET devices is usable as tunable probabilistic element in a network. A computing device comprising the network is also proposed. The FeFET device comprising a channel layer comprising an oxide semiconductor material and/or a 2D semiconductor material. The FeFET device further comprises a gate structure on the channel layer, the gate structure comprising a ferroelectric or anti-ferroelectric layer and a gate layer arranged on the ferroelectric or anti-ferroelectric layer. The gate structure is arranged between a source contact and a drain contact, which are additionally arranged on the channel layer.

Zusammenfassung wird geladen …

Zusammenfassung wird geladen …

Zusammenfassung wird geladen …

Zusammenfassung wird geladen …

The disclosure relates to a capacitive memory structure (10), comprising: a substrate (11); a first metallic layer (12) on the substrate; a ferroelectric material layer (13) on the first metallic layer (12); wherein the ferroelectric material layer (13) is electrically excitable to two polarization states, each polarization state representing a memory state of the capacitive memory structure (10). The capacitive memory structure (10) further comprises a second metallic layer (14) on the ferroelectric material layer (13); wherein the first metallic layer (12) and the second metallic layer (14) have different work functions.

Zusammenfassung wird geladen …