MediaTek

A primitive adaptive variable rate shading method includes generating a first absolute difference of depths in x direction (S202), generating a second absolute difference of depths in y direction (S204), adding the first absolute difference with the second absolute difference to generate a third absolute difference (S206), and setting the variable shading rate according to at least the plurality of thresholds, and the third absolute difference (S208).

A power management method includes: receiving an input video signal, wherein the input video signal comprises multiple frames; extracting at least one video feature from each of the multiple frames; performing a prediction operation according to the at least one video feature to generate a coarse prediction result, wherein the coarse prediction result is indicative of a value of a required power of the each of the multiple frames; and for the each of the multiple frames, adjusting a frequency of a video decoder (16, 206) according to a refined prediction result to drive the video decoder (16, 206), wherein the refined prediction result is an error calibrated version of the coarse prediction result.

A front-end-of-line, FEOL, floorplan (200) of an integrated circuit includes a plurality of FEOL components (202, 204, 206, 208), a non-rectangle-shaped empty region, a first FEOL dummy (218), and a second FEOL dummy (216). The non-rectangle-shaped empty region is located between the FEOL components (202, 204, 206, 208), and includes a first empty region (212) in a first direction and a second empty region (210) in a second direction perpendicular to the first direction, where the first empty region (212) has a first end connected to the second empty region (210). The first FEOL dummy (218) is inserted in the first empty region (212). The second FEOL dummy (216) is inserted in the second empty region (210). The first FEOL dummy (218) is separated from the second FEOL dummy (216) at the first end of the first empty region (212).

An oscillator circuit (100, 300) includes a first cross coupled pair (110, 310), a second cross coupled pair (120, 320), a resonant circuit (130) coupled between the first cross coupled pair (110, 310) and the second cross coupled pair (120, 320) and a first injection circuit (140-1, 340-1). The resonant circuit (130) includes a first node outputting a first voltage signal (VoscP) and a second node outputting a second voltage signal (VoscN). The first injection circuit (140-1, 340-1) is coupled to the first cross coupled pair (110, 310) and injects a first compensating current with a first predetermined phase to a predetermined node of the first cross coupled pair (110, 310).

The present invention provides a circuitry (200) including an output driver (210) and an ESD lock circuit (250). The output driver (210) includes a first transistor (M1) and a second transistor (M2), wherein the first transistor (M1) is coupled between an I/O pad (202) and a ground voltage, and the second transistor (M2) is coupled between the I/O pad (202) and a supply voltage. The ESD lock circuit (250) is coupled between the I/O pad (202) and the ground voltage, and is configured to generate a control signal to control the first transistor (M1) according to a voltage at the I/O pad (202).

A semiconductor structure is provided. The semiconductor structure includes a substrate, electronic devices, and an interconnection structure. The electronic devices are disposed on the substrate. The electronic devices includes first gate structures. The interconnection structure including a first interconnection-level conductive trace is located directly above the electronic devices. The first interconnection-level conductive trace has first openings for exposing at least one of the first gate structures.

A laminate non-planar radio-frequency, RF, choke device includes a first RF choke (200). The first RF choke (200) has a first winding structure including a plurality of first conductive traces (202, 204) and a plurality of first vias (206, 208). The first conductive traces (202, 204) are formed on a first layer (L1) and a second layer (L3) of a laminate. The first vias (206, 208) are formed between the first layer (L1) and the second layer (L3) of the laminate. The first vias (206, 208) are stitched in a winding direction through the first conductive traces (202, 204).

The present invention provides a circuitry (100, 200, 300) including a driver (114, 214), a band-pass filter (120, 220), a routing trace (130, 230) and at least one receiver (140, 144, 240_1 - 240_N, 244_1 - 244_N) is disclosed. The driver (114, 214) is configured to generate a first signal. The band-pass filter (120, 220) is configured to filters the first signal to generate a second signal. The second signal passes through the routing trace (130, 230) to generate a third signal. The at least one receiver (140, 144, 240_1 - 240_N, 244_1 - 244_N) is configured to receive the third signal to generate an output signal.

A read-only memory, ROM, (100) includes a first ROM cell (104), a second ROM cell (106), and a third ROM cell (102). The first ROM cell (104) is configured to store a first data value of a ROM code, and includes a first meta-oxide-semiconductor, MOS, transistor (114). The second ROM cell (106) is configured to store a second data value of the ROM code, and includes a second MOS transistor (116), wherein a source node of the second MOS transistor is electrically connected to a drain node of the first MOS transistor (114). The third ROM cell (102) is configured to store a third data value of the ROM code, and includes a third MOS transistor (112), wherein a drain node of the third MOS transistor (112) is electrically connected to a source node of the first MOS transistor (114).

A chip with electrostatic discharge protection is shown. The chip has an output driver and an electrostatic discharge (ESD) protection control circuit. The output driver has a first output driver transistor coupled between an input/output (I/O) pad of the chip and ground, and a second output driver transistor coupled between a power source and the I/O pad. The ESD protection control circuit has a first output terminal coupled to a control terminal of the first output driver transistor, to control the first output driver transistor for electrostatic discharge protection. The ESD control circuit is enabled in response to electrostatic disturbance at the I/O pad.