Beijing NAURA Microelectronics Equipment Patente

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The present disclosure discloses a seed layer formation method, a metal interconnection process method, and semiconductor process equipment. The seed layer formation method includes: depositing a metal seed layer on a substrate having vias or trenches on a surface thereof, stopping deposition of the metal seed layer when openings of the vias or trenches are reduced to an extent that metal ions cannot enter the vias or trenches, oxidizing the surface of the substrate to transform the metal seed layer on the surface of the substrate and a portion of the metal seed layer at the openings of the vias or trenches into metal oxides, placing the substrate in a solution capable of dissolving the metal oxides to dissolve the metal oxides on the surface of the substrate and at the openings of the vias or trenches, thereby reopening the openings of the vias or trenches. The present disclosure enables increased seed layer coverage at the bottoms and sidewalls of vias or trenches, preventing voids from forming during subsequent metal electroplating.

The present disclosure provides an auxiliary heating apparatus and a semiconductor heat treatment equipment. The auxiliary heating apparatus includes: a housing, which is capable of being disposed inside a semiconductor heat treatment equipment at a position near a process door during use, and is provided with a mounting cavity; a heating element, which is disposed in the mounting cavity; a cable, which is connected to the heating element, and is configured to be connected to a power supply; and a connector, a first end of the connector being connected to the housing, a second end of the connector being capable of extending out of the semiconductor heat treatment equipment during use, the connector being provided with a wiring channel communicating with the mounting cavity, and the cable being capable of extending out of the semiconductor heat treatment equipment through the wiring channel during use. The auxiliary heating apparatus provided in the present disclosure can increase the number of product wafers processed by a single machine and improve process quality of product wafers.

The present disclosure provides an ignition chamber of a semiconductor process equipment, a semiconductor process equipment, and a control method. In the ignition chamber of the semiconductor process equipment, one end of a communication pipeline and one end of a purge pipeline respectively communicate with a first end of a combustion chamber, and the other end of the purge pipeline is configured to communicate with a combustion-supporting gas source; and one end of an exhaust pipeline, one end of a first gas inlet pipeline, and one end of a second gas inlet pipeline respectively communicate with a second end of the combustion chamber opposite to the first end of the combustion chamber, the other end of one of the first gas inlet pipeline and the second gas inlet pipeline is configured to communicate with a combustible gas source, and the other end of the other of the first gas inlet pipeline and the second gas inlet pipeline is configured to communicate with the combustion-supporting gas source. The ignition chamber can solve the problem that when purging is performed on an existing ignition chamber before the existing ignition chamber is used for a wet oxidation process, part of oxygen flows into a process chamber and undergoes a dry oxidation process with a workpiece to be processed, which hinders the subsequent wet oxidation process.

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The present disclosure provides a position calibration apparatus and semiconductor process equipment. The position calibration apparatus includes a first light curtain assembly disposed within the process chamber of the semiconductor process equipment. The first light curtain assembly includes a first light curtain emitting end, a first light curtain receiving end, a second light curtain emitting end, and a second light curtain receiving end located on a first plane. The first light curtain emitting end is configured to emit a first calibration light to a workpiece within the process chamber, and the first light curtain receiving end is configured to receive the first calibration light and obtain a first projection of the workpiece on the first light curtain receiving end. The second light curtain emitting end is configured to emit a second calibration light to the workpiece, and the second light curtain receiving end is configured to receive the second calibration light and obtain a second projection of the workpiece on the second light curtain receiving end. An angle between a projection of the first calibration light and a projection of the second calibration light on the first plane is greater than 0°. A controller is configured to determine the position information of the workpiece based on the first projection and the second projection.

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The present disclosure relates to the field of semiconductor technology, and more particularly to a semiconductor process chamber and semiconductor process equipment. The semiconductor process chamber includes a chamber body, a carrier, a magnetron assembly, a bias magnetic field assembly, and a magnetic shielding member. The bias magnetic field assembly is located inside the chamber body and surrounds the carrier. The magnetic shielding member is located above the bias magnetic field assembly and is configured to guide the bias magnetic field above the bias magnetic field assembly, thereby reducing the magnetic field coupling of the bias magnetic field assembly and the magnetron assembly. The semiconductor process equipment includes the above semiconductor process chamber. The semiconductor process chamber and semiconductor process equipment can reduce or even avoid the magnetic field coupling superposition of the bias magnetic field assembly and the magnetron assembly, ensuring the uniformity of plasma concentration and sputtering rate on the target surface as much as possible, reducing or even avoiding abnormal fluctuations in voltage applied to the target, and ensuring the uniformity of the corrosion depth on the target surface and the uniformity of the magnetic thin film deposited on the surface of wafer.

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This application discloses a semiconductor process chamber and semiconductor process equipment. The semiconductor process chamber includes: a chamber body provided with an exhaust port; at least one first flow equalization plate disposed within the chamber body at a side close to the exhaust port and shielding the exhaust port, each first flow equalization plate being provided with a plurality of flow equalization holes; and a connection assembly connecting the chamber body and the first flow equalization plate, wherein the connection assembly is configured such that a distance between at least one first flow equalization plate and the exhaust port is adjustable. Embodiments of his application can maintain, as much as possible, a distance between quartz boats close to the exhaust port and the adjustable first flow equalization plate unchanged, thereby improving film thickness uniformity of silicon wafers in the quartz boats close to the exhaust port. In addition, by changing a number of first flow equalization plates, spacing between the first flow equalization plates, and a distance between the first flow equalization plates and the exhaust port, film thickness uniformity of silicon wafers in the quartz boats close to the exhaust port may be improved.

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The present disclosure provides a method of removing photoresist on a wafer and a semiconductor process device. During the process of removing the photoresist after ion implantation, a spectral intensity of an emitted light generated by a particular element in a chamber corresponding to different sampling moments is obtained; based on spectral intensities corresponding to two adjacent sampling moments, variation characteristic of spectral intensity at each sampling moment is determined; when the variation characteristic corresponding to a current sampling moment satisfies a preset condition, it is determined that the hardened layer removal process is near an end point and the wafer is controlled to descend from its current position toward a heating base according to a preset relationship to remove a hardened layer of the photoresist. By obtaining the spectral intensity of the emitted light produced by a particular element, and judging whether the hardened layer removal process is near the end point based on whether the variation characteristic of the spectral intensity satisfies the preset condition, the wafer is controlled to descend and the temperature is increased only when the hardened layer removal process is near its end point to avoid the hardened layer from popping at high temperature.

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The present disclosure provides a gate drive mechanism, a process chamber, and semiconductor processing equipment. The gate drive mechanism includes a first drive apparatus, a second drive apparatus, and a connector. The connector is configured to be connected to a gate and driving-connected to the first drive apparatus and the second drive apparatus. The first drive apparatus is configured to drive the connector to move along a first direction to allow the connector to drive the gate to move along the first direction. The second drive apparatus is configured to drive the connector to move along a second direction, the second direction intersecting with the first direction, to allow the connector to drive the gate to move along the second direction relative to the first drive apparatus. By providing the second drive apparatus, the gate drive mechanism of the present disclosure can allow the gate to move horizontally. Thus, the gate can cover the liner structure to realize sealing or separate the gate from the liner. While the seal performance of the gate is ensured, the collisions and scratches between the gate and the liner structure are effectively avoided.

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