LG Display Patente

A display device (100) can include a substrate (110) in which a plurality of sub pixels (SP1, SP2, SP3) is defined, a thin film transistor (120) disposed on the substrate (110), a planarization layer (PNL) disposed on the thin film transistor (120), an organic light emitting diode (130) disposed on the planarization layer (PNL) to correspond to each of the plurality of sub pixels (SP1, SP2, SP3), an encapsulation layer (140) disposed on the organic light emitting diode (130), a touch sensor layer (150), a touch protection layer (TPAS) disposed on the touch sensor layer (150), a black matrix (160) disposed between adjacent sub pixels on the touch protection layer (TPAS), and a plurality of color filters disposed on the touch protection layer (TPAS) to correspond to each of the plurality of sub pixels (SP1, SP2, SP3).

A display device (100) according to embodiments of the present disclosure may include a substrate (111) including a display area (DA) and a non-display area (NDA) outside the display area (DA), the display area (DA) including an upper display area (DA_TOP), a lower display area (DA_BOT), and a middle display area (DA_MID) between the upper display area (DA_TOP) and the lower display area (DA_BOT), and the non-display area (NDA) including a pad area (PA) closer to the upper display area (DA_TOP) than the middle display area (DA_MID), and a plurality of data lines (DL) arranged in the display area (DA). An n-th data line (DL(n)) among the plurality of data lines (DL) may include an n-th upper data line (DL(n)_TOP) arranged in the upper display area (DA_TOP) and extending in a first direction, an n-th lower data line (DL(n)_BOT) arranged in the lower display area (DA_BOT) and extending in the first direction, and an n-th bypass link line (DL(n)_BLL) passing through the middle display area (DA_MID) and electrically connecting the n-th upper data line (DL(n)_TOP) and the n-th lower data line (DL(n)_BOT), wherein n is a natural number greater than or equal to 1.

A display panel and a display apparatus are provided. The display panel and the display apparatus may each include an active area including a plurality of pixel areas and a plurality of scan circuit areas disposed between the plurality of pixel areas, a plurality of pixel circuits disposed in the plurality of pixel areas and configured to control emission of lights by a plurality of light emitting devices, based on an emission control signal, and a plurality of scan circuits disposed in the plurality of scan circuit areas and configured to generate a scan signal which is to be supplied to the plurality of pixel circuits, wherein the plurality of scan circuits may receive the emission control signal to generate the scan signal.

Provided is a gate driver (120, 620, 1520, 1620). The gate driver (120, 620, 1520, 1620) includes a light emission driver (EDV) comprising a plurality of light emission stages (EST1, ..., EST32) cascaded and configured to output a plurality of light emission control signals (EM1, ..., EM32) on the basis of a light emission start signal (EVST) and a plurality of light emission clock signals (ECLK1, ECLK2) and an output controller (SCTR1, SCTR2) comprising a plurality of stages cascaded and configured to output a plurality of pull-up control signals (PUS1, ..., PUS4) and a plurality of pull-down control signals (PDS1, ..., PDS4) on the basis of the plurality of light emission control signals (EM1, ..., EM32), a plurality of clock signals (CLK1, CLK2), a plurality of control clock signals (CCLK1, ..., CCLK4), a first power source (VGH), and a second power source (VGL) having a lower voltage level than the first power source (VGH), wherein the plurality of stages each includes a carry part (CRY1, ..., CRY4) configured to output a carry signal (CR1, ..., CR4) on the basis of at least one of the plurality of light emission control signals (EM1, ..., EM32), at least one of the plurality of clock signals (CLK1, CLK2), the first power source (VGH), and the second power source (VGL) and an output part (OUT1, ..., OUT4) configured to output the pull-up control signal and the pull-down control signal on the basis of the carry signal (CR1, ..., CR4), at least one of the plurality of control clock signals (CCLK1, ..., CCLK4), the first power source (VGH), and the second power source (VGL).

Implementations of the disclosure describe a display apparatus including a backlight unit including a light guide plate, a backlight sheet having a sheet hole formed therein, and a backlight light source element configured to emit light to the light guide plate, a liquid crystal panel positioned on a front surface of the backlight unit, and an optical module positioned on a portion of a back surface of the backlight unit, the portion overlapping the sheet hole. The optical module includes a prism structure including a first prism surface oriented toward the liquid crystal panel, a second prism surface perpendicular to the first prism surface, and an inclined surface provided between the first prism surface and the second prism surface, an optical element positioned adjacent to the second prism surface, and a compensation plate positioned between the first prism surface and the sheet hole, the compensation plate having a light extraction pattern.

Provided is a display device. The display device includes a display panel. The display panel includes a non-bending area including a display area and a non-display area configured to surround the display area, the display area is an area in which a plurality of light-emitting elements is disposed. The display panel further includes a bending area extending from one side of the non-display area. The display device further includes a polarizing plate disposed on the display panel in the non-bending area. The display device further includes a bonding layer disposed between the display panel and the polarizing plate in the non-bending area. The display device further includes at least one non-bonding pattern configured to overlap at least a part of an outermost peripheral portion of the polarizing plate and provided on one surface of the bonding layer.

An electroluminescent display device can include a substrate (100), a first electrode (400) on the substrate (100), a light emitting unit (500) including a light emitting layer disposed on the first electrode (400), and a second electrode (600) on the light emitting unit (500). A peak wavelength of a photoluminescence (PL) spectrum of the light emitting layer is shorter than a peak wavelength of an out-coupling OC curve of the light emitting unit (500) at a front viewing angle, and is longer than a peak wavelength of the OC curve of the light emitting unit (500) at a 45° side viewing angle.

A light emitting display device can include a plurality of lower uneven patterns on a surface of an insulating layer corresponding to a non-emission area and a plurality of upper uneven patterns on a surface of a black matrix. The light emitting display device can further include a light control uneven pattern on a surface of the insulating layer corresponding to an emission area. The shapes of the lower uneven pattern and/or the upper uneven pattern can be changed according to a subpixel region.

A display apparatus (100) comprising: a substrate (110) comprising a plurality of pixels having a plurality of subpixels (SP), wherein a first subpixel (SP1) of the plurality of subpixels (SP) comprises: an overcoat layer (113) disposed on the substrate (110); an upper color filter (UCF) on the overcoat layer (113); a pixel electrode (114) disposed on the upper color filter (UCF); and a reflective electrode (117) on the pixel electrode (114), wherein the reflective electrode (117) extends into a non-light emission area (NEA) between the plurality of subpixels (SP), the reflective electrode (117) in the non-light emission area (NEA) is partially disposed closer to the substrate (110) than the pixel electrode (114), and a refractive index of the upper color filter (UCF) is different from a refractive index of the overcoat layer (113).

A display apparatus comprising: a substrate including a display area in which a plurality of pixels are arranged and a non-display area around the display area, each of the plurality of pixels having a plurality of subpixels; a cathode electrode on the substrate, the cathode electrode disposed in the display area and in a part of the non-display area; an organic layer under the cathode electrode in the display area and in a portion of the non-display area; an organic layer shielding portion in the non-display area, wherein the organic layer is disposed in the portion of the non-display area without being disposed in the organic layer shielding portion; and a low-reflection structure overlapping at least a part of the organic layer shielding portion, the low-reflection structure between the cathode electrode and the substrate in the non-display area.

A display device may include a first display area (DA1), a second display area (DA2) including a plurality of first transmission areas (TA1), a first light emitting device (ED1) located in the first display area (DA1), a second light emitting device (ED2) located in the second display area (DA2) and disposed between the plurality of first transmission areas (TA1), a first passivation layer (650) disposed to surround a side surface of the first light emitting device (ED1), and a second passivation layer (700) disposed to surround a side surface of the second light emitting device (ED2).

A display device includes a display panel configured to display an image, a gate driver connected to gate lines of the display panel, and a data driver connected to data lines of the display panel. The display panel may operate in a period during which a display data voltage is stored based on three scan signals sequentially applied through three scan lines included in one gate line during one horizontal time, and a source node is initialized based on an initialization data voltage. A method of driving a display device is also disclosed.

Disclosed are a light emitting device and a light emitting display device including the light emitting device. The light emitting device includes a first electrode and a second electrode facing each other, a light emitting layer between the first electrode and the second electrode, a hole transport common layer between the first electrode and the light emitting layer, and an electron transport common layer between the light emitting layer and the second electrode, a first hole transport auxiliary layer and a second hole transport auxiliary layer provided sequentially between the hole transport common layer and the light emitting layer, and an electron blocking layer between the second hole transport auxiliary layer and the light emitting layer. A highest occupied molecular orbital (HOMO) energy level of the second hole transport auxiliary layer can be higher than a HOMO energy level of the first hole transport auxiliary layer and a HOMO energy level of the electron blocking layer respectively located on opposite sides of the second hole transport auxiliary layer.

A display apparatus includes a display panel having a pixel shift structure for three-dimensional (3D) implementation, a parallax film disposed on the display panel and including a plurality of lenses, and a bypass circuit configured to, when edge image data implementing an edge area of a two-dimensional (2D) input image is a clear type, output the edge image data of the clear type in a state where color map conversion corresponding to the pixel shift structure of the display panel is not applied, in a 2D mode.

Provided is a touch display device comprising: an active area (AA) including a first area (A1) in which a plurality of subpixels (SP) are disposed; a second area (A2) surrounded by the first area (A1); at least one hole (H1, H2) located in the second area (A2); a substrate (SUB); at least one transistor (T1, T2) disposed on the substrate (SUB); an encapsulation layer (ENCAP) disposed on the at least one transistor (T1, T2); a touch buffer layer (T-BUF) disposed on the encapsulation layer (ENCAP); at least one touch electrode connecting line (X-CL, Y-CL) disposed on the touch buffer layer (T-BUF); a touch insulating film (ILD) disposed on the at least one touch electrode connecting line (X-CL, Y-CL); at least one touch electrode (X-TE, Y-TE) disposed on the touch insulating film (ILD); at least one touch routing line (X-TL, Y-TL) connected to the at least one touch electrode (X-TE, Y-TE); and at least one crack detecting pattern (CDP1, CDP2) disposed at a periphery of the at least one hole (H1, H2).

The embodiments of the present disclosure may provide a display device (100) comprising: a substrate (SUB) including a display area (DA) capable of displaying an image, the display area (DA) including a first display area (DA1) having a plurality of transmissive areas (TA) and a second display area (DA2) positioned outside the first display area (DA1); a touch sensor metal (TSM) disposed in the first display area (DA1) and positioned outside the plurality of transmissive areas (TA); a first signal line (SL1) disposed in the first display area (DA1) and at least partially overlapping with a portion of the touch sensor metal (TSM); and a second signal line (SL2) disposed in the first display area (DA1) and at least partially overlapping with another portion of the touch sensor metal (TSM). Accordingly, the embodiments of the present disclosure may provide a display device (100) having an optical transmission structure that allows an optoelectronic device disposed below the display panel (110) to properly receive light while maintaining touch performance in an optical area (OA).

A display device can include a first substrate including a plurality of subpixels, a second substrate disposed on one side of the first substrate and including a pad portion, a bending portion that connects the first substrate and the second substrate, an etch stop layer disposed in the bending portion, a planarization layer disposed on the etch stop layer, a plurality of connection lines disposed on the planarization layer, and a first blocking pattern overlapping with at least one of the plurality of connection lines, the first blocking pattern being disposed between the etch stop layer and the planarization layer.

A display device can include first, second and third light-emitting elements disposed on a first substrate, an optical gap layer disposed on the first, second and third light-emitting elements, a second substrate disposed on the optical gap layer, first, second and third color filters disposed on the second substrate, first, second and third concave portions on a lower surface of the second substrate, and first, second and third lenses on an upper surface of the optical gap layer, in which the first, second and third lenses fill the first, second and third concave portions, respectively.

According to an aspect of the present disclosure, a wafer with light emitting elements, a method of inspecting light emitting elements, and a method of manufacturing light emitting elements are provided. The wafer includes a substrate, a plurality of light emitting elements above the substrate, a connector above the substrate and connected between the plurality of light emitting elements, and a support between the connector and the substrate. The plurality of light emitting elements are spaced apart from the substrate. Accordingly, the plurality of light emitting elements may be easily separated from the substrate individually in a subsequent process.

Disclosed are a display panel in which a unit pixel is divided into a wide-angle area and a narrow-angle area in which at least sub-pixel is disposed and light emission is individually and selectively performed, a display device including the same, and a manufacturing method thereof. A semi-cylindrical lens is disposed in the wide-angle area so as to cover a plurality of sub-pixels. Semi-spherical lenses are disposed in the narrow-angle area so as to cover sub-pixels respectively. Therefore, a direction of light emitting from a light-emitting layer is controlled by adjusting a refractive index of each of the lenses in the wide-angle area and the narrow-angle area. Thus, a viewing angle is controlled.

A thin film transistor substrate includes a first thin film transistor disposed having a polycrystalline semiconductor layer, a first gate electrode on the polycrystalline semiconductor layer, a first source electrode and a first drain electrode; a first gate insulating layer between the polycrystalline semiconductor layer and the first gate electrode; a second thin film transistor disposed having an oxide semiconductor layer on the first gate electrode, a second gate electrode on the oxide semiconductor layer, a second source electrode and a second drain electrode; an intermediate insulating layer disposed on the first gate electrode and under the oxide semiconductor layer; and a second gate insulating layer on the intermediate insulating layer and under the first source electrode, the first drain electrode and the second gate electrode.

An electroluminescent display device can include a substrate (100) including a first sub-pixel (R Sub-pixel) and a second sub-pixel (G Sub-pixel), a first electrode (400) in each of the first sub-pixel (R Sub-pixel) and the second sub-pixel (G Sub-pixel) on the substrate (100), a light emitting part (500) on the first electrode (400), and a second electrode (600) on the light emitting part (500). The light emitting part (500) includes a hole transport layer (HTL1, HTL2-2(R)), HTL2-1(G)), a first light emitting layer (EML(R)) disposed in the first sub-pixel (R Sub-pixel), a second light emitting layer (EML(G)) disposed in the second sub-pixel (G Sub-pixel), and an electron transport layer (ETL). The second light emitting layer (EML(G)) extends to the first sub-pixel (R Sub-pixel) and is disposed under the first light emitting layer (EML(R)). The hole transport layer (HTL1, HTL2-2(R)), HTL2-1(G)) is disposed between the second light emitting layer (EML(G)) and the first light emitting layer (EML(R)) in the first sub-pixel (R Sub-pixel).

This disclosure provides a display device and a method for driving the same. A display device includes a switching transistor (T1) turned on according to a scan signal (Scan1) applied through a scan line (SCAN1) to transmit a data voltage (Vdata) applied through a data line (DL1) to a capacitor (CST), a signal delay compensation circuit (CC) turned on according to the scan signal (Scan1) to compensate for a signal delay of the scan signal (Scan1) in response to a change in the data voltage (Vdata), a driving transistor (DT) configured to generate a driving current based on the data voltage (Vdata) stored in the capacitor (CST), and a light-emitting diode (OLED) configured to operate based on the driving current to emit light.

The present invention provides a display apparatus comprising a thin film transistor substrate and manufacturing method thereof, the display apparatus comprising: a base substrate; and a first thin film transistor and a second thin film transistor disposed on the base substrate and spaced apart from each other, wherein the first thin film transistor includes: a first oxide semiconductor layer; and a first gate electrode overlapping the first oxide semiconductor layer, and the second thin film transistor includes: a second oxide semiconductor layer; and a second gate electrode overlapping the second oxide semiconductor layer, wherein the first oxide semiconductor layer includes a first sub-oxide semiconductor layer having a crystalline structure, and the second oxide semiconductor layer has a first amorphous structure.

A display device (100) according to embodiments of the present disclosure may include a substrate (210), a plurality of light emitting devices (ED) disposed on the substrate (210) and positioned in a display area (DA), a plurality of column lines (CL) electrically connected to a first electrode (Ecl) of each of the plurality of light emitting devices (ED), a plurality of row lines (RL) electrically connected to a second electrode (Erl) of each of the plurality of light emitting devices (ED), a plurality of drivers (DRV) configured to drive the plurality of column lines (CL) and the plurality of row lines (RL), and a plurality of row connection lines (RCL) electrically connecting the plurality of row lines (RL) and the plurality of drivers (DRV). At least one of the plurality of row connection lines (RCL) may include a multi-wiring section (RCL_D) including two or more conductive layers vertically overlapping with each other with an insulating layer interposed therebetween.

The present disclosure relates to a display apparatus. The display apparatus has a display area and a non-display area surrounding the display area and comprises: a substrate (101); a first thin film transistor (200) and a second thin film transistor (300) disposed on the substrate; a light emitting device disposed on the first thin film transistor (200) and the second thin film transistor (300) and comprising a first electrode (E1), an emission layer (EL) and a second electrode (E2); and an encapsulation layer disposed on the light emitting device, wherein the first electrode (E1), the emission layer (EL) and the second electrode (E2) are formed to have a concave-convex structure in at least a portion of an emission region. The display apparatus can improve color viewing angle and light extraction efficiency.

A display device includes a substrate having a plurality of sub-pixels. A driving thin film transistor is disposed in each sub-pixel and includes a source electrode and a drain electrode. A first electrode is disposed in each sub-pixel and is electrically connected to the source electrode or the drain electrode. The first electrode comprises a first sub-electrode and a second sub-electrode spaced apart from each other. The first sub-electrode is electrically connected to the source electrode or the drain electrode through a first connection electrode. The second sub-electrode is electrically connected to the source electrode or the drain electrode through a second connection electrode. The arrangement allows selective electrical isolation of one of the sub-electrodes in response to a defect, while enabling continued operation of the other sub-electrode.

An organic light emitting display apparatus is disclosed, including a substrate having a plurality of subpixels; a pixel defining layer on the substrate and defining a light emitting opening; a partition wall on the pixel defining layer and defining a partition wall opening corresponding to the light emitting opening; and a light emitting element corresponding to the partition wall opening. The partition wall opening includes a center opening, a first partition wall opening extending in a first direction from the center opening, a second partition wall opening extending in a second direction overlapping the first direction, and a third partition wall opening extending in a third direction overlapping both the first and second directions. The plurality of subpixels is respectively disposed in the first, second, and third partition wall openings, enabling separation and arrangement of subpixels within a shared structure for efficient light emission without using a fine metal mask.

A light emitting display apparatus includes: a substrate including an active area and a non-active area adjacent to the active area; a planarization layer in the active area and a first part of the non-active area; a bank layer, a light emitting diode layer, and a first pattern disposed on the planarization layer; a second pattern and a dam disposed in a second part adjacent to the first part of the non-active area and having different heights.

A display device may include: a display area and a non-display area outside the display area; a light emitting diode disposed in the display area and on a substrate; an insulating layer covering the light emitting diode and disposed in the display area and the non-display area; lenses disposed in the display area and on the insulating layer; a stopper disposed in the non-display area and on the insulating layer; first flatness-enhancing patterns disposed between the display area and the stopper; and a planarization layer covering the lenses, the stopper and the first flatness-enhancing patterns. The non-display area may include a first non-display area at a first direction from the display area and a second non-display area at a second direction from the display area. The first flatness-enhancing patterns may be disposed in the first non-display area and include a convex pattern or a concave pattern.

A display apparatus may include a display panel including a plurality of non-bending areas and a bending area disposed between the plurality of non-bending areas; a first protection member disposed on the display panel in the bending area; a second protection member disposed on the first protection member; and a third protection member disposed on the second protection member.

A display device includes a substrate (111) including a first area (AAl) including first subpixels (SP1) and a transmissive part (TA), and a second area (AA") including second subpixels (SP2). A first transistor (T1) in the first area (A1) includes an oxide semiconductor active layer (ACT1), a gate electrode (G1), and first and second source-drain electrodes (SD11, SD12). A second transistor (T2) disposed in the first area (AA1) includes an oxide semiconductor active layer (ACT2) including first and second active layers (A21, A22), a gate electrode (G2), and first and second source-drain electrodes (SD21, SD22). A light-emitting element (135) is disposed in the first area (AA1). A third transistor (T3) is connected between the second transistor (T2) and the light-emitting element (135) and includes an oxide semiconductor active layer (ACT3) including first and second active layers (A31, A32), a gate electrode (G3), and first and second source-drain electrodes (SD31, SD32). The second active layer (A32) of the third transistor (T3) has a higher carrier mobility than the first active layer (A31) of the third transistor (T3).

A display device includes a display panel which includes a plurality of pixels and includes a substrate divided into a first area disposed at the center and a second area which encloses the first area; and a gate driver including a plurality of stages configured to supply a gate signal to the pixels through gate lines. Each of the plurality of stages included in the gate driver is disposed in a gate area which at least partially overlaps the first area and the second area, the plurality of pixels includes a plurality of first pixels disposed on the first area and a plurality of second pixels disposed on the second area, and the first pixels may be disposed in the first area at a first density and the second pixels may be disposed in the second area at a second pixel density which is lower than the first pixel density.

Discussed is an organic light emitting display device including a plurality of pixels, where red sub pixels and blue sub pixels of adjacent pixels are aligned in a first direction and are also aligned in a second direction, the second direction being a direction that intersects the first direction. Also, the green pixels of adjacent pixels are aligned in the first direction and are also aligned in the second direction. And the at least one green sub pixel of each pixel is disposed between the at least one red sub pixel and the at least one blue sub pixel of the each pixel, and the at least one green sub pixel is offset from the at least one red sub pixel and the at least one blue sub pixel in the first direction and the second direction in the each pixel.

The embodiments of the present disclosure relate to a display device (100), and more particularly, to a display device (100) capable of minimizing luminance variation caused by differences in wiring resistance within an optical area (OA) by differentially arranging a plurality of data connection lines (DCL1, DCL2), including a first connection line (DCL1) and a second connection line (DCL2) having a lower resistance than the first connection line (DCL1), in the optical area (OA).

A display device includes a first type heat dissipation layer having a high emissivity disposed on a lower surface of a display panel, an upper surface of an inner plate and/or a lower surface of the inner plate facing to a lower frame, and a second type heat dissipation layer having a lower emissivity disposed on the lower surface of the inner plate corresponding to a driving circuit board. The heat generated in the display panel can be efficiently dissipated to an outside and heat generated in the driving circuit board can be minimized from being transferred to the display panel.

The present disclosure provides a thin film transistor comprising a gate electrode, an active layer, a source electrode, and a drain electrode, wherein the active layer includes a first channel part overlapping the source electrode, a second channel part overlapping the drain electrode, and a connection part connecting the first channel part and the second channel part, and the connection part is a conductorized region. Additionally, a manufacturing method of the thin film transistor and a display apparatus including the thin film transistor mentioned above are disclosed.

A display device comprises a substrate, a data link line (DL), a power link line (VL), and a dummy pattern (DM). The substrate includes a display area in which pixels are arranged and a non-display area outside the display area. The data link line (DL) is positioned in the non-display area to deliver a predetermined signal to the pixels. The power link line (VL) is spaced apart from the data link line (DL) at a predetermined distance in the non-display area and delivers a predetermined power to the pixels. The dummy pattern (DM) is positioned between the data link line (DL) and the power link line (VL) in the non-display area.

A display apparatus and a display panel are discussed. The display apparatus includes a substrate (100), a transistor (TR2) disposed in each of a plurality of subpixels (SP) disposed in an active area (AA) of the substrate (100) and including a channel region (CH), an active layer (ACT) at the channel region (CH), and a gate electrode (G) overlapping the active layer (ACT), an external metal layer (LSb) disposed between the active layer (ACT) and the substrate (100) to overlap the active layer (ACT), and an internal metal layer (LSa) disposed between the active layer (ACT) and the external metal layer (LSb) to overlap the active layer (ACT) and the external metal layer (LSb). The plurality of subpixels (SP) include a first subpixel (SP1) and a second subpixel (SP2) configured to emit lights of different colors.

The present disclosure provides a thin film transistor substrate, a method for manufacturing the thin film transistor substrate and a display apparatus including the thin film transistor substrate. One example of the present disclosure provides a thin film transistor substrate comprising a buffer layer disposed on a base substrate and a plurality of thin film transistors on the buffer layer, wherein the plurality of thin film transistors comprise a plurality of active layers and a gate electrode overlapping at least a portion of each of the plurality of active layers, the buffer layer comprises a plurality of flat areas and a plurality of inclined areas alternately disposed with each other, and the plurality of active layers are spaced apart from each other and disposed in the plurality of flat areas.