NXP Semiconductors Patente

Described is a system, and method for monitoring a digital signature, comprising: generating keypairs K_st, each comprising an OTS public key and a seed-derived OTS private key, each associated with an index st; generating a binary tree, a root of which corresponds to a master public key and leaf-nodes of which to keypairs K_st, storing the seed, master public key and index st in a first processor and multiple nodes in a second processor, receiving a digital signature request; in response: downloading the seed, master public key, and index st, selecting the keypair K_st associated with the index st,computing an authentication path for K_st using the multiple nodes, creating a digital signature comprising the authentication path, deleting at least one node belonging to the authentication path, replacing the index st with st+1 in the first processor,and verifying the validity of the digital signature.

A method includes providing a circuit substrate including an active surface including one or more protrusions formed from a first material with a first melt temperature; coating each of the one or more protrusions with a second material having a second melt temperature that is less than the first melt temperature; and pressing a semiconductor device die onto the circuit substrate to form a circuit assembly, where the die includes one or more cavities aligned with the protrusions. Each die is plated with a third material having a third melt temperature that is greater than the second melt temperature. The method includes heating the circuit assembly at a selected temperature that is greater than or equal to the second melt temperature and that is less than the first and third melt temperatures to reflow the second material to form an intermetallic connection between the substrate and the die.

A transcendental math accelerator including a barrel shifter, a polynomial coefficient table (PCT), a polynomial interpolator, a normalization shifter, a result exponent table (RET), and exponent and sign logic (ESL). The barrel shifter shifts the input mantissa based on a specified function and the input exponent into a polynomial coefficient table index (PCTI) and an interpolation index. The PCT selects a coefficient set using the specified function and the PCTI. The polynomial interpolator calculates a preliminary output mantissa according to a polynomial equation using the coefficient set and the interpolator index. The normalization shifter shifts the output mantissa for a normalized floating-point format. The RET selects an exponent based on the function, the input exponent, and the PCTI. The ESL determines the output sign using the input sign and the function, and determines the output exponent based on the input exponent, the result exponent, and any shifts by the normalization shifter.

A distributed coherent radar, DCR (100), is disclosed that maintains synchronization between clocks of radars (102, 104). A determination is made that a first radar (102) is being started up or a mode of the first radar is being changed. A measured temperature indicative of a temperature of a digitally controlled crystal oscillator, DCXO (118,130), of the first radar is obtained based on the determination. A DCXO control setting of the DCXO of the first radar is identified based on the temperature to reduce a frequency drift of the DCXO of the first radar and frequency drift difference between the DCXO of the first radar and DCXO of a second radar (104). The DCXO of the first radar is adjusted with the DCXO control setting. The DCXO of the first radar and DCXO of the second radar indicates timing for clocks of respective radars and the adjustment maintains the synchronization between the clocks.

A capacitor cell includes two capacitor circuits and two cell nodes, where each capacitor circuit is located in a path between a circuit node of the cell and a respective cell node. The capacitor cell includes enabling transistors that are made conductive to enable the capacitance of the cell to be utilized by a circuit such as an oscillator for frequency control by an enable signal that has a voltage range between a low supply voltage and a high supply voltage. One of the enabling transistors is coupled between the cell nodes. Each of two enabling transistors includes a first current terminal coupled in a path to a respective cell node. The second current terminals of the two enabling transistors are biased at a bias voltage that is less than the high supply voltage when the enable signal is not asserted.

A method comprising, providing a plurality of first semiconductor dies on a surface of a carrier in a first region. Providing a second semiconductor die on the carrier in a second region. Etching a trench between each of the semiconductor dies, each trench extends into the carrier to a depth. Mounting a grinding foil on the carrier to attach each semiconductor die to the grinding foil. Back grinding a surface of the carrier to the depth. Applying a carrier foil to the back-grinded surface of the carrier. Either modifying the grinding foil or the carrier foil in a region aligned with the first region or use a de-taping module to press the grinding foil to the carrier foil. Then releasing, the plurality of first semiconductor dies from the grinding foil. The plurality of first semiconductor dies release from the grinding foil on removal of the grinding foil from the carrier.

A multi-level panel level package substrate is formed with a compact vertical balun for converting between single-ended and differential-ended signals, where the vertical balun includes a first non-phase-shifting conductive balun path element having one or more vertically aligned conductive structures formed in at least two package layers and connected between a first differential-ended signal balun node and a single-ended signal balun node; a second phase-shifting conductive balun path element having a plurality of conductive structures formed in at least two package layers and connected between a second differential-ended signal balun node and the single-ended signal balun node; and a single-ended contact element integrally formed with the single-ended signal balun node at a package layer location where the first non-phase-shifting conductive balun path element is directly, electrically connected to the second phase-shifting conductive balun path element.

A controller area network, CAN, transceiver comprising: CAN bus pins for connecting to a CAN bus; a TXD pin for receiving transmission data from a controller associated with the CAN transceiver; a driver circuit configured to receive the transmission data from the TXD pin and selectively apply a differential voltage signal to the CAN bus pins to selectively assert a dominant bit on the CAN bus in response to the transmission data; and a dominant control circuit configured to: detect assertion of a dominant bit on the CAN bus by sensing a current associated with the differential voltage signal applied by the driver circuit to at least one of the CAN bus pins; and enable a safe mode by inhibiting a flow of the current in response to detecting erroneous assertion of the dominant bit.

A system comprises: at least one processor core (110) supporting a virtual machine (120); an interface (150) configured for communication between the processor core (110) and a memory (160); a resource domain controller, RDC (130), configured to control access to the memory (160); and a secure enclave (140); wherein the resource domain controller, RDC (130), is configured by the secure enclave (140). A method for controlling access to a memory (160) and/or a device (170) assigned to a virtual machine (120) comprises: allocating, by a secure enclave (140), at least one memory region of the memory (160) to the virtual machine (120); assigning, by the secure enclave (140), a domain identifier to a processor core (110) supporting the virtual machine (120) and/or the device (170); and providing to the resource domain controller (130), by the secure enclave (140), the domain identifier and information identifying said at least one memory region allocated to the virtual machine (120).

Disclosed is a method of detecting a health state of a battery, in a power supply circuit having a charger and an energy storage device and for a pulsed load having a repetition interval, the method comprising: controlling a charging current of the energy storage device, by controlling an operating frequency of the charger, to recharge the energy storage device over the repetition interval at an optimised charger operating frequency; at least one of: comparing the optimised charger operating frequency with a threshold frequency, and comparing a rate-of-change of the optimised charger operating frequency with a threshold rate-of-change; and indicating an end-of-life state of the battery in response to at least one of: the optimised charger operating frequency exceeding the threshold frequency, and the optimised charger operating frequency exceeding the threshold rate-of-change. Other embodiments are disclosed.

A CAN XL transceiver configured to operate in a slow mode at a first bit rate and in a fast mode at a second bit rate higher than the first bit rate, the CAN XL transceiver comprising: a CAN bus connection for coupling the CAN XL transceiver to a CAN bus of a CAN XL network; a TXD pin for receiving transmission instructions from a controller associated with the CAN XL transceiver; and a network diagnosis module configured to: receive a CAN XL message from the CAN bus via the CAN bus connection; receive a pulse width modulation, PWM, signal from the TXD pin for indicating fast mode operation of the CAN XL transceiver; identify a test message in a data portion of the CAN XL message using the PWM signal; perform one or more test procedures on the CAN bus based on the test message; and output measurement results from the one or more test procedures.

The proposed method improves dynamic range utilization of the ADC unit by adjusting the amplifier gain and a reference gain level used to compensate the amplifier gain adjustment, based on a saturation status of the ADC unit. An update of the reference gain level is performed according to the gain change of the analog amplifier of the received signal and the recent ADCs saturation status. This provides a technical advantage by ensuring that the decoded signal remains steady when the amplifier gain is adjusted, thus maintaining signal integrity. This may help to achieve a more or less steady output in all circumstances. Resulting therefrom, the signal to be decoded is kept constant. This may be useful, when the received signal is strong and the ADC unit is saturated despite adaptation of gain.

The disclosure relates to a microphone input coupling circuit (500) comprising a sigma-delta ADC (501) and a DC control loop (508) connected to receive a digital output signal (506) from the ADC and configured to provide a DC correction signal (Dcorr) to a feedback DAC (507) of the ADC (501), the DC control loop (508) comprising a low pass filter (702) configured to extract a DC offset from the digital output signal to generate the DC correction signal (Dcorr), wherein the feedback DAC (507) is configured to apply a DC offset to the feedback signal (dac_out) according to the DC correction signal (Dcorr).

An asynchronous digital control circuit (200) includes a FSM state vector circuit (210) and a plurality of sequential logic circuits (300). A number of sequential logic circuits comprise: a first input (310) arranged to receive a sequential logic circuit analog event enable signal from the state vector circuit; a register (360) captures an occurrence of an analog event; a logic gate (370) gates an output of the register with a previous digital control circuit action (372) to provide mutually exclusive actions. A second analog input receives a respective captured analog event signal (320); and an analog event condition circuit (350) combines a plurality of analog input signals to form an analog event signal. An output is at least one action to control an analog circuit in response to the respective captured analog event signal and the sequential logic circuit analog event enable signal.

The present disclosure describes a method and a system for detecting fault injection attacks in a digital signature. The method comprises the steps of: initiating a first counter configured to count a number of generations of digital signature candidates, initiating a second counter configured to count a number of digital signature candidates which fail security checks, incrementing the first counter each time that a digital signature candidate is generated, selecting a size β and parsing the first counter in block intervals of said size β, performing at least one security check on each digital signature candidate generated, incrementing the second counter in response to a digital signature candidate failing at least one security check, and in response to the first counter being an integer multiple of β: assigning to the last completed block interval of said size β a third counter, such third counter configured to count the number of failed security checks in the last completed block interval, assigning to the last completed block interval of said size β a third counter, such third counter configured to count the number of failed security checks in the last completed block interval, comparing the third counter with a criterion based at least on a probabilistic threshold and on said size β. In response to the third counter not fulfilling the criterion the method detects that at least one fault injection attack has been performed.

An integrated circuit for an automotive bus system, comprising: a die; a reference terminal; an input terminal, wherein the reference terminal is spaced apart from the input terminal; and a routing path that comprises an electrostatic discharge mitigation circuit and also provides a galvanic connection between the input terminal and the reference terminal. The routing path comprises a conductive trace on the die; the conductive trace comprises a plurality of sections; the plurality of sections is arranged such that, in use, a first section has a current flow in a first direction, and a second section has a current flow in a second direction; the first direction is opposite to the second direction; and the first section is positioned adjacent to the second section, such that the first and second sections are inductively or electro-magnetically coupled to each other when the current flows through the first and second sections.

A method of remotely digitizing and updating a virtual card is proposed which is agnostic to emulation environments.

A computer implemented method of detecting one or more objects in an image. The method comprises processing a strip of the image, the strip comprising S lines of pixels of the image, with a backbone model to extract backbone features. The backbone features are processed with a neck model to enhance and/or fuse the backbone features and thereby produce neck features. The neck features are processed with a head model to detect one or more objects in the image. The step of processing a strip of the image is repeated until the whole image is processed.

A system and method of detecting fault in current sensing of an electric motor controller including a current imbalance detector and a fault detector. The electric motor controller includes a control loop using feedback current values for generating phase current signals driving an electric motor, a current sensor that provides sensed current signals indicative yet independent of the phase current signals, and an estimator that monitors operating parameters of the electric motor and provides estimated current signals. Imbalance occurs when a sum of sensed current signals is outside a threshold of a constant value. The fault detector uses the sensed current signals and the estimated current signals to determine phase criteria markers indicative of phase symmetry and compares each phase criteria marker with an average criteria marker to identify a faulty phase current sensor. The criteria markers are based on deviations between sensed and estimated current signals in each phase.

One example discloses a module, including: an e-switch configured to be coupled to a power supply and a load; a controller coupled to the e-switch; wherein the controller is configured to determine if the e-switch was intentionally or unintentionally shutdown; wherein the controller is configured to command the e-switch to send a first power level to the load if the e-switch was intentionally shutdown; wherein the controller is configured to command the e-switch to send a second power level to the load if the e-switch was unintentionally shutdown; wherein at a first time the second power level is less than the first power level; and wherein if at a second time the second power level is greater than the first power level, the controller is configured to command the e-switch to stop sending power to the load.

The present disclosure relates to a method of providing an early warning of thermal runaway in a battery cell, the method comprising: monitoring, over time, a temperature of the battery cell; monitoring, over time, a real part of an impedance of the battery cell for a plurality of test signal frequencies by: applying a plurality of test signals to the battery cell at each of a plurality of discrete time intervals, each of the plurality of test signals having a corresponding one of the plurality of test signal frequencies; and determining, for each applied test signal, the real part of the impedance of the battery cell; determining, over time, whether the temperature of the battery cell is increasing; determining, over time, whether the real parts of the impedances corresponding to the plurality of test signal frequencies have converged; and providing a first warning if the real parts of the impedances at the plurality of test signal frequencies have converged and the temperature has been increasing for a first predetermined number of the discrete time intervals.

A multiple core processing system as described herein for optimizing broadcast operations includes multiple first-level (L1) caches, a distributed second-level (L2) cache system including multiple L2 cache partitions each having a unique identifier, and a routing network that enable communications between the L1 and L2 caches. Each L1 cache sends a request message with a memory address to a targeted L2 cache partition. When rejected, the L1 cache resends the request only in response to a retry message that incorporates an identifier that matches a locally stored identifier. Each L2 cache partition sends a reject message to a requesting L1 cache when busy and later broadcasts a retry message that incorporates its identifier when not busy. The L1 cache predetermines the identifier of the target L2 cache partition when sending the request, or each L2 cache partition incorporates its identifier in the reject message.

The present disclosure relates to a key fob for accessing a vehicle, wherein the key fob comprises: a secure element comprising: a microcontroller unit; a non-volatile memory module communicably coupled to the microcontroller unit, the non-volatile memory module configured to store a first system software for running a first vehicle access application and a second system software for running a second vehicle access application; and one or more secure hardware blocks communicably coupled with the microcontroller unit; wherein the key fob is configured to operate in a first mode or second mode, wherein, in the first mode, the microcontroller unit is configured to: activate the secure hardware blocks; operate at a first clock speed; and boot the first system software; and in the second mode, the microcontroller unit is configured to: inhibit activation of one or more of the secure hardware blocks and/or operate at a second clock speed that is lower than the first clock speed; and boot the second system software.

An integrated patch antenna with a plurality of layers, comprising: a reference plane, positioned in a first layer, wherein the reference plane is configured to provide a connection to a reference voltage; a driving patch, positioned in a second layer, wherein the first layer is separated from the second layer by a plurality of layers, such that: the driving patch is positioned above the reference plane, a volume between the reference plane and the driving patch defines a first resonant cavity, and the integrated patch antenna comprises a plurality of layers within the first resonant cavity. The integrated patch antenna also comprises a feed line configured to connect the driving patch to a transmitter or receiver, comprising: a first conductive via positioned in the first resonant cavity, galvanically connected to the driving patch; and a first conductive trace, galvanically connected to the first conductive via.

An apparatus and method for beam steering an antenna array for a MIMO receiver. A signal output and at least one phase shifted output is produced for each antenna element in a MIMO antenna array that receives a phase shift control input, where the at least one phase shifted output is phase shifted relative to the signal output based upon the phase shift control input. A plurality of combined signals is produced for input to a MIMO receiver, where each combined signal is produced for a group of antenna elements and where each respective combined signal includes a combination of: a signal output of a first antenna element and a phase shifted output of at least a second antenna element. A phase shift control input is produced that creates a reduced antenna gain pattern in a direction of a detected strong signal for each respective pair of antenna elements.

Aspects of this disclosure are directed to, DCO circuits and methods. The DCO, comprise: an inductance-capacitance, (LC), resonant circuit having a first branch connected in parallel with a second branch, each branch comprising a capacitor and an inductive-element connected in series with the capacitor; a first transistor connected, by its main terminals, across the capacitor of the first branch; a second transistor connected, by its main terminals, across the capacitor of the second branch; and a biasing current source arranged and connected to provide current to the resonant circuit; wherein a control terminal of the transistor of each branch is connected to a node between the respective capacitor and respective inductive-element of an opposite branch, and wherein at least one of the first transistor and second transistor is controllable to adjust a transconductance of the respective branch.

There is provided boundary cells arranged to form a boundary between a first power domain and a second power domain. Each power domain has an associated power rail. The boundary cells physically and electrically isolate functional cells of the first power domain from functional cells of the second power domain. Each boundary cell comprises a first well tap having a first conductivity type provided within a first region of a substrate, wherein the first well tap is electrically connected to a ground rail, and a second well tap having a second conductivity type provided within a second region of the substrate, wherein the second well tap is electrically connected to the power rail of the first power domain. The power rails of each power domain extend partially across the boundary cell, the first power rail being physically and electrically isolated from the second power rail.

In accordance with a first aspect of the present disclosure, a secure element for use in a battery system is provided, the secure element comprising: a seal interface configured to couple the secure element to a seal included in the battery system, wherein the seal is configured to physically protect a battery unit of the battery system; a storage unit configured to store a reference value indicative of a closed state of the seal; a monitoring unit configured to monitor an electrical characteristic of the seal and to compare said electrical characteristic of the seal with the reference value. In accordance with a second aspect of the present disclosure, a corresponding method of operating a secure element is conceived.

In accordance with a first aspect of the present disclosure, a near field communication (NFC) device is provided, comprising: an NFC antenna; a first transmitter operatively coupled to the NFC antenna; a second transmitter operatively coupled to the NFC antenna; a controller operatively coupled to the first transmitter and the second transmitter; wherein the NFC antenna comprises a first part and a second part, the first part extending from the first transmitter to a ground connection of said NFC antenna, and the second part extending from said ground connection to the second transmitter; wherein the controller is configured to cause the first transmitter to feed the first part of the NFC antenna while the second transmitter does not feed the second part of the NFC antenna, and to cause the second transmitter to feed the second part of the NFC antenna while the first transmitter does not feed the first part of the NFC antenna. In accordance with a second aspect of the present disclosure, a corresponding method of operating an NFC device is conceived.

The disclosure relates to methods of training an object detecting and tracking model. The object detecting or tracking model is trained by receiving (S201) location telemetry data transmitted by an object within the field of view and receiving (S203) sensor data from a sensor and derives object data therefrom. The object detecting and tracking model derives the ground truth from the location telemetry data and uses that to train the model. The disclosure further discusses related systems

The present disclosure relates to a communication device, wherein the communication device is configured to receive a CAN frame via the CAN interface, the CAN frame comprises a first stream packet comprising a first stream data field and a first header, which comprises a plurality of common header fields and a plurality of first header fields, wherein the processing unit is configured to create a second stream packet corresponding to the first stream packet except for the first header fields, such that the second stream packet comprises the first stream data field and a second header comprising the common header fields and, in place of the first header fields, at least one second header field, wherein the processing unit is configured to create an Ethernet frame comprising the second stream packet as a payload, wherein the processing unit is configured to create a destination MAC address and a source MAC address of the Ethernet frame based on at least one of the plurality of first header fields, and wherein the communication device is configured to send the Ethernet frame via the Ethernet interface.

The present invention relates to a Controller Area Network, CAN, device comprising: a data, RD, interface, a processing unit, and a bus interface for coupling to a CAN bus, wherein the CAN device is configured to receive first data via the RD interface, wherein the processing unit is configured to create a series of CAN frames referred to as a frame series based on the first data such that the frame series comprises a start CAN frame and at least one further CAN frame referred to as at least one follower CAN frame, wherein the processing unit is configured to distribute the first data among the CAN frames of the frame series, wherein the processing unit is configured to create the start CAN frame such that the start CAN frame comprises an identifier that represents a priority value referred to as the start priority value within a predefined first value range, wherein the processing unit is configured to create each follower CAN frame such that each follower CAN frame comprises a respectively associated identifier that represents a priority value referred to as a follower priority value within a predefined second value range, wherein the second value range is less than the first value range, and wherein the CAN device is configured to transmit the CAN frames of the frame series via the CAN interface such that the at least one follower CAN frame follows the start CAN frame.

The disclosure relates to a frequency doubler circuit (100) comprising: first and second input terminals (101, 102) for receiving an input voltage signal (IN+, IN-) at a first frequency; a first pair of transistors (103a, 103b) connected between a supply line (104) and a first node (105); a second pair of transistors (106a, 106b) connected between a common line (107) and a second node (108), the first and second pairs of transistors (103a, 103b, 106a, 106b) having gates coupled to the respective first and second input terminals (101, 102); an output matching circuit (109) having first and second output terminals (110, 111) for providing an output voltage signal (OUT+, OUT-) at a second frequency; a first common gate transistor (112) connected between the first node (105) and a first input (113) of the output matching circuit (109); and a second common gate transistor (114) connected between the second node (108) and a second input (115) of the output matching circuit (109).

A method for performing ultra-wide-band (UWB) radio-frequency (RF) frame validation, wherein an UWB frame comprises: a synchronisation header (SYNC) field suitable for synchronisation between a transmitter and a receiver, and a scrambled timestamp sequence (STS) suitable for providing additional integrity and security for ranging measurements. The method comprises: receiving a SYNC channel impulse response (CIR) of an UWB frame; receiving an STS CIR of the UWB frame; comparing peak amplitude values of the SYNC CIR and the STS CIR. If a difference between the peak amplitude values of the SYNC CIR and the STS CIR is greater than a predetermined magnitude difference threshold, then: rejecting the UWB frame; else: comparing polarities of the SYNC CIR and the STS CIR. If the polarities of the SYNC CIR and the STS CIR are different, then rejecting the UWB frame; else: accepting the UWB frame.

A method is described which monitors hypervisor execution and controls hypervisor features to enforce a confidential computing environment.

A method (800) for adapting a supply voltage of a device comprises: configuring (810) a change in an operational state of the device; measuring (820) a temperature of the device; determining (830) a supply voltage level for the device to operate in the configured operational state; and adapting (840) a supply voltage of the device in dependence on at least the measured temperature and the supply voltage level for the device to operate in the configured operational state.

A serial communication device for I2C or I3C communication and method is described. The serial communication device includes a serial data (SDA) terminal coupled to a series arrangement of a SDA filter and a SDA programable delay circuit. The serial communication device includes a serial clock (SCL) terminal coupled to a series arrangement of a SCL filter and a SCL programable delay circuit. In response to detecting a start condition, a first count value is generated by a first counter during a first time duration corresponding to a SDA filter propagation delay time, a second count value is generated by a second counter during a second time duration corresponding to a SCL filter propagation delay time. A delay of at least one of the SDA programable delay circuit and the SCL programable delay circuit determined from the first count value and the second count value.

An ESD circuit includes a clamp that can be used for both discharging ESD current and for over voltage protection. The integrated circuit includes a signal IC terminal that is coupled to the clamp through a resistor circuit. In response to an over voltage condition of the signal IC terminal, the clamp becomes conductive to make conducive a discharge path between the signal IC terminal and a supply voltage rail to conduct charge to reduce the over voltage condition. The discharge path is through the resistor and through the clamp. A transistor is coupled to the control terminal of the clamp and has a control input coupled to receive an ESD trigger signal. In response to a detected ESD event, the trigger circuit is asserted to make the transistor conductive to pull the voltage of the control terminal of the clamp towards a voltage of the supply voltage rail to make conductive the discharge path to discharge ESD current between the IC terminal and the supply voltage rail.

The disclosure relates to a computer-implemented voice recognition method and system, in which an audio signal (104) is provided to an acoustic model (100), processed to determine phonemes (202) from the audio signal (104), which are provided to a decoding graph (201) comprising a plurality of search paths corresponding to sequences of phonemes and an output (203) from the decoding graph (201) determined according to one of the plurality of search paths, wherein the plurality of search paths in the decoding graph (201) comprises a plurality of command search paths defining a plurality of sequences of phonemes for a respective plurality of voice commands and a watermark search path defining a sequence of phonemes for a watermark of the decoding graph (201).

The disclosure relates to measurement of a change in distance over time using radar. Example embodiments include a computer-implemented method of measuring a change in distance over time using FMCW radar signals, the method comprising: transmitting (1701) a series of chirp signals; receiving (1702) a series of reflected chirp signals from a target; and processing (1703, 1704, 1705) the series of reflected chirp signals to determine a change in distance to the target over time from phase differences between the transmitted and received chirp signals, wherein phase differences between successive frames (1301, 1302) derived from the received chirp signals are fitted to a function (1303) to correct for any phase differences greater than 2π between the successive frames (1301, 1302).