NXP Semiconductors Patente

A radar apparatus includes a correlator that operates on sequences of Lc signal values to generate a correlation r[n]. Based on an object detection or map data, only certain block(s) of r[n] of length Lc/d (d is an integer) are generated from corresponding signal value blocks, or are selected for subsequent processing. Computation times for range and velocity are significantly reduced as a result. The radar apparatus adapts by generating or selecting different block(s) or r[n] based on a different object detection or different map data.

An integrated circuit for a wireless charging receiver, the integrated circuit comprising: a differential input for receiving a differential voltage from an antenna of the wireless charging receiver, the differential input comprising a first input terminal and a second input terminal; a variable resistor coupled between the first input terminal and the second input terminal; a rectifier coupled to the differential input and configured to: receive the differential voltage; and output a rectified voltage; a control circuit coupled to the rectifier and the variable resistor, wherein the control circuit is configured to: monitor a rise time of the rectified voltage; and set a resistance value of the variable resistor based on the rise time.

The disclosure relates to duty cycle correction of digital data in a CML transmission system. Example embodiments include a CML transmission system (600) comprising: a transmission channel (601) with a transmitter (602) connected to a first end (604) and a receiver (603) connected to a second end (605). A control system (606) is configured to measure a duty cycle of a received signal from the receiver (603) and provide first and second termination resistance control signals (RSTP, RSTN) to respective first and second adjustable receiver termination resistances (501, 502) of the receiver (603) to adjust a balance of the termination resistance control signals (RSTP, RSTN) dependent on a comparison between the measured duty cycle and a nominal duty cycle.

A circuit assembly includes a packaged electronic device having an RF (radio frequency) contact and a shield contact. The circuit assembly further includes a substrate coupled to the packaged electronic device and at least partially containing an inner conductive structure electrically coupled to the RF contact and an outer conductive structure electrically coupled to the shield contact, the inner conductive structure and the outer conductive structure forming a vertical coaxial structure through the substrate. The circuit assembly still further includes a waveguide antenna electrically coupled to the coaxial structure on a side of the substrate opposite the packaged electronic device. Further embodiments are directed to a device suitable for use in a circuit assembly as described above.

In accordance with a first aspect of the present disclosure, a vehicle access system for use in a vehicle is provided, the vehicle access system comprising: a detection unit configured to detect whether at least one external access device is present within a predefined area around the vehicle; and a controller operatively coupled to the detection unit, wherein the controller is configured to control a level of activity of the detection unit in dependence on a predetermined probability that the vehicle will be accessed within predefined time slots. In accordance with further aspects of the present disclosure, a corresponding operating method is conceived, and a computer program for carrying out said method is provided.

A method (300) for authenticating a transaction comprises: identifying (425, 535) a first transaction made at a first physical location that includes a first transaction time; receiving (205) a request for a second transaction; and identifying (210, 240) the requested second transaction is made at a second physical location that includes a second transaction time. The method further comprises; computing using encryption (235) a distance between the first and second physical location; computing (320) a minimum speed to transition between the first and second location in a delta time between the first transaction time and the second transaction time; comparing (330) the computed minimum speed to a threshold; and determining (335) whether the requested second transaction is authentic in response to comparing the computed minimum speed to the threshold. In this manner, determining a distance, time delay and therefore minimum speed between two consecutive transactions provides an additional authentication using encryption.

Dual edge synchronizers and methods of using dual edge synchronizers to filter out glitches are provided. Dual edge synchronizers include a first two flip-flop synchronizer, a second two flip-flop synchronizer in parallel with the first two flip-flop synchronizer, a plurality of gates that receive the outputs from the two synchronizers and implement a gate logic to generate an enable signal and a D input signal that are passed to a latch. The latch generates a dual edge synchronizer output signal, wherein a change in the state of the D input signal is passed as a change in the state of the dual edge synchronizer output signal when the enable signal is high and is not passed as the dual edge synchronizer output signal when the enable signal is low.

One example discloses a clock generation circuit, including: a clock base circuit configured to receive a clock request (req_pulse) signal having a pulse width; wherein the clock base circuit is configured to generate a clock output signal having a predetermined number of cycles based on the pulse width of the clock request (req_pulse) signal.

Circuits and methods are disclosed that include a boost rail having a first voltage and an electrostatic discharge (ESD) rail having a second voltage that is less than the first voltage. An ESD protection circuit may include a trigger circuit configured to determine an ESD event on the boost rail and to selectively activate a clamp circuit to shunt current from the ESD rail to a power supply terminal in response to the ESD event. The circuit may include a first voltage drop circuit having a first configuration and coupled between a first power supply terminal and the boost rail to provide the first voltage and a second voltage drop circuit having a second configuration and coupled between the ESD rail and one of the boost rail or the first power supply terminal.

The present disclosure relates to a radar system and related method, where the radar system includes radar front-end circuitry having a leader device and a follower device. The leader device includes first processing circuitry configured to output, at a first time, an initial LO signal via a first LO interface perform a first calibration process, including calibration of first TX/RX circuitry, based on a first calibration schedule and based on the first time. The follower device includes a second processing circuitry configured to determine the first time at which the first LO signal is output by the leader device and perform a second calibration process, including calibration of second TX/RX circuitry, based on a second calibration schedule and based on the first time.

The present disclosure relates to a radar system and related method, where the radar system includes radar front-end circuitry having a leader device and a follower device. The leader device includes first processing circuitry configured to output, at a first time, a first signal pulse via a first IO interface and perform a first calibration process, including calibration of first TX/RX circuitry, based on a first calibration schedule and based on the first time. The follower device includes a second processing circuitry configured to determine the first time at which the first signal pulse is output by the leader device and perform a second calibration process, including calibration of second TX/RX circuitry, based on a second calibration schedule and based on the first time.

The present disclosure relates to an Ethernet device being configured to change stepwise from an idle state to a full active state, wherein the Ethernet device being configured to either detect a predefined signal during an arbitration cycle in order to perform a final step to fully activate the Ethernet device or otherwise to either maintain in an intermediate state or to change back to the idle state. The present disclosure also relates to a method for the Ethernet device.

Improved hearing systems and methods are disclosed herein. In one example embodiment, a hearing system includes memory device(s), audio input device(s) configured to receive audio input signals including audio information arising from a plurality of sound sources, audio output device(s), and processing device(s). During an inference mode, the processing device(s) are configured to operate in accordance with the first neural network to generate intermediate output signals that, to a higher degree than in the audio information, reflect or emphasize at least one desired sound source component of the audio information arising from a desired one of the sound sources of the plurality of sound sources determined to be the desired one of the sound sources at least indirectly based upon a first undershot angle evident from the audio information. The audio output device(s) are configured to generate audio output signals based at least indirectly upon the intermediate output signals.

A delta sigma modulator includes a comparator circuit with an output that provides a digital signal which is indicative of a voltage of an a signal received at its input terminal. The modulator includes a continuous-time path from the modular input terminal to an input terminal of a comparator of the comparator circuit. The modulator includes a first feedback loop connected to a first integrating node of the path that provides a first comparator circuit output controlled feedback current and a second a second feedback loop that provides a second comparator circuit output controlled feedback current to a second integrating node of the path that is connected to the input terminal of the comparator and connected to a capacitor.

A method is provided which enables dynamic loading to be performed on an MCU.

A high power switch is described with improved avalanche breakdown voltage using well blocking. In an example, a semiconductor switch includes a substrate of a first type, a deep well of a second type over the substrate, an inner well of the first type over the deep well, a gate over the top surface and over the inner well, a source over the inner well having a contact of a second type coupled to the gate through the inner well, and a drain over the inner well having a contact of the second type coupled to the gate through the inner well. An inner moat is outside of the inner well and over the deep well surrounding the gate, the source, the drain, and the body electrode. An outer moat is outside the deep well over the substrate and surrounding a contact well.

One example discloses a process sensor, including: a set of process sensitive current sources having a set of transistors embedded in a semiconductor device; wherein the process sensitive current sources are configured to generate an output current that varies in response to a process parameter shift of the transistors in the semiconductor device; a ring oscillator coupled to receive the output current from the set of process sensitive current sources; wherein the ring oscillator is configured to generate an output signal having a frequency that varies in response to the output current.

A method of forming a semiconductor device with an embedded die is provided. The method includes forming a cavity at a first major side of a glass substrate. A reduced thickness portion of the glass substrate remaining between a bottom of the first cavity and a second major side of the glass substrate. A plurality of first through glass vias (TGV) and a plurality of second TGV are formed through the reduced thickness portion of the glass substrate. The glass substrate is placed over a semiconductor die having a plurality of copper pillars formed on respective bond pads. The semiconductor die is positioned within the first cavity such that the plurality of copper pillars extend through respective first TGV. A bonding material is injected into the cavity such that space remaining between the glass substrate and the semiconductor die is substantially filled.

A priority based prefetch by a memory controller is disclosed. A prefetch of data of a low priority master is suspended when a data request associated with a high priority master indicated by a master identification is to be performed. The suspension includes storing a saved state of the prefetch, performing the prefetch of data of the high priority master, and resuming the prefetch of data of the low priority master when the prefetch of data of the high priority master is completed.

A system and method for processing received radar signal reflections is presented. A range bin matrix is generated from a range-Doppler antenna cube generated using the reflections of the plurality of transmitted radar signals. A a first range bin array that includes a plurality of values associated with different Doppler bins is determined and an offset range bin array that includes the plurality of values of the first range bin array offset by a number of Doppler bins is generated. A first Doppler bin in the first range bin array and the offset range bin array that each include non-zero values is determined and the value associated with the first Doppler bin in the first range bin array is set to a value of zero to generate a corrected range bin array. The radar system determines an estimated direction of arrival using the corrected range bin array.

A test tone generator (467) for a receiver (356) comprises a dual-modulus divider circuit (415) arranged to receive a local oscillator, LO (367), and generate a tone therefrom in a series of pulses (417) at an offset frequency from the LO signal; at least one counter (420) connected to an output of the dual-modulus divider circuit and arranged to count a number of pulses (417) and reset the dual-modulus divider circuit when a count threshold is reached. A tone shaping circuit (430) converts the series of pulses into an output test tone (432) The dual-modulus divider circuit (415) and tone shaping circuit in combination are arranged to generate a test tone from the series of pulses at an offset frequency from the LO signal, that does not contain frequency content at an image frequency.

A receiver for a wireline channel communication system, comprising an input for receiving a signal from one or more wires and an analog to digital configured to output a digital representation of the analog signal. A slicer module configured output a digital logic signal based on an amplitude of the analog signal. A high pass filter configured to receive the digital representation of the analog signal and output a filtered signal. A phase detector configured to receive a first signal based on the digital logic signal, and the filtered signal and configured to output an error signal indicative of a phase difference between the first signal and the filtered signal. A clock data recovery module configured to output a clock adjustment signal based on the error signal, wherein the clock adjustment signal is configured to control a sampling performed by the ADC.

An attenuator includes passgates for providing attenuation of received signals at desired frequencies. The passgates are controlled by source followers implemented with transistors that receive the differential signals at their control terminals. Current provided to the source follower transistors can be set to provide an attenuation level at a desired frequency to offset the effects of the communications channel and parasitics of the receiver. In some embodiments, the current provided to the source follower transistors maybe programmable.

Embodiments of a radio frequency (RF) controller for a 5G modem, a 5G modem, and a method for operating an RF controller of a 5G modem are disclosed. In an embodiment, an RF controller for a 5G modem includes a timing generator configured to generate a symbol clock signal, a memory unit containing execution boxes (Eboxes) of micro-operations and an index of the Eboxes to be executed in response to detecting a symbol idle period of the symbol clock signal, and an Ebox execution engine configured to execute micro-operations in one of the Eboxes based on the index of the Eboxes to perform an RF maintenance or calibration operation during the symbol idle period.

A method of receiving a Bluetooth Low Energy (BLE) audio broadcast and a Bluetooth Low Energy audio broadcast receiver is described. A BLE broadcast audio receiver receives a broadcast isochronous stream (BIS) intended for playback by the receiver. The BLE broadcast audio receiver receives a further BIS intended for playback by a different BLE broadcast audio receiver. The further BIS is re-transmitted by the BLE broadcast receiver.

Systems and methods for a discovery process for contention-based ranging, wherein a UWB subsystem of a user device is configured to determine if the short MAC address allocated to the user device has been added to the ranging management list (RML) of an access control device. If the short MAC address has not been added to the RML, the user device generates a different short MAC address that is not present in the RML and responds to the access control device with the different short MAC address. This process repeats until the short MAC address has been added to the RML. If the access control device receives responses from more than one user device having the same short MAC address within the same contention period, the short MAC address will not be added to the RML.

A processing system including a peripheral configured to store security information and having a clock input receiving a gated clock, a watch clock generator configured to generate a watch clock that has a reduced duty cycle relative to a system clock, and clock control circuitry configured to select the system clock as the gated clock during normal operation of the peripheral and to select the watch clock as the gated clock during a low power mode of the peripheral. The watch clock generator may include a counter that counts system clock cycles and clock pulse selector, such as a modulo circuit, configured to select cycles of the system clock for generating the watch clock. For multiple peripherals, delay circuitry may skew a watch clock between two or more peripherals. Multiple watch clocks with different delayed duty cycles may be generated, each for a corresponding one of multiple groups of peripherals.

First antennas in a first radar sensor receive first signals transmitted by one or more second antennas in a second radar sensor and reflected by at least one object. Third antennas in the second radar sensor receive second signals transmitted by one or more fourth antennas in the first radar sensor and reflected by the at least one object. A snapshot that includes complex values that represent phase responses of the first signals and the second signals is generated and a carrier phase offset between the first signals and the second signals is estimated based on the snapshot. In some cases, an output representing detection of an object is generated based on the carrier phase offset.

A method for verifying integrity of a binary tree graph structure having an "h" number of layers and a plurality of nodes configured to provide a public key, including: verifying an integrity of a stored root hash value associated with a root node; obtaining a non-root node of the plurality of nodes, the "h" number of layers includes a leaf layer, and the leaf layer includes a plurality of leaf nodes associated with a plurality of one-time signing public keys; obtaining an authentication path associated with the non-root node, the authentication path including other nodes; performing a plurality of pairwise hash computations on the non-root node and other nodes to produce a candidate root hash value; comparing the candidate root hash value to the stored root hash value; and determining the integrity of the binary tree graph is verified when the candidate root value equals the stored root value.

An Ethernet device comprising a transceiver and one or more processors, the Ethernet device configured to: transmit a request message to a staticallyconfigured second Ethernet device on an Ethernet network, wherein the request message is encoded according to a layer-2 protocol and a payload of the request message comprises a request for a second device network configuration from the second Ethernet device; receive a reply message from the second Ethernet device, wherein the reply message is encoded according to the layer-2 protocol and a payload of the reply message includes the second device network configuration of the second Ethernet device; compare the second device network configuration to a local device configuration of the Ethernet device; and route a diagnostic signal based on a mismatch between the second device network configuration and the local device configuration.

A divider circuit is disclosed. The divider circuit includes a pair of differential latch circuits. The divider circuit receives complementary clock signals as a pair of differential signals. The divider circuit generates frequency divided signals based on the complementary clock signals, inverted versions of the complementary clock signals, and input signals. The frequency divided signals may be substantially ripple-free. Further, the frequency divided signals remain substantially ripple-free in a presence of the skew between the complementary clock signals.

There is disclosed a method for registering a mobile device comprising an embedded Universal Integrated Circuit Card, eUICC, at a mobile network server. The method comprises determining subscriber identification information and deriving a first key. Then a registration request is sent to the mobile network server. The eUICC signs first random data with the first key and sends it to the mobile network server. The server produces a server authentication key and authenticates the eUICC, and if successful, grants limited access. The eUICC signs first or second random data with a second key and sends a registration message comprising the signed first or second random data to the mobile network server, which determines the validity of the signed first or second random data, and if valid, grants regular access to the eUICC. Further an embedded Universal Integrated Circuit Card, a mobile network server and a computer program product is disclosed.

The disclosure relates to a touch screen sensing system (1100), example embodiments of which comprise: a touch screen panel (1103) having a plurality pairs of touch sensing electrodes (row<1-Nrow>, col<1-Ncol>) arranged in rows and columns extending across the panel (1103); and a plurality of transceivers (1101<1-Nrow>, 1102<1-Ncol>), each of the plurality of transceivers (1101<1-Nrow>, 1102<1-Ncol>) connected to send and receive sensing signals (701<1-n>) to and from a respective one of the plurality of touch sensing electrodes (row<1-Nrow>, col<1-Ncol>), wherein each one of the plurality of transceivers (1101<1-Nrow>, 1102<1-Ncol>) is configured to transmit a sensing signal (701<1-n>) including a range of frequencies over a signal bandwidth (702<1-n>), the sensing signals (701<1-n>) being orthogonal to each other.

A bearing race for a rolling element bearing (130) is described. The bearing race includes a metal region having an outer surface and an inner surface. The race has a groove in at least one of the outer surface and the inner surface. The groove extends around at least part of a circumference the outer surface or the inner surface. A piezoelectric layer (110) and a resistive layer (112) are located in the groove.

There is described a method for locating a device (110, 120), the method comprising:i) forming a beam (150) from a first wireless transmitter signal and a second wireless transmitter signal at a transmitter device (120);ii) performing a scan operation for a receiver device (110) with the formed beam (150);iii) evaluating at least one criterium associated with the scan operation of the formed beam (150); andiv) locating the device (110, 120) based on the evaluated at least one criterium.

There is described a method for estimating a current geographical region of a device, comprising: (i) receiving a first signal at a first radio frequency in a first geographical region; (ii) determining a value of the first radio frequency and a value of a first characteristic parameter of the first signal; (iii) providing a value of a second radio frequency of a second signal and a related value of a second characteristic parameter of the second signal and wherein the combination of these two values relate to a second geographical region; (iv) comparing the determined value of the first radio frequency with the value of the second radio frequency, and comparing the value of the first characteristic parameter with the value of the second characteristic parameter; (v) estimating if the device is located in the second geographical region based on the comparisons.

A bandgap reference circuit comprising: a proportional to absolute temperature, PTAT, voltage circuit configured to generate a PTAT voltage; and a bandgap voltage circuit comprising a diode, the bandgap voltage circuit configured to: receive the PTAT voltage from the PTAT voltage circuit; and combine the PTAT voltage with a diode voltage across the diode to output a bandgap reference voltage.

The disclosure relates to a supply voltage glitch detection circuit (300) comprising: a first flip-flop (301) having a data input (302), a clock input (303) and an output (304); a delay circuit (305) having an output (307) connected to the data input of the first flip-flop; a first clock signal divider (308) having a clock input (309) connected to receive an inverted clock signal and an output (312) connected to an input (306) of the delay circuit (305); a second clock signal divider (313) having a clock input (314) connected to receive the clock signal and an output (315) connected to the clock input (303) of the first flip-flop, wherein the circuit (300) is configured to cause a glitch detection signal output to change state upon a supply voltage of the circuit (300) deviating to cause a change in a delay provided by the delay circuit (305).

A method is proposed to make more efficient use of limited computing resources in signature generation.

Systems and methods for delta-sigma modulators with downsampled digital integrators. In various embodiments, a delta-sigma modulator may include: a comparator configured to receive an analog input and to provide a digital output at a sampling frequency, where the digital output is applied to an integrator path and to a feed-forward path; a digital integrator in the integrator path, where the digital integrator is configured to operate with a clock frequency that is less the sampling frequency; and a summer configured to add an output of the integrator path to an output of the feed-forward path to produce a bitstream.