SK hynix

A memory device comprises a plurality of reference voltage generators, each of which corresponds to a plurality of data pins and generates a reference voltage for each of the corresponding data pins, with each of the plurality of reference voltage generators comprising a voltage divider that divides a power supply voltage into a plurality of divided voltages; a control logic that receives a first code indicating internal reference voltage level information and a second code indicating offset voltage information for a corresponding data pin, and that generates a control code based on the first and second codes; and a reference voltage selector comprising tree-structured transfer gates that select one of the plurality of divided voltages in response to the control code and output the selected one as a reference voltage.

A memory device according to some embodiments of the present disclosure may comprise a substrate including a cell region and a peripheral region, a first transistor disposed in the peripheral region of the substrate, the first transistor comprising a first gate insulating layer, a first gate electrode, and a first gate capping layer and a second transistor disposed in the peripheral region of the substrate, the second transistor comprising a semiconductor layer, a second gate insulating layer having a lower surface positioned higher than a lower surface of the first gate insulating layer, a second gate electrode, and a second gate capping layer having an upper surface positioned at the same height as an upper surface of the first gate capping layer.

A semiconductor device includes an integrated circuit structure disposed over a substrate and a hydrogen sensing structure disposed over the substrate to be laterally spaced apart from the integrated circuit structure. The integrated circuit structure includes an oxide semiconductor layer. The hydrogen sensing structure includes a hydrogen ion sensing layer containing a resistance change material, and a first sensing electrode layer and a second sensing electrode layer disposed at opposite ends of the hydrogen ion sensing layer. A bottom surface and a top surface of the hydrogen ion sensing layer are arranged to have same levels as a bottom surface and a top surface of the oxide semiconductor layer based on the surface of the substrate, respectively.

A semiconductor device includes a gate structure including a source select line, a drain select line, and word lines stacked between the source select line and the drain select line; a second channel layer penetrating through the source select line and including polysilicon; a third channel layer penetrating through the drain select line and including polysilicon; a first channel layer penetrating through the word lines, connected between the second channel layer and the third channel layer, and including molybdenum disulfide (MoS₂); and an insulating core disposed inside the first channel layer.

A memory system includes a memory controller; and a memory device configured to: during a write operation, generate a write error correction code based on write data, and store, according to a write poison signal received from the memory controller, the write data and the write error correction code, or first and second patterns in a memory cell array, and during a read operation, correct an error in read data based on a read error correction code read from the memory cell array, output a decoding status signal according to an error correction result, and generate a read poison signal according to at least one of the decoding status signal, a first comparison result between the read data and the first pattern, and a second comparison result between the read error correction code and the second pattern, to output the read poison signal to the memory controller.

A pluggable memory apparatus includes a plurality of memory sockets, a slot, and a main controller. The slot connects with an external device. The main controller is communicably coupled to the plurality of memory sockets and the slot, and has error correction function. The main controller sets at least one data processing mode among a plurality of data processing modes based on error rates of a plurality of memory modules mounted in the plurality of memory sockets, and remaps input/output data according to the at least one data processing mode.

Memory controllers, memory devices, and memory systems are disclosed. In an embodiments, a memory system includes a memory device configured to provide a data processing function such as a computational function. In the memory system, during at least a part of a period in which some ranks among N ranks sharing a data channel perform a computational operation, at least one of the remaining ranks performs a general memory operation such as a write or read operation, allowing the memory system to reduce delays in the general memory operation while still providing the computational operation.

A nonvolatile memory device includes N planes each comprising a plurality of memory blocks, N discharge control circuits adjacent to the N planes, respectively, and configured to connect each common source line of the N planes and a ground voltage terminal in response to each one of N discharge control signals, a plane selection circuit configured to select K planes of the N planes, and an operation control circuit configured to adjust voltage levels of K discharge control signals according to a distance difference between the ground voltage terminal and each of K discharge control circuits corresponding to the K planes, among the N discharge control circuits.

A semiconductor device including high-integrated memory cells and a method for fabricating the semiconductor device is provided. The semiconductor device includes a vertical arrangement and a horizontal arrangement of nano sheets; horizontal conductive lines that surround the horizontal arrangement of the nano sheets; pads coupled to edge portions of the horizontal conductive lines; inter-pad dielectric layers disposed between the pads; contact plugs each coupled to a different one of the pads; and contact spacers each including a first low-k material and each formed on a sidewall of each of the contact plugs.

A method for fabricating a semiconductor device including high-integrated memory cells and the semiconductor device is provided. The method includes forming a horizontal arrangement of nano sheet target patterns over a substrate, wherein the nano sheet target patterns include initial sheets that are horizontally oriented and sheet expansion tabs disposed on both sides of each of the initial sheets; performing a surface treatment on the nano sheet target patterns to form a horizontal arrangement of narrow sheets and nano sheet dielectric layers, each of the nano sheet dielectric layers surrounding a different one of the narrow sheets; and forming a horizontal conductive line on the nano sheet dielectric layers, the horizontal conductive line surrounding the narrow sheets.