SK hynix

Image sensing devices including pixel isolation structures are disclosed. In an embodiment, an image sensing device includes a first pixel and a second pixel. The first pixel includes a first photoelectric conversion region configured to detect light of a first wavelength range, and a first pixel isolation structure that surrounds the first photoelectric conversion region and has a first width. The second pixel includes a second photoelectric conversion region configured to detect light of the first wavelength range, and a second pixel isolation structure that surrounds the second photoelectric conversion region and has a second width smaller than the first width.

A semiconductor device and a method for manufacturing the same are disclosed. The semiconductor device includes a word-line structure extending into a semiconductor layer to a first depth, and additionally extending in a first direction, an active region extending in a diagonal direction with respect to the first direction in the semiconductor layer, and overlapping with the word-line structure, a bit-line pad region overlapping with one end of the active region and contacting one side of the word-line structure, and extending into the semiconductor layer to a second depth that is shallower than the first depth, and a storage-node pad region overlapping with another end of the active region and contacting another side of the word-line structure, the storage-node pad region being spaced apart from the bit-line pad region in the diagonal direction and extending into the semiconductor layer to a third depth that is shallower than the first depth.

A semiconductor device including a substrate; an insulating layer disposed on the substrate, and including an outer boundary; a passivation layer disposed on the insulating layer, and including an inner boundary that is located inward of the outer boundary; a dummy pattern layer having a lower surface that forms the same plane with the lower surface of the passivation layer, overlapping at least a part of a region disposed between the outer and inner boundaries, and having a side surface that is located inward of the inner boundary; and a redistribution pattern layer disposed on the dummy pattern layer.

A method of manufacturing a silicon on insulator (SOI) substrate is provided. A method of forming an SOI substrate includes forming a first wafer structure on an upper surface of a first wafer having a notch and a wafer identification (ID). The first wafer structure includes an etch stopper, a semiconductor layer, a buried insulation layer and a first bonding insulation layer, which are sequentially formed. An edge of the first wafer structure may be trimmed to form a trimmed region. Residual trimming byproducts on the first bonding insulation layer of the first wafer structure may be removed. The first wafer structure may be bonded to the second wafer structure. The semiconductor layer of the first wafer structure may be transferred onto the second wafer structure. A trimmed region may have a width greater than a recess length of the notch, and a depth greater than a depth of the wafer ID.

An image sensing capable of improving characteristics of one or more miniaturized pixels is disclosed. The image sensing device includes: a substrate including photoelectric conversion regions, each photoelectric conversion region configured to generate photocharges corresponding to an intensity of incident light, the substrate having a light receiving surface through which the incident light enters the substrate to reach the photoelectric conversion regions; and a plurality of microlenses disposed above the light receiving surface of the substrate, each microlens having a top surface to receive incident light and a bottom surface that is opposite to the top surface. each of the microlenses is structured to have a focal distance greater than or equal to a limit focal distance associated with a distance between the light receiving surface of the substrate and the bottom surface of each of the microlenses.

A semiconductor device includes a substrate including a chip region and a scribe lane region including a chip adjacent region, a chip adjacent crossing region, and a peripheral crossing region; a passivation layer; row trenches disposed between the boundary between the chip adjacent crossing region and a first boundary of the peripheral crossing region and the boundary between the chip adjacent crossing region and the chip adjacent region, in a direction crossing the first boundary, and disposed in the passivation layer; and column trenches disposed between the boundary between the chip adjacent crossing region and a second boundary of the peripheral crossing region and the boundary between the chip adjacent crossing region and the chip adjacent region, in a direction crossing the second boundary, and disposed in the passivation layer.

A semiconductor package includes first data memory dies configured to share a first control bus and a first data bus, the first data memory dies belonging to different ranks, a first error correction memory die configured to share the first control bus with the first data memory dies and connected to a first error correction bus, second data memory dies configured to share a second control bus and a second data bus, second data memory dies belonging to different ranks, and a second error correction memory die configured to share the second control bus with the second data memory dies and connected to the second error correction bus.

In a method of forming an SOI substrate, an etch stopper layer, a semiconductor layer, a buried insulation layer and a first bonding insulation layer may be sequentially formed on an upper surface of a donor wafer to form a donor wafer structure. A second bonding insulation layer may be formed on an upper surface of a carrier wafer to form a carrier wafer structure. The donor wafer structure may be bonded on the carrier wafer structure to form a bonding structure in which the first and second bonding insulation layers face each other. After the donor wafer is grinded, the remaining donor wafer is stripped. The etch stopper layer may be removed using a plasma cleaning gas including NF₃ to expose the semiconductor layer. A surface of the exposed semiconductor layer may be treated to have a uniform thickness.

A package substrate includes wirings on a substrate body. Each wiring includes a substrate pad in a boding finger region of the substrate body and a connected trace extending into a chip mounting region of the substrate body. Plating layers are respectively disposed on the substrate pads. Disposed on the substrate body are first and second residual sections of a first plating inlet line respectively connected to first and second traces. An insulating layer covers the first and second traces and residual sections. The insulating layer includes a first opening through which the first and second plating layers are exposed and includes a second opening separating the first residual section from the second residual section. The first trace includes a recessed section on a side facing the second trace, and the second opening is disposed within the recessed section.

A semiconductor device includes a gate structure including insulating layers and conductive layers alternately stacked, channel structures (120) extending through the gate structure and arranged in a first direction (I) and a second direction (II) crossing the first direction, a slit structure (130) extending in the first direction and including a body portion (130A) and protrusions (130B) protruding from the body portion in the second direction, and dummy structures (140) arranged in the first direction between the channel structures and the slit structure and respectively contacting the protrusions.