SK hynix Patente

A memory device comprises a plurality of reference voltage generators, each of which corresponds to a plurality of data pins and generates a reference voltage for each of the corresponding data pins, with each of the plurality of reference voltage generators comprising a voltage divider that divides a power supply voltage into a plurality of divided voltages; a control logic that receives a first code indicating internal reference voltage level information and a second code indicating offset voltage information for a corresponding data pin, and that generates a control code based on the first and second codes; and a reference voltage selector comprising tree-structured transfer gates that select one of the plurality of divided voltages in response to the control code and output the selected one as a reference voltage.

A memory device according to some embodiments of the present disclosure may comprise a substrate including a cell region and a peripheral region, a first transistor disposed in the peripheral region of the substrate, the first transistor comprising a first gate insulating layer, a first gate electrode, and a first gate capping layer and a second transistor disposed in the peripheral region of the substrate, the second transistor comprising a semiconductor layer, a second gate insulating layer having a lower surface positioned higher than a lower surface of the first gate insulating layer, a second gate electrode, and a second gate capping layer having an upper surface positioned at the same height as an upper surface of the first gate capping layer.

A semiconductor device includes an integrated circuit structure disposed over a substrate and a hydrogen sensing structure disposed over the substrate to be laterally spaced apart from the integrated circuit structure. The integrated circuit structure includes an oxide semiconductor layer. The hydrogen sensing structure includes a hydrogen ion sensing layer containing a resistance change material, and a first sensing electrode layer and a second sensing electrode layer disposed at opposite ends of the hydrogen ion sensing layer. A bottom surface and a top surface of the hydrogen ion sensing layer are arranged to have same levels as a bottom surface and a top surface of the oxide semiconductor layer based on the surface of the substrate, respectively.

A semiconductor device includes a gate structure including a source select line, a drain select line, and word lines stacked between the source select line and the drain select line; a second channel layer penetrating through the source select line and including polysilicon; a third channel layer penetrating through the drain select line and including polysilicon; a first channel layer penetrating through the word lines, connected between the second channel layer and the third channel layer, and including molybdenum disulfide (MoS₂); and an insulating core disposed inside the first channel layer.

A memory system includes a memory controller; and a memory device configured to: during a write operation, generate a write error correction code based on write data, and store, according to a write poison signal received from the memory controller, the write data and the write error correction code, or first and second patterns in a memory cell array, and during a read operation, correct an error in read data based on a read error correction code read from the memory cell array, output a decoding status signal according to an error correction result, and generate a read poison signal according to at least one of the decoding status signal, a first comparison result between the read data and the first pattern, and a second comparison result between the read error correction code and the second pattern, to output the read poison signal to the memory controller.

A pluggable memory apparatus includes a plurality of memory sockets, a slot, and a main controller. The slot connects with an external device. The main controller is communicably coupled to the plurality of memory sockets and the slot, and has error correction function. The main controller sets at least one data processing mode among a plurality of data processing modes based on error rates of a plurality of memory modules mounted in the plurality of memory sockets, and remaps input/output data according to the at least one data processing mode.

A memory device includes a first control circuit that is adjacent to a data input and output circuit and that generates an output enable signal driven to a first internal voltage based on an output control pulse generated after the start of a data output operation, generates output data from internal data loaded onto a global line through a repeater by receiving a delay output enable signal driven to a second internal voltage, and outputs the output data to the data input and output circuit, a data storage circuit that is adjacent to the first control circuit and that outputs the internal data to the global line after the start of the data output operation, and a second control circuit that is adjacent to the data storage circuit and that generates the delay output enable signal based on the output enable signal after the start of the data output operation.

A semiconductor device including high-integrated memory cells and a method for fabricating the semiconductor device is provided. The semiconductor device includes a vertical arrangement and a horizontal arrangement of nano sheets; horizontal conductive lines that surround the horizontal arrangement of the nano sheets; pads coupled to edge portions of the horizontal conductive lines; inter-pad dielectric layers disposed between the pads; contact plugs each coupled to a different one of the pads; and contact spacers each including a first low-k material and each formed on a sidewall of each of the contact plugs.

A storage device according to the embodiment of the present disclosure may include a memory for storing data and a controller determining whether to activate one or more of a plurality of low power mode entry techniques among a plurality of low-power mode delay techniques based on the power mode.

A nonvolatile memory device includes N planes each comprising a plurality of memory blocks, N discharge control circuits adjacent to the N planes, respectively, and configured to connect each common source line of the N planes and a ground voltage terminal in response to each one of N discharge control signals, a plane selection circuit configured to select K planes of the N planes, and an operation control circuit configured to adjust voltage levels of K discharge control signals according to a distance difference between the ground voltage terminal and each of K discharge control circuits corresponding to the K planes, among the N discharge control circuits.

Memory controllers, memory devices, and memory systems are disclosed. In an embodiments, a memory system includes a memory device configured to provide a data processing function such as a computational function. In the memory system, during at least a part of a period in which some ranks among N ranks sharing a data channel perform a computational operation, at least one of the remaining ranks performs a general memory operation such as a write or read operation, allowing the memory system to reduce delays in the general memory operation while still providing the computational operation.

A method for fabricating a semiconductor device including high-integrated memory cells and the semiconductor device is provided. The method includes forming a horizontal arrangement of nano sheet target patterns over a substrate, wherein the nano sheet target patterns include initial sheets that are horizontally oriented and sheet expansion tabs disposed on both sides of each of the initial sheets; performing a surface treatment on the nano sheet target patterns to form a horizontal arrangement of narrow sheets and nano sheet dielectric layers, each of the nano sheet dielectric layers surrounding a different one of the narrow sheets; and forming a horizontal conductive line on the nano sheet dielectric layers, the horizontal conductive line surrounding the narrow sheets.

A semiconductor device including high-integrated memory cells and a method for fabricating the semiconductor device are provided. The semiconductor device includes a first memory cell array including a vertical arrangement of first memory cells, a second memory cell array vertically disposed over the first memory cell array, and including a vertical arrangement of second memory cells, and a dummy memory cell array vertically disposed between the first memory cell array and the second memory cell array, and including a vertical arrangement of dummy memory cells. The first memory cells, the second memory cells and the dummy memory cells have the same structure.

The present application relates to a semiconductor package. The semiconductor package includes a wiring structure. The wiring structure includes a first insulating layer, a conductive pad on the first insulating layer, a second insulating layer on the conductive pad, a through hole passing through the second insulating layer and overlapping with the conductive pad, a protruding pattern disposed on the conductive pad and located in the through hole, and an under bump metallurgy (UBM) layer that contacts the upper surface and side surface of the protruding pattern and is connected to the conductive pad. A semiconductor chip connected to the UBM layer and disposed on the wiring structure.

Image sensing devices and imaging systems are disclosed. In an embodiment, an image sensing device includes: a first pixel group and a second pixel group, each of which includes a first pixel including a first active region with a first region size and a second pixel including a second active region with a second region size smaller than the first region size. Each of the first pixel and the second pixel may include an avalanche diode, an antireflective layer disposed on the avalanche diode, and a light receiving pattern disposed on the antireflective layer.

According to a method of fabricating an SOI substrate, a stopper layer, a semiconductor layer, a buried insulating layer and a first bonding insulation layer are sequentially formed on a sacrificial wafer. A second bonding insulation layer is formed on a reference wafer. The first and second bonding insulation layers include a Silicon Carbon Nitride (SiCN) material. Si-OH bonds are formed in the first bonding insulation layer and the second bonding insulation layer by an O2 plasma treatment. The sacrificial wafer is bonded to the reference wafer so that the first bonding insulation layer contacts the second bonding insulation layer.

A semiconductor device including high-integrated memory cells and a method for fabricating the semiconductor device are provided. The method for fabricating a semiconductor device includes forming an alternating stack of sacrificial pad sheets and inter-pad dielectric layers, which are stacked vertically spaced apart from each other over a substrate; forming preliminary contact holes penetrating the alternating stack; forming sacrificial plugs filling the preliminary contact holes; performing post-treatment processes on the sacrificial plugs and forming sacrificial plug patterns having different heights and sacrificial recesses having different depths; forming contact liner layers on sidewalls of the sacrificial recesses; removing the sacrificial plug patterns and forming contact holes; forming contact plugs filling the contact holes; removing the sacrificial pad sheets and forming pad openings; and forming each pad of a plurality of pads in a different one of the pad openings.

A semiconductor device including high-integrated memory cells and a method for fabricating the semiconductor device is provided. The semiconductor device includes a vertical arrangement and a horizontal arrangement of nano sheets; horizontal conductive lines horizontally oriented while surrounding the horizontal arrangement of the nano sheets; pads coupled to edge portions of the horizontal conductive lines; and inter-pad dielectric layers disposed between the pads, each inter-pad dielectric layer including an air gap.

In a method of forming an SOI substrate, a stopper layer having an etch selectivity different from a first wafer may be formed on the first wafer having a first surface and a second surface facing each other. A semiconductor layer having an etch selectivity different from the stopper layer may be formed on the stopper layer. A buried insulation layer may be formed on the semiconductor layer. The buried insulation layer may be formed by applying a compressive stress condition, to have a height of a central portion of the buried insulation layer being formed higher than a height of an edge portion of the buried insulation layer.

An image signal processor includes a defective pixel detector configured to detect a defective pixel from among similar characteristic pixels, the similar characteristic pixels representing pixels having a characteristic same as a characteristic of a target pixel included in a target kernel, a pattern determiner configured to determine a pattern of the target kernel based on pixel data of pixels included in the target kernel when the defective pixel is present, and a pixel interpolator configured to interpolate, when the defective pixel is positioned in a texture area of the pattern, the target pixel based on pixel data of pixels positioned in the texture area among dissimilar characteristic pixels and pixel data of pixels positioned in the texture area among the similar characteristic pixels, the dissimilar characteristic pixels representing pixels having a characteristic different from the characteristic of the target pixel.

A semiconductor device includes a first conductive line including an upper portion of a carbon-based thin layer; a variable resistance layer disposed over the first conductive line; a selector layer disposed over the variable resistance layer and a second conductive line disposed over the selector layer.

An image sensing device for generating image data is disclosed. A clamp control circuit included in the image sensing device includes a sensing circuit configured to sense a voltage level of a pixel signal to output a sensing signal; and a clamping circuit coupled to a column line, and configured to control a voltage level of a clamp voltage control signal in response to a voltage level of the sensing signal, and control a level of a clamp voltage in response to a clamp enable signal, the clamp voltage controlled based on a voltage level of the clamp voltage control signal and provided to the column line.

A memory device according to embodiments of the present disclosure may comprise a word line buried in a substrate and extending in a first direction, a bit line contact disposed between word lines, contacting an active area of the substrate, and having at least a portion of a side surface concave toward a center in a second direction perpendicular to the first direction, and a gate capping layer including a first capping portion contacting an upper surface of the word line and a second capping portion positioned on the first capping portion, overlapping with at least a portion of the side surface of the bit line contact in the second direction, and having a width different from a width of the first capping portion.

A memory device includes a contact, and a plurality of support structures disposed around the contact, wherein each of the support structures is formed utilizing a plurality of overlapping holes. The support structures include an insulating layer disposed within the overlapping holes. The support structures are formed by expanding and overlapping a plurality of first openings.

A memory device including a first substrate including a cell region and a peripheral region disposed around the cell region; a memory cell array disposed in the cell region of the first substrate; a second substrate disposed on the memory cell array; peripheral transistors disposed on the second substrate and connected to the memory cell array; a first insulating layer disposed in a trench that is located in the peripheral region of the first substrate, and including high density plasma oxide; and a second insulating layer on the first insulating layer.

A semiconductor device may include: channel pillars (12) arranged in a first direction (I) and a second direction (II) intersecting the first direction and having a first interval (W1) in the first direction and a second interval (W2) in the second direction, the first interval being smaller than the second interval; a select line (13) surrounding the channel pillars arranged in the first direction and extending in the first direction; word lines (WL) stacked above the select line; and local bit lines (17) penetrating through the word lines and connected to the channel pillars.

A method of forming an SOI substrate including a hydrogen thermal treatment performed on a pretreated sacrificial wafer, under high temperature. A stopper layer and a semiconductor layer may be sequentially formed on a first surface of the sacrificial wafer on which the hydrogen (H₂) thermal treatment was performed. The stopper layer and the semiconductor layer may be formed by an epitaxial growth process using a mixed precursor including a monosilane (MS) source and a dichlorosilane (DCS) source.

Embodiments of the present disclosure provide a chip stack package including a first semiconductor chip having a front bump on a first surface, a second semiconductor chip stacked on a second surface of the first semiconductor chip opposite the first surface, a carrier bump bonded to the front bump, a mold member surrounding the first semiconductor chip, the second semiconductor chip, and the carrier bump, and an external connection bump disposed on the carrier bump.

A semiconductor package includes a wiring structure, a first bump, and a semiconductor chip. The wiring structure includes a first electrode and has a first surface and a second surface that faces away from the first surface. The second surface of the wiring structure includes a recessed area that overlaps the first electrode. The first bump includes a first conductive pillar on the first surface of the wiring structure and a first solder layer on the first conductive pillar. The first bump contacts the first electrode. The first electrode includes a first section and a second section. The first section of the first electrode is disposed between the first surface of the wiring structure and the second surface of the wiring structure. The second section of the first electrode has a lower surface that is included in the first surface of the wiring structure. The horizontal width of the first conductive pillar is less than the horizontal width of the first electrode. A semiconductor chip is disposed above the second surface of the wiring structure.

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