Samsung Electronics Patente

A system (100) and a method are disclosed for wireless communication. The method includes transmitting, by a first access point, AP (101), capability information indicating one or more multi-access point coordination, MAPC, schemes; and transmitting, by the first AP (101), an MAPC negotiation indication indicating an enabled state or a disabled state for MAPC negotiation.

A device, system, and method are disclosed for efficiently enabling Processing-in-Memory, PIM, or processing-near-memory, PNM, compression on mobile systems on a chip, SoC. In an embodiment, a memory device (310) includes a cryptographic engine, CE (316), wherein the memory device (310) is configured to receive encrypted data via a memory input/output, IO, bus (320), and the CE (316) is configured to decrypt the encrypted data to obtain decrypted data. The memory device (310) can further comprise a PIM or PNM device (314) configured to process the decrypted data.

A device, system, and method are disclosed for processing-in-memory, PIM, compression. In an embodiment, a method includes obtaining, by an input/output sense amplifier, IOSA (204), from an associated RAM bank (202), compressed data (702); sending, by the IOSA (202), the compressed data (702) divided into a plurality of portions (704); receiving, by a respective decompressor of a plurality of decompressors (306) of a PIM block (212) associated with the RAM bank (202), a respective portion of the compressed data (702); decompressing, by the respective decompressor, the respective portion of the compressed data to obtain a respective portion of decompressed data; and sending, by the respective decompressor, the respective portion of the decompressed data to a respective Arithmetic Logic Unit, ALU, of a plurality of ALUs (308) of the PIM block (212) for processing.

Methods and devices are provided in which a volume manager determines a bucket of a variable-granularity volume map, VVM, for block volume storage, based on a corresponding volume logical block address, vLBA, set; and determines an entry for the vLBA set in the VVM or a fine-grained volume map, FVM, for the block volume storage, based on the determined bucket comprising at least one empty entry or entries of the VVM occupied, wherein the FVM comprises a higher granularity than the VVM.

Provided are non-volatile memory devices, storage devices, and methods of operating the storage devices. The non-volatile memory device includes a memory interface circuit including a data pin configured to output a data signal, a command address pin separated from the data pin and configured to receive a first data output packet, and a first pin configured to receive a toggle signal corresponding to the first data output packet, a first page buffer configured to output first data in response to the first data output packet, and a first register configured to provide the first data to the memory interface circuit through a first path based on receiving a first clock signal generated based on the toggle signal, and provide the first data to the memory interface circuit through a second path different from the first path in response to receiving a second clock signal different from the first clock signal.

A circuit device (100) includes a semiconductor substrate (102) having a first transistor structure (104). The first transistor structure includes at least one first channel region (106) extending between first source/drain regions (108), first source/drain contacts (110) on the first source/drain regions, respectively, and a first gate (112) on the at least one channel region between the first source/drain contacts. A first spacer (115) electrically isolates one of the first source/drain regions from one of the first source/drain contacts thereon. Related devices and fabrication methods are also discussed.

Semiconductor devices and methods of manufacturing the semiconductor devices are provided. For example, a semiconductor device (1) may include: a stack of semiconductor layers including a first semiconductor layer (200B), and a second semiconductor layer (200C) stacked on the first semiconductor layer (200B) in a first direction (Z); a heat sink (300) stacked on the second semiconductor layer (200C) in the first direction (Z); and a heat pipe (100) that extends in the first semiconductor layer (200B), the second semiconductor layer (200C), and the heat sink (300) in the first direction (Z).

An example capacitor structure includes a lower electrode structure (70), a dielectric pattern (95) and an upper electrode (105). The lower electrode structure (70) includes a first lower electrode (65) on a substrate (10), and a second lower electrode (62) on a sidewall of the first lower electrode (65). The second lower electrode (62) includes an alloy of a first metal and a second metal. The dielectric pattern (95) is disposed on a surface of the lower electrode structure (70). The upper electrode (105) is disposed on a surface of the dielectric pattern (95). The second lower electrode (62) has a thickness varying in a vertical direction perpendicular to an upper surface of the substrate (10). A weight ratio between the first metal and the second metal is uniform in the vertical direction in the second lower electrode (62).

An integrated circuit is provided. The integrated circuit includes: a voltage-dividing circuit including a plurality of resistors connected to each other in series, wherein the voltage-dividing circuit is configured to generate, based on a test signal, an internal test signal, at least one first reference signal, and at least one second reference signal; a first low-pass filter configured to receive the at least one first reference signal and generate a first reference voltage; a second low-pass filter configured to receive the at least one second reference signal and generate a second reference voltage; a first comparator configured to compare the first reference voltage to the internal test signal; and a second comparator configured to compare the second reference voltage to the internal test signal.

A storage device includes a nonvolatile memory device including an input/output register, the nonvolatile memory device sensing data from a memory region corresponding to an address and transmitting the data that is sensed from the memory region, and a storage controller that transmits a command and the address to the nonvolatile memory device via a first bus and that transmits and receives data to and from the nonvolatile memory device via a second bus. The nonvolatile memory device, in response to a first command that is received from the storage controller, outputs a sensing status of first data and stores the first data in the input/output register.

A system and a method are disclosed for coordinating for a coordinated beamforming, Co-BF, in an overlapping basic service set, BSS. The method includes detecting, with at least one of a first access point, AP, an overlapping BSS between a first AP (AP1) and a second AP (AP2) and transmitting, with the first AP (AP1), an indication of whether the first AP (AP1) received a cross-BSS channel state indicator, CSI, report (214c). The method also includes coordinating with the second AP (AP2) by the first AP (AP1), to perform a Co-BF based on the cross-BSS CSI report (214c).

A semiconductor device comprising: a substrate (110) includes a first surface (110a) and a second surface (110b) opposing each other; an epitaxial layer (131) positioned on the first surface (110a) of the substrate (110), including a gate trench (160), and the epitaxial layer (131) having a first conductivity type; a channel layer (300) positioned on the inner sidewall (160_s) of the gate trench (160) and having the first conductivity type; a gate electrode (150) positioned on the inner side surface of the channel layer (300); a gate insulating layer (140) positioned on the bottom surface of the gate trench (160), and between the channel layer (300) and the gate electrode (150); a source electrode (173) positioned on the epitaxial layer (131); and a drain electrode (175) positioned on the second surface (110b) of the substrate (110).

A memory device includes: a cell semiconductor layer respectively including sub-cell regions arranged in a first direction, and contact regions between the sub-cell regions, wherein the sub-cell regions include memory cells; and a circuit semiconductor layer on the cell semiconductor layer and including a circuit configured to control the memory cells. The cell semiconductor layer includes: sub-wordlines extending in the first direction from the sub-cell regions to adjacent contact regions; odd wordline interconnection lines extending from an odd sub-cell region to adjacent contact regions; and even wordline interconnection lines extending from an even sub-cell region to the adjacent contact regions.

A semiconductor device includes a substrate, a first conductivity type semiconductor layer on a first surface of the substrate and penetrated by a first trench and a second trench, a gate electrode in the first trench and including a first side surface and a second side surface opposing each other, a first gate insulating layer on the first side surface and a lower surface of the gate electrode, a second conductivity type doping layer on the first conductivity type semiconductor layer and covering a portion of a side surface of the first gate insulating layer, a first conductivity type doped region on the second conductivity type doping layer and covering another portion of the side surface of the first gate insulating layer, a source electrode on the first conductivity type doped region, a drain electrode on a second surface of the substrate and a shielding pattern around the second trench.

A nonvolatile memory device includes a memory cell array including a plurality of planes, a page buffer circuit connected to the memory cell array through a plurality of bit lines, an input/output circuit connected to the page buffer circuit through a plurality of data lines, a control logic circuit controlling an operation for the planes in response to a command, a first command-address pad set electrically connected to the control logic circuit and receiving a first command, and a second command-address pad set electrically connected to the control logic circuit and receiving a second command. A time during which the first command is received overlaps with a time during which the second command is received.

A memory device includes a first semiconductor layer including a first cell region and a second cell region over the first cell region, and a second semiconductor layer under the first semiconductor layer in a substantially vertical direction and including a page buffer circuit which includes a first page buffer set associated with odd data and a second page buffer set associated with even data, the first cell region includes first memory cells, a first odd bit line transmitting odd data of the first memory cells, and a first even bit line transmitting even data of the first memory cells, the second cell region includes second memory cells, a second odd bit line transmitting odd data of the second memory cells, and a second even bit line transmitting even data of the second memory cells.

Methods, devices, and systems for training a deep learning recommendation model (DLRM), include: offloading (S101) one or more storage tables to a memory device; training (S102) a DLRM based on training data, wherein during the training, a storage table prefetched from the memory device is loaded according to a training phase; and storing (S103) feature data obtained during the training into the loaded storage table.

An example of a semiconductor memory device includes a substrate; bitlines extending in a first direction on the substrate; first back gate lines extending in a second direction; first semiconductor patterns connected to the bitlines and extending in a third direction, on the first back gate lines; wordlines extending in the second direction on the first semiconductor patterns; second semiconductor patterns connected to the bitlines and extending in the third direction, on the wordlines; and second back gate lines extending in the second direction on the second semiconductor patterns.

Provided is an operation method of user equipment in communication with a satellite in a non-terrestrial network, the operation method including receiving a synchronization signal block (SSB) burst through wide beams from the satellite, performing, based on the SSB burst, an indexing operation on narrow beams corresponding to the wide beams, estimating an optimal narrow beam, based on the indexed narrow beams, and performing random access to the satellite, based on the estimated narrow beam.

A random number generation device includes an instantiate and reseed function logic configured to receive an entropy input having a size smaller than or equal to a reference size of a reference seed material that may be processed at one time during a crypto operation and configured to repeatedly perform the crypto operation, based on a seed material configured to be processed at one time during the crypto operation in a current crypto operation sequence and an operation result in a previous crypto operation sequence, and a random number generation logic configured to generate random number data.

A semiconductor memory device includes a stack structure including a plurality of layers stacked on a substrate in a vertical direction, and bit lines disposed at a side of the stack structure and extending in the vertical direction. The plurality of layers include semiconductor patterns, gate electrodes extending from the semiconductor patterns in a first horizontal direction, and information storage elements adjacent to the semiconductor patterns in a second horizontal direction crossing the first horizontal direction. The semiconductor patterns include first impurity regions adjacent to the bit lines, second impurity regions adjacent to the information storage elements, and channel regions between the first impurity regions and the second impurity regions. The information storage elements include first electrodes adjacent to the second impurity regions. A portion of the stack structure includes metal silicides disposed between the second impurity regions at a side of the semiconductor patterns and the first electrodes.

A storage device includes a memory device including command and address pins, data pins, first control signal pin, memory blocks, and a transceiver transmitting or receiving data through the data pins and a memory controller transmitting a command and an address to the memory device through the command and address pins, transmitting and receiving data to and from the memory device through the data pins, and transmitting a first control signal to the memory device through the first control signal pin. The memory device transmits, in response to receiving a select chip enable packet received through the command and address pins, a second control signal in an activated state to at least one driving circuit that, in response to receiving the second control signal in an activated state, drives the transceiver transmitting and receiving data. The memory device then transmits or receives first data based on the select chip enable packet and the first control signal through the data pins.

An encryption device includes a controller configured to output random data including K random bits, where K is an integer greater than or equal to 2, and a random shuffling circuit configured to receive N input bits and perform a random shuffling operation on the N input bits, where N=3×2^b, and b is a non-negative integer, based on a plurality of layers each including the random data and an even number of multiplexers, to output final shuffling data having a uniform distribution, wherein a total number of multiplexers included in the random shuffling circuit is 2×K, each of the K random bits is input to two multiplexers included in one layer, and a number of layers is a smallest integer from among integers greater than or equal to K divided by a largest integer from among integers less than or equal to N/2.

A processing element (510) is disclosed. The processing element (510) may include a memory array (305) to store at least a first value and a second value. The processing element (510) may also include a first circuit (310, 320) to access the first value and the second value from the memory array (305). The processing element (510) may also include a multiply and accumulate, MAC, circuit (605) to process the first value and the second value to produce a third value. The processing element (510) may be part of a memory.

An image sensor includes a sensor substrate including a first pixel, a second pixel, a third pixel, and a fourth pixel, and a nano-photonic lens array including a first meta-region, a second meta-region, a third meta-region, and a fourth meta-region, wherein each of the first to fourth meta-regions includes at least one nano-structure configured to condense light of a first wavelength onto the first and fourth pixels, light of a second wavelength onto the second pixel, and light of a third wavelength onto the third pixel, and at least one nano-structure provided in at least one of the second meta-region and the third meta-region is a polarization-separating nano-structure configured to provide the light of the first wavelength having a first polarization component to the first pixel and provide the light of the first wavelength having a second polarization component to the fourth pixel.

A memory cell array may include a first memory cell including a first transistor structure and a first capacitor structure, a second memory cell including a second transistor structure and a second capacitor structure, and a first wordline contact connected to the first transistor structure and the second transistor structure, wherein the first capacitor structure is spaced apart from the first transistor structure in a first direction, and the second capacitor structure is spaced apart from the second transistor structure in a second direction different from the first direction.

Systems, methods, and apparatuses are disclosed for reducing cell search time. In one or more examples, the systems, devices, and methods include discarding (905) a first candidate of a first set of candidates of carrier frequencies based the first candidate failing to satisfy a power ratio threshold; storing (910) a second candidate based on the second candidate satisfying the power ratio threshold; generating (915), at the UE, an increased power ratio threshold based on the respective power ratios of the two or more accumulations of the second candidate satisfying the minimum power ratio threshold, the increased power ratio threshold being greater than the power ratio threshold; identifying (920), based on the UE storing one or more candidates, a second set of candidates that is a subset of the first set of candidates, the second set of candidates including the second candidate; and establishing (925) a connection to a cell based on the second candidate.

An electronic device includes an antenna that receives a receiving signal including samples, each having a value repeating every first number of samples, and a communication processor electrically connected to the antenna. The communication processor obtains a first cumulative correlation value by accumulating results of correlation operations between a first delay signal and the receiving signal, obtains a second cumulative correlation value by accumulating results of correlation operations between a second delay signal and the receiving signal, the second delay signal being obtained by delaying the receiving signal by a second delay time that is different from a first delay time of the first delay signal, and obtains data included in the receiving signal when an absolute value of the second cumulative correlation value is greater than or equal to a second threshold and an absolute value of the first cumulative correlation value is less than a first threshold.

An image sensor includes an active pixel sensor region configured to output a pixel signal for image generation, and a periphery region at an edge of the active pixel sensor region. The active pixel sensor region and the periphery region may include a sensor substrate, and the sensor substrate may include a plurality of pixels arranged across the active pixel sensor region and the periphery region. The active pixel sensor region may include a plurality of nanostructures disposed to face the sensor substrate and spaced apart from the sensor substrate, the periphery region may include a light-shielding layer disposed on the sensor substrate and at the edge of the active pixel sensor region, and the light-shielding layer may include a light-reflective layer and a light-absorbing layer including an inorganic material.

An electronic device (1500) comprises: a battery (1520); one or more processors (1540); and a memory (1530) storing instructions, which, when executed by the one or more processors (1540), cause the electronic device (1500) to: store an updated parameter value of at least one target parameter selected from among a plurality of degradation parameters based on monitoring of the battery (1520); determine parameter values of the other parameters based on the updated parameter value of the at least one target parameter; estimate a battery state of the battery (1520) based on the updated parameter value of the at least one target parameter and the determined parameter values of the other parameters, using a battery state estimation model; update the parameter values of the other parameters based on the estimated battery state; and determine an updated battery state based on the updated parameter value of the at least one target parameter and the updated parameter values of the other parameters.

An image sensor includes a nano-photonic lens array, the nano-photonic lens array includes unit meta-groups each including a first meta-region, a second meta-region, a third meta-region, and a fourth meta-region, each of the first to fourth meta-regions includes a first sub-region, a second sub-region, a third sub-region, and a fourth sub-region, at least one nanostructure is provided in each of the first to fourth sub-regions, in the first to fourth meta-regions of a peripheral meta-group in a periphery of the nano-photonic lens array, a distance by which the nanostructure of the first sub-region and the nanostructure of the second sub-region are shifted in the first direction decreases as an azimuth angle of the peripheral meta-group increases from 0 degrees to 90 degrees, and a distance by which the nanostructure of the first sub-region and the nanostructure of the third sub-region are shifted in the second direction increases as the azimuth angle of the peripheral meta-group increases from 0 degrees to 90 degrees.

A storage device may include a non-volatile memory device and a storage controller including a phase-locked loop circuit, the phase-locked loop circuit may include a phase detector configured to output a phase-difference signal corresponding to a phase difference between the reference clock signal and the feedback clock signal; a voltage generator configured to generate an input voltage corresponding to the phase-difference signal and output the input voltage; an oscillator configured to generate an output clock signal having a frequency corresponding to the input voltage and output the output clock signal; a reset synchronization circuit configured to synchronize the reset signal based on the reference clock signal, and output a synchronous reset signal, and a frequency divider configured to reset based on the synchronous reset signal, generate the feedback clock signal by dividing a frequency of the output clock signal, and output the feedback clock signal.

A method to be executed by processing circuitry comprising one or more processors, a memory, an encoder and a decoder. The method includes inputting a measured image into an encoder, obtaining a feature produced from the encoder as a noise-invariant feature, passing the noise-invariant feature to a decoder, obtaining an image produced by the decoder as a denoised image, and detecting a local anomaly of the measured image by using the noise-invariant feature. The method may involve detecting one or more of a shape anomaly, a particle anomaly, and a crack anomaly for the measured image by using the noise-invariant feature. Further, the method may involve detecting a global anomaly in the measured image by using the denoised image.

A semiconductor device includes a substrate including a first surface and a second surface opposite to the first surface, a first active pattern on the first surface of the substrate and extending in a first direction, a first gate structure on the first active pattern and extending in a second direction intersecting the first direction, a first epitaxial pattern on at least one side of the first gate structure and connected to the first active pattern, a first frontside source/drain contact on a first surface of the first epitaxial pattern and connected to the first epitaxial pattern, a frontside wiring structure on a first surface of the first frontside source/drain contact and connected to the first frontside source/drain contact, and an insulating pattern on a second surface of the first gate structure and extending in the second direction.

Disclosed herein are methods, devices and systems including a supporting board (110) and a first cooling structure (102) on the supporting board (110), the first cooling structure (102) including a first high-power density package immersed within a first dielectric fluid (106), the first dielectric fluid (106) thermally coupled to the first high-power density package. A first connector (108) is arranged between the first cooling structure (102) and the supporting board (110) and communicatively couples the first high-power density package to the supporting board (110). The first dielectric fluid (106) is separated from the first connector (108) by at least one surface of the first cooling structure (102). The first dielectric fluid may have a first liquid phase and a first vapor phase within the first cooling structure (102).

The present disclosure, methods, and devices for efficiently writing data to a storage device are disclosed. The method may include receiving, from a host device, one or more commands to write data in the NAND flash memory region of the storage device, wherein each command having a data block and a write request to write the data block in a page of the NAND flash memory region; performing a set of operations of a predefined routine, based on the one or more commands; preventing transmission of a first completion indication of the set of operations to the host device; receiving data blocks associated with each command, the data blocks being associated with a subsequent set of operations of the predefined routine; and performing the subsequent set of operations of the predefined routine, based on receiving the data blocks for writing the data to the NAND flash memory region.

A semiconductor device includes a gate stacking structure (120), a channel structure (CH), a cover insulation layer (168a), and a common source layer (170). The gate stacking structure (120) has a first surface (120a) and a second surface opposite to each other, and includes a plurality of interlayer insulation layers (132m) and a plurality of gate electrodes (130) alternately stacked on each other. The channel structure (CH) includes a channel penetration portion (CHa) and a channel expanded portion (CHb). The channel structure (CH) includes a channel layer (140) and a gate dielectric layer (150). The gate dielectric layer (150) includes a first dielectric portion (150a) in the channel penetration portion (CHa) and a second dielectric portion (150b) extending from the first dielectric portion (150a) in a horizontal direction at a portion adjacent to the first surface (120a) of the gate stacking structure (120).

A system and devices (100) are disclosed for implementing Compute with Memory Stack (CMS) semiconductor hardware (e.g., die, packages, etc.) with an architecture integrating memory and compute on a die, implementing shorter distance high-bandwidth communication between elements, and minimizing data traffic. A device (100) includes a first die (110), the first die (110) including a first compute component, a second compute component, a first set of Through Silicon Vias, TSVs, (152) associated with the first compute component and connecting stacked dies of the device (100), and a second set of TSVs (152) associated with the second compute component and connecting the stacked dies of the device (100). The device (100) includes a second die (115), stacked on the first die (110). The second die (115) may include a first memory bank module connected to the first compute component using the first set of TSVs (152), and a second memory bank module connected to the second compute component using the second set of TSVs (152).

A method of processing a frame in a wireless communication device is provided. The method includes: receiving (301), by the wireless communication device, the frame, the frame including a first user information field; detecting (302), by the wireless communication device and based on information contained in the first user information field, whether the frame includes an intermediate frame check sequence, IFCS, and whether location information for the IFCS is available; when the location information for the IFCS is available, determining (304), by the wireless communication device and based on the location information contained in a user information field following a common information field of the frame, a position of one or more additional user information fields that include the IFCS; and when the location information for the IFCS is available, verifying (306), by the wireless communication device, the IFCS based on the one or more additional user information fields.

An image processing method and an apparatus are provided. The image processing method performed by a computing device including a processor and a memory includes configuring, by the processor, a convolutional layer or a transposed convolutional layer as a first convolutional layer; setting, by the processor, a filter; performing, by the processor, a convolutional operation or a transposed convolutional operation by applying the filter to weight of the first convolutional layer and generate a second convolutional layer; and performing, by the processor, a convolutional operation or a transposed convolutional operation by applying the second convolutional layer to an input tensor and outputting a result.