Samsung Electronics Patente

A memory device (30b) includes a plurality of planes (31, 32) and a control circuit. The plurality of planes (31, 32) may be included in a chip, and each of which may include a cell array and a page buffer. The control circuit, in a first mode, may enable or disable at least one first plane (31) among the plurality of planes (31, 32) based on a signal (nCE1) received through a first chip enable pad (P01) and output a signal (RnB1) that indicates a state of the at least one first plane (31) through a first ready/busy pad (P02). The control circuit may also enable or disable at least one second plane (32) among the plurality of planes (31, 32) based on a signal (nCE2) received through a second chip enable pad (P05) and output a signal (RnB2) that indicates a state of the at least one second plane (32) through a second ready/busy pad (P06).

A storage device includes a storage controller configured to output a command instructing reading of data, and a nonvolatile memory device including a plurality of NAND strings corresponding to a plurality of bit lines and a plurality of string selection lines, and configured to select a plurality of first bit lines among the plurality of bit lines based on the command, electrically connect a plurality of first NAND strings corresponding to the plurality of first bit lines among the plurality of NAND strings to the plurality of first bit lines and a common source line, and electrically disconnect a plurality of second NAND strings corresponding to a plurality of second bit lines among the plurality of NAND strings from the plurality of second bit lines and the common source line.

A processor-implemented method includes determining a task ratio between a first processing group and a second processing group for an inference task of a generative model, generating subtensors by dividing tensors used for the inference task based on communication dependency of computation stages of the inference task, storing the generated subtensors in a first memory pool of the first processing group and in a second memory pool of the second processing group based on the task ratio, and performing the inference task using the stored subtensors by the first processing group and the second processing group.

A semiconductor chip may include: a chip substrate including a first surface and a second surface opposite to the first surface; a passivation layer on the second surface of the chip substrate; a through via penetrating the chip substrate and the passivation layer; a chip pad on the through via and the passivation layer; and a seed layer between the through via and the chip pad and between the passivation layer and the chip pad. The passivation layer may include an etching region in which the through via is located, and an upper surface of the etching region of the passivation layer may be recessed.

A low molecular weight compound represented by Chemical Formula (1) or Chemical Formula (2), each of which is described herein; a composition including the low molecular weight compound and a salt compound, the salt compound including a borate anion represented by Chemical Formula (3), which is described herein, and an iodonium cation; an organic film prepared by curing the composition and a carboxyl-containing compound; and an electroluminescent device including the organic film are disclosed.

A semiconductor nanoparticle, a method of preparing the semiconductor nanoparticle, and a display device including the semiconductor nanoparticle. The semiconductor nanoparticle includes silver, indium, gallium, and sulfur, and as a radial concentration distribution of silver, indium, and gallium is measured, the semiconductor nanoparticle exhibits a maximum value of a mole ratio of gallium to a total of indium and gallium in a first zone, and in the first zone, a mole ratio of silver to the total of indium and gallium is greater than or equal to about 0.18:1 and less than 1.5:1, and the semiconductor nanoparticle exhibits a quantum yield of greater than or equal to about 85%.

A memory device (200) includes a memory cell array (210) including one or more banks, a power gating switch (231) disposed on a power path for transmitting a power supply voltage (VDD, VPP) inside the memory device (200), a power gating controller (232) configured to turn on or off a power gating operation of the power gating switch (231) based on a temperature of the memory device (200,) and a frequency of an access to the memory device (200), and a control logic circuit (240) configured to provide, to the power gating controller (232), temperature information (Temp) indicating the temperature of the memory device (200) and a counting value indicating the frequency of the access, wherein when the power gating operation is turned on, the power gating switch (231) toggles in response to the access to the memory device (200), and when the power gating operation is turned off, the power gating switch (231) remains turned on regardless of the access to the memory device (200).

A semiconductor device includes: a bit line on a substrate and extending in a first direction parallel to an upper surface of the substrate; a semiconductor pattern on the bit line and extending in a direction perpendicular to the upper surface of the substrate; a gate electrode on a side surface of the semiconductor pattern and extending in a second direction intersecting the first direction; a storage node contact on an upper surface of the semiconductor pattern; an upper insulating layer covering a side surface of the storage node contact; and a capping pattern between the upper insulating layer and the gate electrode. The upper insulating layer is on an upper surface of the capping pattern. The upper surface of the semiconductor pattern and the upper surface the capping pattern each have a concave profile.

A three-dimensional semiconductor memory device includes a first peripheral circuit structure (PS1) and a second peripheral circuit structure (PS2) sequentially provided on a first substrate (10). The second peripheral circuit structure includes a second substrate (100) having a first surface (100a) and a second surface (100b) facing the first surface, a transistor array (TA) including transistors (TR2) on the first surface of the second substrate, an insulating layer (40) on the second surface of the second substrate, a conductive line (CL) extending in the insulating layer in a first direction parallel to the first surface of the second substrate, and a conductive contact (CT) between the conductive line and the second surface of the second substrate.

An example semiconductor device is a SiC semiconductor device, including a buffer layer, a first conductivity type semiconductor layer on a first surface of the buffer layer, a second conductivity type well region in the first conductivity type semiconductor layer, a first conductivity type well region in the second conductivity type well region, a gate electrode adjacent to the second conductivity type well region, a gate insulating layer between the gate electrode and the second conductivity type well region, a first electrode on the first conductivity type well region, and a second electrode on a second surface of the buffer layer, the second surface being opposite the first surface. The buffer layer includes a first buffer layer including a first element homologous to Si, and, in the first buffer layer, the content of the first element is 10 at% to 50 at%.

The present disclosure relates to an image sensor and a method of operating the image sensor. An example image sensor include a first sub-pixel group (PGs11) including a first plurality of photodiodes (PD1 - PD8) arranged in a plurality of rows and a plurality of columns and sharing a first floating diffusion node (FD1), a second sub-pixel group (PGs12) adjacent to the first sub-pixel group (PGs11), and including a second plurality of photodiodes (PD9 - PD16) arranged in a plurality of rows and a plurality of columns and sharing a second floating diffusion node (FD2) separate from the first floating diffusion node (FD1), a color filter (CF1), at least a portion of which is disposed on the first sub-pixel group (PGs11) and the second sub-pixel group (PGs12), and a first lens (MLb), at least a portion of which is overlapped planarly with the first sub-pixel group (PGs11) and the second sub-pixel group (PGs12).

Provided are systems (100), methods, and apparatuses for data replication in memory devices (115). In one or more examples, the systems (100), devices, and methods include providing an allocation of memory resources of a memory pool appliance to a host (105); selecting a first memory module of multiple memory modules of the memory pool appliance as a primary memory resource of the allocation; selecting at least a second memory module of the multiple memory modules as a secondary memory resource of the allocation; configuring, in a memory switch of the memory pool appliance and for the allocation, a virtual memory module as an interface between the host (105) and memory modules of the allocation; and executing a first command, received at the virtual memory module and from the host (105), to read data based on the allocation.

A display apparatus includes a display layer including a plurality of light-emitting devices, and a drive layer configured to drive the plurality of light-emitting devices, where at least one of the plurality of light-emitting devices includes a light-emitting structure including a first light-emitting element, a second light-emitting element, and a third light-emitting element sequentially and monolithically stacked from the drive layer in a first direction, each of the first light-emitting element, the second light-emitting element, and the third light-emitting element including a p-type semiconductor layer, an active layer, and an n-type semiconductor layer, where the n-type semiconductor layer of the first light-emitting element includes AlGaN and a doping amount of an n-type dopant in the n-type semiconductor layer of the first light-emitting element is 2E+19/cm<3> or more.

A method for selecting measurements for positioning is disclosed. The method may include calculating (405), by an initiator device, a plurality of distance measurements, determining (410), by the initiator device, that a difference between a first value and a second value of the plurality of distance measurements is greater than a threshold, in response to the difference being greater than the threshold, dividing (415), by the initiator device, the plurality of distance measurements into N clusters, selecting (420), by the initiator device (108), a first cluster from among the N clusters based on a number of distance measurements in the first cluster, and outputting (425), by the initiator device, a distance between the initiator device and a responder device based on the distance measurements in the first cluster.

A semiconductor device includes local bitlines connected to memory cells, global bitlines disposed at a level higher than a level of the local bitlines and extending in a first horizontal direction, and bitline sense amplifiers connected to the global bitlines. The global bitlines include a first global bitline and a first global complementary bitline, complementary to the first global bitline. The first global bitline includes a 1-1 bitline structure, and the first global complementary bitline includes a 2-1 bitline structure at least partially overlapping the 1-1 bitline structure in the first horizontal direction. The 1-1 bitline structure includes 1-1 lower lines spaced apart from the 1-1 lower lines in the first horizontal direction and a 1-1 upper line disposed on the 1-1 lower lines and connected to the 1-1 lower lines.

The present disclosure provides a search method, a host, and a process near memory (PNM) apparatus, and a host storage system. The search method, when executed by a host may include calling a process near memory (PNM) apparatus to perform a search-related computation on a vector dataset in a vector database; and receiving a result associated with the search-related computation from the PNM apparatus. The search method, when executed by a PNM apparatus may include performing a search-related computation on a vector dataset in a vector database in response to receiving a calling instruction from a host; and returning a result associated with the search-related computation to the host after completion of the search-related computation.

The disclosure provides a retrieval method, a host, and a process near memory apparatus. The method includes receiving a query vector, initializing a plurality of process near memory (PNM) apparatuses to perform, in a respective stored subset of data, a sub-retrieval corresponding to the query vector, receiving a plurality of sub-results returned by the plurality of PNM apparatuses based on the sub-retrieval, and outputting a retrieval result regarding the query vector based on the plurality of sub-results.

A device is disclosed. The device may include a connection to a host or a management unit, a media to store a data, and a controller to access the data in the media based at least in part on a request from the host. A buffer may store a correctable event record, which may include fields. Some fields in the correctable event record may be encrypted using a homomorphic encryption, HE, algorithm and an encryption key.

A persistent memory device is disclosed. A non-volatile storage (345) may store a data, and a volatile storage (340) may cache the data. A cache controller (360) may manage access to the data in the non-volatile storage (345) and the volatile storage (340). The persistent memory device may include a storage for a table to associate a first number of dirty pages of the data to copy from the volatile storage (340) to the non-volatile storage (345) with an energy level. A second controller may be configured to copy a dirty page of the data from the volatile storage (340) to the non-volatile storage (345) based at least in part on a second number of dirty pages of the data in the volatile storage (340) exceeding the first number of dirty pages.

In the semiconductor device according to the inventive concept, part of a multi-layer wiring structure (ML) located in a wiring region (MA) of a peripheral circuit structure (PERI) may be replaced by a replacement process to form a capacitor structure (CS), and thus, there is the effect of improving electrical characteristics and reliability due to an increase in the area of the capacitor structure.

A memory device that performs a training operation on a chip select signal includes a clock divider receiving a clock signal from a host and dividing the clock signal to generate at least two internal clock signals, an internal clock selector receiving the at least two internal clock signals from the clock divider and selecting one of the at least two internal clock signals as a target internal clock signal to sample one of a high level or a low level of the chip select signal, and a sampler receiving the chip select signal from the host, receiving the target internal clock signal from the internal clock selector, and sampling the chip select signal using the target internal clock signal.

A display apparatus includes a display substrate including a plurality of pixel areas, and a plurality of light-emitting device chips on the display substrate and respectively corresponding to the plurality of pixel areas, each of the plurality of light-emitting device chips includes a stacked structure in which a first light-emitting structure, a second light-emitting structure, and a third light-emitting structure are stacked in a first direction on the display substrate, and the first light-emitting structure, the second light-emitting structure, and the third light-emitting structure are configured to generate light of different colors from each other.

Provided is a memory device including a first sense amplification circuit (42) connected to a first input and output line pair (LIO, LIOB), a pre-charge circuit (44) connected to a second input and output line pair (GIO, GIOB), and a first switch circuit (43), wherein the pre-charge circuit (44) is configured to pre-charge the second input and output line pair (GIO, GIOB) at a pre-charge voltage after the first switch circuit (43) disconnects the first input and output line pair (LIO, LIOB) from the second input and output line pair (GIO, GIOB), and wherein the first switch circuit (43) is configured to connect the first input and output line pair (LIO, LIOB) and the second input and output line pair (GIO, GIOB) to deliver a voltage of the first input and output line pair (LIO, LIOB), which is amplified by the first sense amplification circuit (42), to the pre-charged second input and output line pair (GIO, GIOB) in a read operation.

A system (1) and a method are disclosed for handling resource measurements for data collection. The method includes, based on a user equipment, UE (105), being configured with more than one bandwidth part, BWP, and a first BWP of the more than one BWP being activated, performing logging, by the UE (105), of a first channel state information, CSI, measurement result associated with a first resource, corresponding to the first BWP, as an entry of an artificial-intelligence/machine-learning, AI/ML, dataset, and transmitting, by the UE (105), the first CSI measurement result from the UE (105), based on the AI/ML dataset.

A method and electronic device for managing wireless communication using an abstinence announcement, including: a transceiver; at least one processor; and a memory configured to store at least one instruction which, when executed by the at least one processor, causes the electronic device to: associate with a wireless local area network, WLAN, as a non-access point, AP, station, STA (101-1, 101-2, 101-3, 101-4); receive, from an AP (102-1, 102-2) included in the WLAN, a frame including an abstinence announcement indicating that the AP (102-1, 102-2) intends to refrain from initiating a transmission opportunity, TXOP, with the non-AP STA (101-1, 101-2, 101-3, 101-4) during an abstinence period; and based on receiving the abstinence announcement, modify at least one network behavior of the non-AP STA (101-1, 101-2, 101-3, 101-4) during a portion of the abstinence period.

An operation method, performed by a processor of a terminal, includes identifying a first resource group corresponding to the terminal, identifying first reference signals of a first type for the first resource group, identifying channel state information, based on one or more of the first reference signals or based on a second reference signal of a second type that is associated with the first reference signals, and identifying channel characteristic information corresponding to the first resource group based on the channel state information.

A semiconductor device according to an embodiment may include a gate stacking structure (120), a channel structure, and a gate contact (172). The gate stacking structure (120) may include a plurality of air gap layers (130g) and a plurality of gate electrodes (130) alternately stacked to on each other. The channel structure may pass through the gate stacking structure (120). The channel structure may include a channel layer (140) and a gate dielectric layer (150). The gate dielectric layer (150) may include a charge storage layer (154) including a plurality of storage portions (154p) spaced apart from each other. The plurality of storage portions (154p) may correspond to the plurality of gate electrodes, respectively. The gate contact (172) may pass through the gate stacking structure (120) that includes the plurality of air gap layers (130g) and the plurality of gate electrodes (130). The gate contact (172) may be electrically connected to a connection gate electrode (130c) of the plurality of gate electrodes (130).

A terminal (100) comprises a transceiver (1320), transmission signal processing blocks (1340) comprising a plurality of first transmission signal processing blocks in a first transmission signal processing block group (300; 340) and a plurality of second transmission signal processing blocks in a second transmission signal processing block group (320), and a processor (1360), and the processor (1360) is configured to transmit, to a base station (200), a first signal through the first transmission signal processing block group (300; 340), activate, based on transmission configuration information received from the base station (200), at least one of the plurality of second transmission signal processing blocks, and based on completion of the transmitting of the first signal, transmit, to the base station (200), a second signal associated with the first signal through the second transmission signal processing block group (320), based on scheduling information received from the base station (200).

A semiconductor package including a first semiconductor chip, a plurality of second semiconductor chips stacked on the first semiconductor chip in a first direction perpendicular to an upper surface of the first semiconductor chip, an upper semiconductor chip stacked on the uppermost second semiconductor chip among the plurality of second semiconductor chips, and a dummy semiconductor chip stacked on the upper semiconductor chip and including a capacitor. The upper semiconductor chip includes an upper through via that passes through at least a portion of the upper semiconductor chip and is electrically connected to the capacitor.

Methods and devices for controlling a storage device including a non-volatile memory are provided, the methods including: reading (1321) a plurality of voltages from a target memory cell included in the non-volatile memory (220); obtaining (1322) a plurality of initial log-likelihood ratio (LLR) values by providing the plurality of voltages to an initial threshold model; generating (1323) at least one tuned model parameter based on the plurality of initial LLR values; tuning (1324) the initial threshold model based on the at least one tuned model parameter to obtain a tuned threshold model; obtaining (1325) a plurality of uncalibrated LLR values by providing the plurality of voltages to the tuned threshold model; calculating (1326) a calibration parameter based on the plurality of uncalibrated LLR values; modifying (1327) the tuned threshold model based on the calibration parameter to obtain calibrated tuned threshold model; obtaining (1328) a final predicted LLR value by providing at least one of the plurality of voltages to the calibrated tuned threshold model; and obtaining (1328) data based on the final predicted LLR values.

A system and a method are disclosed for carrier frequency planning in beamforming. The method comprises transmitting (1210), with a first access point, AP1, an AP1 frequency reference frame at an AP1 carrier frequency fc1 and obtaining (1220), with a second access point, AP2, a synchronized AP2 carrier frequency fc2 based on the AP1 carrier frequency fc1 . The method further comprises transmitting (1230), with the AP2, an AP2 frequency alignment frame using the synchronized AP2 carrier frequency fc2 . Also disclosed are system and methods for sounding results reuse.

A semiconductor cell architecture is disclosed including a merged-height cell (310), also known as a hyper or booster cell, having a cell height, CH, approximately one-and-one-half times that of a base unit cell (308) (1.5×CH). The base unit cell (308) follows a P/N/P/N vertical placement, while the merged-height cell (310) follows a P/N/N/P configuration. The merged-height cell (310) is vertically offset by about one-quarter cell height (0.25×CH) such that the nanosheet centers of NFET and PFET active regions in the merged-height cell (310) align with those in the base unit cell (308). This alignment allows direct abutment between base and merged-height cells (308, 310) without dummy filler regions, maintaining process limits on active-region jogs. The 1.5×CH architecture increases effective channel width (Weff) and drivability with reduced area penalty compared to conventional 2×CH merged-height cells (310). The merged-height cell architecture enables merged-height standard-cell libraries for sub-3 nm nodes, improving performance, area efficiency, and routing compatibility in advanced integrated-circuit design.

A system and a method are disclosed for fine-tuning an artificial intelligence/machine learning, Al/ML, model online in a wireless communication system. A user equipment, UE, (502) transmits to a base station (504) capability information of fine-tuning online one or more Al/ML models of the UE (502); receives, from the base station (504), channels and/or signals for the UE (502) to determine whether a first Al/ML model of the one or more Al/ML models of the UE (502) needs to be fine-tuned; determines to fine-tune the first Al/ML model online based on the channels and/or signals received from the base station (504) and model-generated output from the first Al/ML model; and fine-tunes the first Al/ML model to generate an output that is used for a downlink transmission.

A phase locked loop is provided. The phase locked loop includes: a digitally controlled oscillator configured to generate an output clock according to a frequency control signal; a frequency divider circuit configured to generate a feedback clock by frequency dividing the output clock based on a first divide ratio value; a phase detection circuit configured to generate a phase difference signal according to a phase difference between the feedback clock and an externally provided reference clock; a loop filter circuit configured to generate a frequency control raw signal based on the phase difference signal; and a peaking suppression circuit configured to generate the frequency control signal by limiting a fluctuation range of the frequency control raw signal.

A semiconductor device includes a channel layer (132); a barrier layer (136) positioned on the channel layer and including a material having a different energy band gap from an energy band gap of the channel layer; a gate electrode (155) positioned on the barrier layer; a gate semiconductor layer (152) positioned between the barrier layer and the gate electrode; a gate spacer (200) including a first gate spacer and a second gate spacer positioned on opposite sides of the gate semiconductor layer and spaced apart from each other; a passivation layer (310) positioned on the barrier layer and covering the gate electrode; and a source electrode (170) and a drain electrode (190) positioned on opposite sides of the gate electrode and connected to the channel layer. The first gate spacer and the second gate spacer cover side surfaces of the gate semiconductor layer and cover at least a portion of side surfaces of the gate electrode.

A semiconductor device includes first and second bit lines each extending in a first direction and adjacent to each other in a second direction perpendicular to the first direction; first and second active patterns each including a first region, a second region, and a channel region between the first and second regions, wherein the first region of the first active pattern is connected to the first bit line in a third direction perpendicular to the first and second directions, and the first region of the second active pattern is connected to the second bit line in the third direction; a word line facing the channel regions of the first and second active patterns; and a conductive shield structure disposed between the first bit line and the second bit line, and between the first region of the first active pattern and the first region of the second active pattern.

A system and a method for organizing a 3D memory circuit are disclosed. The 3D memory circuit includes a memory array and an activation circuit (235). The memory array is configured to be organized into N sections (340<1> to 340<N>). Each section has a row dimension K, a column dimension L, and a word line, WL, connected to L memory cells. The activation circuit (235) is configured to activate, in response to an activation, the WL to generate an activated WL. Each section includes a transfer circuit including a data switch and a select switch. The data switch is configured to route data between a local input/output, LIO, line and a global input/output, GIO, line. The select switch is configured to connect the LIO line to a bit line, BL, by a column select, CS, signal. The BL is connected to one of the L memory cells which is connected to the activated WL.

A method performed by an electronic device includes receiving an input data stream, loading a set of first elements among a set of elements of the input data stream to a first buffer, generating one or more bit vectors based on a comparison between the set of first elements in the first buffer and a set of second elements in a second buffer among the set of elements of the input data stream, determining a match length corresponding to a bit sequence that satisfies a determined match condition based on the one or more bit vectors, determining a mismatch length corresponding to a bit sequence that satisfies a determined mismatch condition based on the one or more bit vectors, and generating compressed data for the input data stream based on the match length and the mismatch length.

A system and a method for a data transfer in a memory circuit are disclosed. The memory circuit includes a data transfer circuit (425), a column select, CS, decoder (412), and an access decoder (414). The data transfer circuit (425) includes a select switch configured to connect a local input/output, LIO, line to a bit line, BL, of a memory cell in a memory section (420) and a data switch configured to route data between LIO line and a global input/output, GIO, line connected to a data bus in response to an access operation. The CS decoder (412) is configured to decode a first part of a column address, CA, of the access operation to generate a CS signal that enables the select switch. The access decoder (414) is configured to decode a second part of the CA (430) and an access signal to generate an access enable, AE, signal that enables the data switch.

An inverter includes a first field-effect transistor including a first channel layer, a first source/drain electrode and a second source/drain electrode disposed on opposite sides of the first channel layer, a first gate electrode facing the first channel layer, and a first gate insulating layer between the first channel layer and the first gate electrode, and a second field-effect transistor including a second channel layer, a third source/drain electrode and a fourth source/drain electrode disposed on opposite sides of the second channel layer, a second gate electrode facing the second channel layer, and a second gate insulating layer between the second channel layer and the second gate electrode. The first channel layer includes a p-type oxide semiconductor based on tellurium oxide, and the second channel layer includes an n-type oxide semiconductor based on indium oxide.