Semiconductor Components Industries

A bootstrapped switch circuit is disclosed. The bootstrapped switch circuit includes a sample transistor having a source coupled to an input terminal and a drain coupled to an output terminal. The bootstrapped switch circuit further includes a charge path to charge a bootstrap capacitor during a hold phase and a bootstrap path configured to apply a voltage of the bootstrap capacitor to the gate of the sample transistor during a sample phase. The bootstrap path includes a low-side transistor configured to couple a first terminal of the bootstrap capacitor to the source of the sample transistor during the sample phase, and a high-side transistor configured to couple a second terminal of the bootstrap capacitor to the gate of the sample transistor during the sample phase. The bootstrapped switch circuit further includes a bootstrap transistor bootstrap transistor configured to maintain an on-state of the high-side transistor during the sample phase.

A transistor is disclosed. The transistor includes a termination region extending around an exterior of a semiconductor die, a transition region located interior to the termination region, a first active region located interior to the transition region along at least a first edge of the semiconductor die, and a second active region above which a source pad area is included. The transistor further includes a gate runner including at least a first side portion located between the first active region and the second active region and extending parallel to the first edge of the semiconductor die.

An ESD protection device is disclosed. The ESD protection device comprises a first bipolar junction transistor including an emitter formed by a substrate having a first conductivity type, an open base formed by a first epitaxial region located above the substrate and having a second conductivity type, and a collector formed by a first well located in the first epitaxial region and having the first conductivity type. The ESD protection device also includes a second bipolar junction transistor having an emitter formed by the substrate, an open base formed by a second epitaxial region located above the substrate and having the second conductivity type, and a collector formed by a second well located in the second epitaxial region and having the first conductivity type. The ESD protection device further includes a trench including a dielectric material and located between the first and second epitaxial regions.

An ESD protection device is disclosed. The ESD protection device comprises a substrate having a first conductivity type, the substrate forming a collector of a bipolar junction transistor, an epitaxial region above the substrate having a second conductivity type and forming a base of the bipolar junction transistor, a first well disposed at an upper surface of the epitaxial region, the first well having the first conductivity type and forming an emitter of the bipolar junction transistor, a base-contact region having a contact-region doping concentration of the second conductivity type that is greater than an epitaxial-region doping concentration of the second conductivity type of the epitaxial region, and a second well having the first conductivity type and located adjacent to the base-contact region to restrict at least in part a contact area between the base-contact region and the epitaxial region.

A MOSFET device is disclosed. The MOSFET devices includes a MOSFET and a sense-FET monolithically integrated on a semiconductor die. A gate pad coupled to a MOSFET gate and a sense-FET gate, and a drain pad is coupled to a MOSFET drain and a sense-FET drain. The MOSFET device further includes a first source metal located above a MOSFET active area and coupled to source contacts of the plurality of MOSFET cells, and a source pad formed by a second source metal that is coupled to the first source metal. In addition, the MOSFET device includes a first current-sense metal located above a sense-FET active area and coupled to one or more source contacts of the sense-FET, and also includes a current-sense pad formed by a second current-sense metal that is coupled to the first current-sense metal and extends over a portion of the MOSFET active area.

An insulated gate bipolar transistor includes multiple semiconductor layers, a trench material, an electrically insulative layer, and an emitter conductive layer. The semiconductor layers have (i) a semiconductor surface and (ii) multiple gate trenches and multiple emitter trenches separated by multiple mesas formed through the semiconductor surface. The trench material is disposed in the emitter trenches. The electrically insulative layer is formed over the semiconductor layers. The electrically insulative layer defines multiple openings that align with the mesas and extend across the emitter trenches. The electrically insulative layer do not extend into the emitter trenches. The emitter conductive layer is formed over the electrically insulative layer. The emitter conductive layer directly contacts through the openings (i) each mesa and (ii) the trench material in each emitter trench. The emitter conductive also extends across the emitter trenches.

A method of manufacturing a semiconductor device includes providing a region of semiconductor material including a top side, an edge region, a multiple shield conductor contact area within the edge region, an active area, and an upper shield contact area. The method includes providing an active trench. The active trench includes a lower shield conductor, a first shield dielectric isolating the lower shield conductor from the region of semiconductor material, an upper shield conductor, and a second shield dielectric isolating the lower shield conductor from the upper shield conductor within the active area. The lower shield conductor and the upper shield conductor are coupled together in the multiple shield conductor contact area. The method includes providing a shield contact in the upper shield contact area coupled to the upper shield conductor in the active trench.

A trench field-effect transistor (FET) is disclosed. The trench FET includes a mesa having a source region (220) and a channel region (210) extending vertically under the source region. The trench FET further includes a gate material (216) formed with a different material compared to the mesa and contacting the sides of the channel region. In addition, the trench FET includes a shield region (212) formed under the gate material, and also includes a drain layer (206) located beneath the channel region.

According to an aspect, a method includes loading a set of weights of a neural network into a plurality of multipliers selectively loading a set of inputs into the plurality of multipliers based on a weight indication bitstream, and generating, by the plurality of multipliers, multiplication results for a node of the neural network using the set of weights and at least a portion of the set of inputs.

According to an aspect, a method includes receiving a weight of a neural network, identifying a first portion of the weight, identifying a second portion of the weight, generating a multiplication result by multiplying an input value with the first portion of the weight, and generating a scaled multiplication result based on the multiplication result and the second portion of the weight.