Semiconductor Manufacturing International (Shanghai) Patente

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An etching method and a fabrication method of semiconductor structures are provided. The etching method includes forming trenches in a to-be-etched structure, and forming a dielectric layer in the trenches. The etching method further includes etching the dielectric layer in the trenches by an etching process, and controlling at least an etching temperature of the etching process while a polymer is formed on side surface of the to-be-etched structure. During the etching process of the dielectric layer, the polymer undergoes a deposition stage and a removal stage. The deposition stage has a deposition rate of the polymer greater than an etch rate of the polymer, and the removal stage has the deposition rate of the polymer less than the etch rate of the polymer.

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A semiconductor structure, a method for fabricating the semiconductor structure and a static random access memory are provided. The method includes providing a base substrate including a substrate and a plurality of discrete fins on the substrate. The substrate includes a pull-up transistor region and a pull-down transistor region. The method also includes forming a gate structure on each fin; and forming pull-up doped epitaxial layers, in the fin on both sides of the gate structure in the pull-up transistor region. In addition, the method includes forming a first pull-down doped region connected to an adjacent pull-up doped epitaxial layer in the fin on one side of the gate structure in the pull-down transistor region. Further, the method includes forming a second pull-down doped region by performing an ion-doped non-epitaxial layer process on the fin on another side of the gate structure in the pull-down transistor region.

A method is provided for fabricating a semiconductor structure. The method includes providing a substrate including a first region for forming a first transistor and a second region for forming a second transistor. The method also includes forming a first stress layer in the substrate in the first region and a second stress layer in the substrate in the second region, wherein top surfaces of the first stress layer and the second stress layer are above a surface of the substrate. Further, the method includes forming a cover layer on each of the first stress layer and the second stress layer, and removing portions of the cover layer formed on adjacent side surfaces of the first stress layer and the second stress layer.

A method for fabricating an NAND flash memory includes providing a semiconductor substrate with a core region and a peripheral region, forming a plurality of discrete gate stack structures in the core region with neighboring gate stack structures separated by a first dielectric layer. The method further includes forming a flowable dielectric layer on the first dielectric layer and the gate stack structures, and forming a solid dielectric layer through a solidification treatment process performed on the flowable dielectric layer. Voids and seams formed in the top portion of the first dielectric layer are filled by the solid dielectric layer. The method also includes removing the solid dielectric layer and a portion of the first dielectric layer to expose a top portion of the gate stack structures, and forming a metal silicide layer on each gate stack structure.

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A CMOS image sensor (20) includes a semiconductor substrate (200), a plurality of pixel regions in the semiconductor substrate, a deep trench (201) disposed between two adjacent pixel regions and filled with a polysilicon layer (2012) doped a first conductivity type, a plurality of well regions (2031) having a second conductivity type in each of the pixel regions, a through hole (207) connected to the polysilicon material, and an metal interconnect layer (208) connected to the through hole. The deep trench filled with the doped polysilicon layer completely isolates adjacent pixel regions. A voltage applied to the metal interconnect layer extracts excess photoelectrons generated by intensive incident light to improve the performance of the CMOS image sensor.

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A method for forming a semiconductor device includes providing a substrate, the substrate including a first trench in an NMOS region and a second trench in a PMOS region. The method also includes depositing a high-K dielectric layer, a cap layer, and a P-type work function metal layer on the bottom and side walls of the first trench and the second trench, removing the P-type work function metal layer and the cap layer from the bottom and sidewalls of the first trench, depositing an N-type work function metal layer on the high-K dielectric layer in the first trench and on the P-type work function metal layer in the second trench, and depositing a metal electrode layer on the N-type work function metal layer.

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The present invention relates to the technical field of semiconductor processes, and discloses a semiconductor device and a manufacturing method therefor. The manufacturing method includes: providing a substrate structure including a substrate and a first material layer on the substrate, wherein a recess is formed in the substrate and the first material layer includes a nanowire; forming a base layer on the substrate structure; selectively growing a graphene layer on the base layer; forming a second dielectric layer on the graphene layer; forming an electrode material layer on the substrate structure to cover the second dielectric layer; defining an active region; and forming a gate by etching at least a portion of a stack layer to at least the second dielectric layer so as to form a gate structure surrounding an intermediate portion of the nanowire, where the gate structure includes a portion of the electrode material layer and the second dielectric layer. The present invention incorporates graphene into the semiconductor process and makes use of the features of graphene in a dual-gate structure.

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A method for forming a semiconductor device includes providing a substrate structure, which has a semiconductor substrate and a semiconductor fin on the substrate. The method also includes forming a catalytic material layer overlying the semiconductor fins, and forming an isolation region covering the catalytic material layer in a lower portion of the semiconductor fins. Next, a graphene nanoribbon is formed on the catalytic material layer on an upper portion of the semiconductor fin, and a gate structure is formed on the graphene nanoribbon.

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The present invention provides D flip-flops (100) and signal driving methods (fig. 8) using D flip-flops thereof. An exemplary D flip-flop includes a pulse signal generating circuit (10) configured to input a first clock signal (CP), a first data signal (D), a second data signal (Q) and a third data signal (Qb) and generate a clock pulse signal (CP_Pulse). The clock pulse signal (CP_Pulse) responds a raising-edge and a falling-edge of the first clock signal (CP). The pulse clock signal (CP_Pulse) is a pulse signal when the first data signal (D) is opposite to the second data signal (Q). The D flip-flop also includes a latching circuit (20) configured to sample and transfer the first data signal (D) and a data signal opposite to the first data signal (Db) to be used as the second signal (Q) and a fourth data (third data Qb) signal respectively when the clock signal (CP_Pulse) is at the high level.

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An input-output "I/O" receiver includes a receiving terminal (PAD), a first N-type metal-oxide-semiconductor "NMOS" transistor (N1), a reformation circuit (202), and a compensation unit (201). The receiving terminal (PAD) is coupled with an external voltage signal. The first NMOS transistor (N1) has a source electrode coupled with the receiving terminal and a gate electrode coupled with a first power supply voltage (VDD1). The reformation circuit (202) is configured to reform a voltage signal transmitted from a drain electrode of the first NMOS transistor. The compensation unit (201) includes a first PMOS transistor (P1), a second PMOS transistor (P2), and a second NMOS transistor (N2). Moreover, the compensation unit (201) is configured to provide a compensation voltage to a voltage signal (B) at the drain electrode of the first NMOS transistor thereby a maximum level of the voltage signal at the drain electrode of the first NMOS transistor (N1) reaches the first power supply voltage (VDD1).

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A flash memory device includes a substrate, an electrode layer on a portion of the substrate, the electrode layer being a work function adjusting layer or a metal silicide layer, and a memory cell. The memory cell includes a channel structure on the electrode layer and having, from the inside to the outside in this order, a channel layer in contact with the electrode layer, a tunneling insulator layer surrounding the channel layer, a charge trapping layer surrounding the tunneling insulator layer, and a barrier layer surrounding the charge trapping layer, and a plurality of gate structures surrounding the channel structure along an axial direction of the channel structure. The flash memory device may be formed on a dielectric layer, and its fabrication process is thus compatible with back end of line processes.

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A substrate alignment device includes a plurality of state detection units, each of which is configured to move from a standby position to a detection position for detecting a positional state of a substrate and return back from the detection position back to the standby position, and a multidimensional robot arm configured to receive and support the substrate, transfer the substrate to a substrate detection site, and adjust the substrate in at least one orientation or position according to the detected positional state of the substrate to position the substrate to a target position for overlay mark measurements.

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A memory and a reference circuit calibration method are provided. The memory includes: a memory array including a plurality of memory cells; a reference circuit including a reference memory cell and a reference connection terminal, wherein the reference memory cell is a same as the memory cell; a calibration circuit including a calibration connection terminal, and a mirror circuit including a first mirror terminal and a second mirror terminal, wherein the first mirror terminal is connected to the reference connection terminal, and the second mirror terminal is connected to the calibration connection terminal; a clamp circuit, configured to set one of a voltage of the reference connection terminal and a voltage of the calibration connection terminal as a preset voltage and to set the other thereof as a comparison voltage; and a comparison circuit configured to input the comparison voltage and the preset voltage, and to output a comparison result.

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