Altera Corporation

Systems or methods of the present disclosure may provide a voltage regulator design for efficient power delivery. The present disclosure includes one or more integrated circuits with one or more sectors of programmable logic circuitry and one or more voltage regulators. The present disclosure also includes a first set of layers on a front plane of a programmable logic device and a second set of layers formed using backside metallization on a back plane of the programmable logic device.

An integrated circuit (100) includes memory circuits (103) in a central region of the integrated circuit, and a network-on-chip (102) that traverses the central region. The network-on-chip (102) includes a controller circuit (104) configurable to exchange data between first and second ones of the memory circuits through the network-on-chip (102) by transmitting the data from a source in the network-on-chip (102) to a sink in the network-on-chip (102). The network-on-chip (102) is configurable to place each of the source and the sink at one of multiple locations along the network-on-chip (102).

An integrated circuit includes a delay controller circuit that generates delay signals based on a current data bit, an adjustable delay circuit that delays the current data bit, and a driver circuit that drives the current data bit outside the integrated circuit. The driver circuit transitions the current data bit at a first voltage to a second voltage over a first delay provided by the adjustable delay circuit based on the delay signals. The driver circuit transitions the current data bit at the second voltage to a third voltage over a second delay provided by the adjustable delay circuit based on the delay signals. The second voltage is less than the first voltage, and the second voltage is greater than the third voltage.

Systems or methods of the present disclosure may provide transmit circuitry that receives one or more input signals and an enable signal, the enable signal indicating whether a three-level communication scheme is enabled, and generates one or more data signals based on the one or more input signals and the enable signal. Equalization circuitry receives the one or more data signals and selectively generates a first set of equalization voltages based on the one or more data signals indicating the three-level communication scheme or selectively generates a second set of equalization voltages based on the one or more data signals not indicating the three-level communication scheme.

Systems, methods, and circuitry for dynamically mixed precision machine learning are provided. An integrated circuit may include conversion circuitry to convert input feature data to block floating point format and upper/lower splitter circuitry to split the input feature data in the block floating point format into an upper component in the block floating point format and a lower component in the block floating point format. A processing element may use only the upper component when operating in a lower-precision mode and use both the upper component and the lower component when operating in a higher-precision mode.

Integrated circuit devices, methods, and circuitry for configuring input/output (IO) circuitry for boundary scan chain testing is provided. An integrated circuit device may include a configuration register and IO configuration selector circuitry. The configuration register may define a voltage level of the IO circuitry based on a code stored in the configuration register. The IO configuration selector circuitry may determine the code based on a power-on-reset (POR) instruction.

The embodiments described herein implement a protocol decoder tool designed by a hardware engineer in a hardware description language (HDL) in a simulator tool for testing and/or in a signal analysis system for decoding protocols in real-time. For example, a user (e.g., hardware engineer, hardware designer, protocol designer) may design a protocol using an HDL and design a protocol decoder tool for decoding the protocol in the HDL. Register transfer level (RTL) files with protocol decoder logic in the HDL may be converted from the HDL to a second language by a converter, compiled into a decoder module by a compiler, and executed in a signal analysis system as the protocol decoder tool. As such, errors in misinterpretation of protocol specifications may be reduced.

An integrated circuit includes filter circuits that partition a wideband digital signal in a frequency domain to generate narrowband digital signals each having a different frequency band, digital-to-analog converter circuits that convert the narrowband digital signals to generate analog signals, and an analog combiner circuit that combines the analog signals into a single wideband analog signal.

An integrated circuit includes a digital signal processing circuit. The digital signal processing circuit includes fixed point multiplier circuits, floating point multiplier circuits, and adder circuits. The digital signal processing circuit is configurable to implement a reduction of floating point multiplication operations based on floating point inputs to the digital signal processing circuit using the fixed point multiplier circuits, the floating point multiplier circuits, and the adder circuits.

A configurable integrated circuit includes a network-on-chip and a response buffer circuit coupled to the network-on-chip. The response buffer circuit includes a direct memory access circuit and a controller circuit. The direct memory access circuit generates read requests and write requests to access memory circuits. The controller circuit provides the read requests and the write requests to the memory circuits through the network-on-chip. The controller circuit exchanges data with the memory circuits for the read requests and the write requests.