Altera Corporation

Integrated circuit devices, methods, and circuitry for configuring input/output (IO) circuitry for boundary scan chain testing is provided. An integrated circuit device may include a configuration register and IO configuration selector circuitry. The configuration register may define a voltage level of the IO circuitry based on a code stored in the configuration register. The IO configuration selector circuitry may determine the code based on a power-on-reset (POR) instruction.

The embodiments described herein implement a protocol decoder tool designed by a hardware engineer in a hardware description language (HDL) in a simulator tool for testing and/or in a signal analysis system for decoding protocols in real-time. For example, a user (e.g., hardware engineer, hardware designer, protocol designer) may design a protocol using an HDL and design a protocol decoder tool for decoding the protocol in the HDL. Register transfer level (RTL) files with protocol decoder logic in the HDL may be converted from the HDL to a second language by a converter, compiled into a decoder module by a compiler, and executed in a signal analysis system as the protocol decoder tool. As such, errors in misinterpretation of protocol specifications may be reduced.

An integrated circuit includes filter circuits that partition a wideband digital signal in a frequency domain to generate narrowband digital signals each having a different frequency band, digital-to-analog converter circuits that convert the narrowband digital signals to generate analog signals, and an analog combiner circuit that combines the analog signals into a single wideband analog signal.

An integrated circuit includes a digital signal processing circuit. The digital signal processing circuit includes fixed point multiplier circuits, floating point multiplier circuits, and adder circuits. The digital signal processing circuit is configurable to implement a reduction of floating point multiplication operations based on floating point inputs to the digital signal processing circuit using the fixed point multiplier circuits, the floating point multiplier circuits, and the adder circuits.

A configurable integrated circuit includes a network-on-chip and a response buffer circuit coupled to the network-on-chip. The response buffer circuit includes a direct memory access circuit and a controller circuit. The direct memory access circuit generates read requests and write requests to access memory circuits. The controller circuit provides the read requests and the write requests to the memory circuits through the network-on-chip. The controller circuit exchanges data with the memory circuits for the read requests and the write requests.

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Devices and methods for providing communication including: an antenna; a proximity sensor configured to detect human presence near the antenna and generate an interrupt signal when human presence is detected; a radio frequency (RF) circuitry configured to provide an RF signal via a transmission line to the antenna for transmission over the air; a voltage source configured to provide a power supply voltage to the proximity sensor; and a voltage-change detection circuitry configured to detect the interrupt signal; a first bias tee circuit electrically connecting the antenna, the proximity sensor, and the transmission line to each other; a second bias tee circuit electrically connecting the RF circuitry, the voltage source, the voltage-change detection circuitry, and the transmission line to each other; and a modem circuitry configured to determine a transmission power of the antenna based on the interrupt signal, the modem circuitry electrically connected to the RF circuitry.

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