STMicroelectronics International Patente

A stream-triggered multi-thread accelerator includes a data streaming interface, a memory, vector processing circuitry and scheduling circuitry. The data streaming interface, in operation, receives and transmits data streams of a plurality of data streaming channels. The memory, in operation, stores a plurality of instruction threads. The plurality of instruction threads include wait-for-trigger instructions specifying streaming data trigger thresholds, and instructions having data streaming channels of the plurality of data streaming channels as operands. The vector processing circuitry is coupled to the memory and to the data streaming interface. The vector processing circuitry, in operation, executes instruction threads of the plurality of instruction threads. The scheduling circuitry, in operation, schedules execution of instruction threads of the plurality of instruction threads by the vector processing circuitry based on the streaming data trigger thresholds of the wait-for-trigger instructions.

A hardware accelerator includes a stream switch, a programmable component and multi-context control circuitry. The stream switch streams a data stream to the programmable component and to the multi-context control circuitry. The multi-context control circuitry, in a configured context mode of operation, counts valid data transactions of the data stream streamed to the programmable component, and controls a sequence of processing operations to be performed on the data of the data stream by the programmable component based on the counting of the valid data transactions of the data stream and on stored configured-context mode configuration information. The multi-context control circuitry, in a hybrid context mode of operation, monitors the data stream to read embedded context tags, and controls a sequence of processing operations to be performed on the data based on the embedded context tags, on the counting of the valid data transactions, and stored hybrid-context mode configuration information.

A process for manufacturing a power electronic device (100) having a plurality of elementary cells, envisages: providing a substrate (2), having a first electrical conductivity (n) and a first doping value and defining a front surface (1a); forming first CSL - Current Spreading Layer - regions (6) in a deep position of the substrate (2) at a distance from the front surface (1a), having the first electrical conductivity (n) and a second doping value, greater than the first doping value; forming first doped regions (10) of elementary cells of the power electronic device (100) above the first current spreading regions (6), having a second conductivity type (p) and separated from each other in a direction (x) parallel to the front surface (1a) by intercell regions (2') of the power electronic device (100); forming second CSL - Current Spreading Layer - regions (16) at the intercell regions (2'), having the first electrical conductivity (n) and distinct and independent characteristics with respect to the first current spreading regions (6).

A voltage-regulator (50) provides regulated-voltage to a digital circuit (60) from a supply-voltage input (VDD). The regulator (50) includes an amplifier (51) comparing a reference-voltage (Vbg) with the regulated-voltage to control a source-gate voltage of an output-transistor (MP1). A source-gate voltage-boosting circuit improves the response of the regulator (50) for operations with high current-demands like high-frequency digital-interface communication. The boosting-circuit includes a capacitor (C) switchable connected between the supply-voltage (VDD) and either a bias current source (IB3) or the gate of the output-transistor (MP1). A phase-generator (57) controls two switches (S1, S2) through non-overlapping control-signals (φint, φsh), implementing an integration-phase and a sharing-phase. During integration, the capacitor (C) charges to a voltage above the source-to-gate voltage of the output-transistor (MP1). During sharing, this charged capacitor (C) connects to the gate of the transistor (MP1), boosting the source-to-gate voltage to increase current sourcing capability during high-frequency digital circuit operation. A clock-gating circuit (55) enables the phase-generator (57) in response to clock activation, synchronizing the boost operation with periods of increased current demand.

A voltage comparison circuit (20, 30) is disclosed. A measurement circuit (20) is configured to generate a measurement signal (V_S) indicative of an input voltage (V_IN), wherein the measurement circuit (20) comprises a voltage divider (RA, RB). The collectors of a first npn bipolar transistor (Q1) and a second npn bipolar transistor (Q2) are coupled to a supply voltage (VDD), and the bases of the first npn bipolar transistor (Q1) and the second npn bipolar transistor (Q2) are coupled to an intermediate node (A) of the voltage divider (RA, RB). A first resistance (R1) is connected between the emitter of the first npn bipolar transistor (Q1) and ground (102), and a second resistance (R2) is connected between the emitter of the second npn bipolar transistor (Q2) and the emitter of the first npn bipolar transistor (Q1). An emitter area of the second bipolar transistor (Q2) is greater than an emitter area of the first bipolar transistor (Q1).A comparison circuit (32, 34, 36, 40) is configured to generate a comparison signal (PG) as a function of a first current (I_Q1) flowing through the collector of the first npn bipolar transistor (Q1) and a second current (I_Q2) flowing through the collector of the second npn bipolar transistor (Q2). Specifically, in response to determining that the first current (I_Q1) is greater than the second current (I_Q2), the comparison circuit (32, 34, 36, 40) asserts the comparison signal (PG).According to various embodiments, the voltage comparison circuit (20, 30) comprises an n-channel FET (M0) having a drain connected to the intermediate node (A), a source connected to the bases of the first npn bipolar transistor (Q1) and the second npn bipolar transistor (Q2) and a gate connected to a bias voltage (V_B), wherein the bias voltage (V_B) corresponds to or is smaller than the supply voltage (VDD).

La présente description concerne un circuit de calcul (100) comprenant :- au moins un cœur de calcul (102) basé sur une architecture sur une architecture en pipeline à ordinateur à jeu d'instructions réduit, RISC-V ;- un ou plusieurs circuits de mémoire (128) configurés pour mettre en œuvre un calcul en mémoire, IMC ;et dans lequel le cœur de calcul comprend un étage d'exécution (108) configuré pour utiliser lesdits un ou plusieurs circuits de mémoire pour mettre en œuvre l'IMC.

Microelectromechanical -MEMS- device (35) formed by a first substrate (1'), having a first and a second main face (35A, 1B) and accommodating integrated electrical components (10) and external connection vias (33) extending through the first substrate (1'); a second substrate (2'), having a first and a second main face (2A, 25B) and accommodating conductive vias (17) extending between the first and second main surfaces of the second substrate, the first main face (25B) of the second substrate (2') coupled to the second main face (1B) of the first substrate (1') and the conductive vias (17) coupled to the external connection vias (33); and a third substrate (3'), having a main face (3A) and accommodating MEMS structures (19), the main face (3A) of the third substrate (3') coupled to the second main face (25B) of the second substrate (2'). The conductive vias (17) and the external connection vias (33) electrically couple the first face (35A) of the first substrate (1') to the MEMS structures (19).

La présente description concerne un transistor (43) HEMT comportant : - une première couche semiconductrice (13) ; et - une grille (45) disposée sur une première face de la première couche semiconductrice (13), dans lequel la grille (45) comprend une alternance d'au moins deux premières couches (451) et d'au moins trois deuxièmes couches (453), les premières couches (451) étant dopées en magnésium et en au moins l'un des éléments dopants choisi parmi le silicium et l'oxygène et les premières couches (451) ayant une concentration en éléments dopants supérieure à la concentration en éléments dopants dans les deuxièmes couches (453).

A neural processing unit implements a neural network and includes a decompression unit including a plurality of decompression cores. During operation of the neural network, compressed kernel data is streamed from an onboard storage to the decompression unit. The decompression unit includes multiple decompression cores. The decompression unit selectively configures the decompression cores to utilize a plurality of decompression algorithms and switches between the multiple decompression algorithms on-the-fly to properly decompress the compressed kernel data in a lossless manner.

According to an embodiment, a wireless power receiving device (120) includes a demodulator (212) that generates carrier cycle data (SYS_CNT) from a received frequency-shift keying modulated signal (FSK_IN) with dithering. A highpass filtering circuit (404) extracts offset values from the carrier cycle data. A polyphase filtering circuit (406) includes multiple smoothing filters (704) and distributes the extracted offset values among these filters based on a dithering pattern length. A compensation circuit (408) stores smoothed offset values from the polyphase filtering circuit (406) in a dithering table (802) during an evaluation window and applies these stored values to compensate carrier cycle data during subsequent demodulation.

A circuit, comprising: a switching circuit stage comprising first and second half bridges comprising a first, high-side DMOS transistor and a second, low-side DMOS transistor, the first half bridge (HB1) and the second half bridge (HB2) comprising respective output nodes between the high-side DMOS transistor and the low-side DMOS transistor therein, the output nodes configured for supplying an electrical load via respective filter networks between the output nodes and the load; control circuitry (60) coupled to the switching circuit stage and configured to control switching sequences of the high-side and low-side transistors in the first (HB1) and second (HB2) half bridges wherein a first pair of DMOS transistors comprising the high-side DMOS transistor in one (HB2 resp. HB1) of the half bridges (HB1, HB2) and the low-side DMOS transistor in the other of the half bridges (HB1, HB2) is switched to a non-conductive state, and a second pair of transistors comprising the high-side DMOS transistor in the other (HB1 resp. HB2) of the half bridges (HB1, HB2) and the low-side DMOS transistor (L2 resp. L1) in the one (HB2 resp. HB1) of the half bridges (HB1, HB2) is switched to a conductive state. The circuit comprises: a current flow line between the output nodes in the first half bridge (HB1) and the second half bridge (HB2), the current flow line comprising an inductance having opposed terminals coupled to a first switch and a second switch, the first switch and the second switch selectively switchable between a non-conductive state and at least one conductive state; first and second capacitances coupled with the output nodes of the first half bridge (HB1) and the second half bridge (HB2). The control circuitry (60) is configured to switch the first and second switches to the at least one conductive state at intervals in said switching sequences between switching the first pair of DMOS transistors to a non-conductive state and switching the second pair of DMOS transistors to a conductive state. The control circuitry (60) is configured to provide control signals to switch at least one of said first and second switches based on a delay among a first output signal at said first output node and a second output signal at said second output node.

La présente description concerne un procédé de mise en oeuvre d'une opération de dérivation (400) de clé d'un algorithme de chiffrement adaptée à recevoir une première clé et à fournir une deuxième clé, lesdites premières et deuxièmes clés comprenant chacune un nombre N de bytes disposés sous forme matricielle, dans laquelle des premiers bytes d'une ligne de bytes d'un premier rang de ladite deuxième clé est calculée en utilisant : - des deuxièmes bytes d'une ligne de bytes du premier rang de ladite première clé ; et - un seul troisième byte d'une ligne d'un deuxième rang, différent du premier rang, de ladite première clé.

The proposed solution is designed for IGBT and discrete devices with vertical gate; the proposed method includes: trench formation, including lithography and etching, in a wafer; oxidation to grow gate dielectric; polysilicon filling with a thin layer to form first gate conductive layer; a second dielectric deposition and recession to fill half of the trench from the bottom up to a fixed depth; trench filling with polysilicon to form a second gate conductive layer. The second dielectric can be chosen with a dedicated stress and a dedicated recession, to counterbalance the polysilicon stress and reduce wafer warpage.

A microelectromechanical device (1) includes: a support body (2); a movable mass (Y4), constrained to the support body (2) with a relative degree of freedom with respect to at least a first direction (Y) parallel to the support body (2), and comprising a frame portion (6) delimiting an opening (7); and a damping and stopping structure (5), anchored to the support body (2) and accommodated in the opening (7) of the movable mass (Y4). The movable mass (Y4) comprises a plurality of first elongated elements (65) defined by respective plates perpendicular to the first direction (Y) and extending in the opening (7) from the frame portion (6) in a comb-like configuration. The damping and stopping structure (5) comprises a plurality of second elongated elements (55) anchored to the support body (2), defined by respective plates perpendicular to the first direction (Y) and extending towards the frame portion (6) of the movable mass (Y4) in a comb-like configuration. The second elongated elements (55) are interdigitated with the first elongated elements (65). The damping and stopping structure (5) further comprises a plurality of stopping elements (56) configured to limit movements of the movable mass (Y4) along at least the first direction (Y).

The present disclosure relates to a system (1) comprising a light emitting module (Tx) and a light receiving module (Rx). The emitting module has a light source (100) emitting light for illuminating one or more targets. The receiving module (Rx) receives, within a field of view (112), light reflected by the one or more targets. The receiving module (Rx) comprises a light sensor (110) and a multilayer interferometric angular filter (114) above the sensor (110). The filter (114) filters out light that reaches the filter (114) with angles outside of the field of view (112).

An integrated circuit for emulating a full frame buffer for a display controller comprises a frame buffer physical memory space (106); a graphics framework module (114) to render a plurality of image frames to be displayed, each image frame rendered in two or more equal size logical blocks corresponding to a different portion of the image frame; and a controller module (110) configured to read each rendered block from the frame buffer and provide each rendered block to the display (112). The graphics framework module writes each block sequentially into the frame buffer. As the controller module is reading each rendered block from the frame buffer, the graphics framework module renders a different part of a same block or a subsequent block of the same image frame, or a first block of a subsequent image frame.

La présente description concerne un procédé de fabrication d'un filtre (400) à ondes acoustiques de volume comprenant les étapes successives suivantes :a) prévoir un substrat semiconducteur (103) ;b) former des première (105C) et deuxième (405) cavités d'air enterrées dans le substrat semiconducteur (103), la première cavité d'air (105C) étant interposée entre la deuxième cavité d'air et une face (103T) supérieure du substrat semiconducteur (103) et présentant des dimensions latérales inférieures à celles de la deuxième cavité d'air ; etc) amincir le substrat semiconducteur (103) par formation de tranchées (105P) entourant la première cavité d'air (105C) et débouchant dans la deuxième cavité d'air.

Selon un aspect, il est proposé un circuit intégré comprenant un circuit (GENC) de génération en mode courant d'un signal à modulation de largeur d'impulsions, ce circuit (GENC) de génération comportant un circuit (DAC) de conversion numérique-analogique utilisé pour réaliser une compensation de pente d'un signal (CURS_V) généré par un capteur de courant et ayant une tension comprise entre une tension de référence et un seuil de tension, ledit circuit (DAC) de conversion numérique-analogique comprenant :- un module numérique configuré pour générer un signal numérique, et- un module de conversion configuré pour convertir ledit signal numérique en un signal analogique de compensation de pente, dans lequel le signal numérique est généré à partir d'une rampe numérique écrêtée de sorte que le signal analogique de compensation de pente présente une tension comprise entre la tension de référence et ledit seuil de tension.

The present disclosure is directed to a power module that powers and controls various electronics, such an electric motor of an electric vehicle. The device includes a plurality of dies on a substrate, and a molding covering the dies and the substrate. The substrate is positioned on a heat sink. Connection pins are electrically coupled to the dies, and extend from the dies, through the molding, and into a printed circuit board. The printed circuit board is spaced from an upper surface of the molding.

An amplifier circuit based on Doherty amplifier architecture comprises a first signal splitter (13₁, 100₁) coupled to an input pre-amplifier (14) and configured to receive an input signal (RF_IN). The first signal splitter (13₁, 100₁) comprises a first passive splitter network (13₁) and a first splitter amplifier (100₁). The first passive splitter network (13₁) is configured to forward a first portion (α_M) of the input signal (RF_IN) towards a first amplifier (11) and a second portion (1-α_M) of the input signal (RF_IN) towards the first splitter amplifier (100₁). One or more secondary signal splitters (300) are provided, wherein the or each secondary signal splitter (300) is configured to receive a respective input signal coming from the first splitter amplifier (100₁) in the first signal splitter (13₁, 100₁) and comprises a passive secondary splitter network (300) configured to forward a first portion (α_A1) of the respective input signal towards a respective secondary amplifier (21) and a second portion (1-α_A1) of the respective input signal towards a respective further secondary amplifier (31). Combiner circuitry (200) provides at an output node (RF_OUT) an output signal resulting from a combination of an output signal from the first amplifier (11), the respective secondary amplifier (21), and the respective further secondary amplifier (31).

A packaged device having conductive pillars coupled with a substrate and connecting pins in openings of the conductive pillars. The device further including a molding compound on the substrate and conductive pillars. Methods of coupling connecting pins in the substrate without the use of pinholders. The methods including forming openings in the molding compound and conductive pillars and inserting the pins in the openings of the conductive pillars.

A conversion architecture (10) comprising a Continuous Time Sigma Delta Analog to Digital Converter (11) comprising a loop filter (111) followed by an analog to digital converter (112) and a feedback loop (113, 113', 116) feeding back the output (v) of said analog to digital converter (112) through an internal digital to analog converter (113; 113') to obtain (110) an error signal (e(t)) with respect to a input signal (u, s(t)), which is fed to said loop filter (111), an output digital signal (ADC_out) of the analog to digital converter (112) being fed to a decimation chain of decimators (14), a local oscillator (12) feeding a clock signal (CLK_ADC) to said analog to digital converter (112), and, through a frequency divider (13), to said chain of decimators (14), wherein said conversion architecture (10) further comprisesa circuit arrangement (116; 116, 24) configured to obtain a calibration tone (CT) by a divided frequency (CK3) outputted by said frequency divider (13) to said chain of decimators (14) and inject said calibration tone (CT) in said feedback loop (113', 116), in particular in the input path of said analog to digital converter (112),a calibration arrangement (22, 23) which comprisesa spurious tone estimation module (22) configured to obtain an estimation (SE) of the power of a spurious tone (2th_spur) in said output signal (v) based on a decimated signal (v₁) taken in said decimation chain (14), anda calibration unit (13) receiving said estimation (SE) of the power of a spurious tone (2th _spur) and configured to send a calibration signal (DAC_CAL) as function of said estimation (SE) of the power of a spurious tone to said digital to analog converter (113'), which comprises an output adjustment arrangement (115; 1131, 1132) configured to adjust an output signal (DAC'_out) of said internal digital to analog converter (113) based on said a calibration signal (DAC_CAL).

Procédé de transfert de données sur une liaison (106) SPI à cinq fils entre un circuit maître (102) et un circuit esclave (104), dans lequel :- les données sont transférées par paquets (30) comprenant chacun une charge utile (34) et un en-tête (32) spécifiant la longueur de la charge utile, et- lors d'un transfert de données entre les circuits maître et esclave, le circuit maître définit un nombre N d'octets à transférer, puis détermine, après un transfert de N octets du circuit maître au circuit esclave et de N octets du circuit esclave au circuit maître, un nombre d'octets restants à transférer du circuit esclave au circuit maître à partir d'une valeur de la longueur de la charge utile incluse dans l'en-tête d'un paquet de données transféré du circuit esclave au circuit maître, cette valeur étant lue par le circuit maître.

The present disclosure relates to a processing system (10a) comprising a safety monitor circuit (SM; SM_TH) configured to generate an error signal (ERR) by monitoring the operation of the processing system (10a). The processing system (10a) comprises also a non-volatile memory (104) configured to store a count value, a hardware safety-time monitor circuit (30) configured to generate a further error signal (ERR_T) as a function of the error signal (ERR), and a fault collection and error management circuit (120) configured to generate one or more reaction signals (IR; ER) as a function of the further error signal (ERR_T). The hardware safety-time monitor circuit comprises a counter (302) configured to selectively increase a count value. Specifically, in response to switching on the processing system (10a), the hardware safety-time monitor circuit (30) transfers the stored count value from the non-volatile memory (104) to the counter (302). Moreover, the hardware safety-time monitor circuit (30) determines whether the error signal (ERR) is asserted. In response to determining that the error signal (ERR) is asserted, the hardware safety-time monitor circuit (30) increases via the counter (302) the count value. Moreover, the hardware safety-time monitor circuit (30) determines whether the count value reaches or exceeds a maximum value (CM). In response to determining that the count value reaches or exceeds the maximum value (CM), the hardware safety-time monitor circuit (30) asserts the further error signal (ERR_T). Moreover, in response to determining a switching off of the processing system (10a) and/or periodically, the hardware safety-time monitor circuit (30) transfers the count value from the counter (302) to the non-volatile memory (104), whereby the count value is a cumulative count value.

A power module (30) has a multilayer support (50) forming a dissipating plate (49) and conductive islands (55, 56). A first die (51A) has a lower face coupled to the first island (55) and a second die (51B) has a lower face coupled to the second island (56). A package (31) encapsulates the support (30), the first and the second dice (51A, 51B), with the dissipating plate (49) formed in an opening of a lower main surface (32A) of the package (31) and flush therewith. A first power pin (36) protrudes from a first side surface (32A) of the package and is coupled to a first pad (61) of the first die (51A). A second power pin (38) protrudes from a second side surface (32B) of the package and is coupled to a first pad (61) of the second die (51B). A saddle element (70) extends at a distance over the first die (51A) and is formed by a power terminal (47) flush with an upper main surface (33A) of the package (31) and by legs (72) extending from the power terminal and bonded to the first island (55).

La présente description concerne une antenne (220) comprenant : - une première fente (221) ; - une deuxième fente (222) parallèle à la première fente (221) ; - une troisième fente (223) ; - une quatrième fente (224) étant parallèle à la troisième fente (223), dans lequel lesdites première et deuxième fente (221, 222) sont disposées de façon symétrique par rapport à un premier axe reliant les milieux des troisième et quatrième fentes (223, 224).

An in-bag detection method computes a plurality of features from sensors data and, through an AI model, performs a classification of the state of motion of an electronic device based on the plurality of features. The method then performs a meta-classification over an output of the AI model by using counters for each of the values that the output can assume to check for consistency of the output. Once the counters of the meta-classifier of the output of the AI model have reached consistency, an inbuilt stability mechanism is triggered. The inbuilt stability mechanism does not require allocation of timers or other external resources. Therefore, instead of calculating the entire plurality of features needed by the AI models, only a subset of features related to motion is calculated.

A high-speed frequency divider (100), a method for generating an output signal (110) proportional to an input signal (106) by a frequency division factor (102), and a phase-locked loop comprising a high-speed frequency divider (100) are provided. The high-speed frequency divider (100) comprises a reduced frequency clock, an asynchronous clock divider, and clock selection circuitry. The reduced frequency clock is generated by dividing an input signal (106) by a clock reduction factor (104). The asynchronous clock divider updates an initial programmed count in synchronization with the reduced frequency clock to generate a frequency divided signal. The initial programmed count is based on the frequency division factor and the clock reduction factor (104). Clock selection circuitry selects a phase of the reduced frequency clock based on a received selection signal. The output signal (110) is based on the frequency divided signal and the selected phase of the plurality of phases.

Sensor (12), of the micro-electromechanical type, for detecting infrared, IR, radiation, comprising: a main body (32) with a buried cavity (34), and a frame portion (42) facing the cavity (34); a suspended mass (38) that is suspended in the cavity (34), has an active area in a first plane (XY) and comprises at least one TMOS (20) configured to detect IR radiation; and an elastic group (40) extending in the cavity (34) between the suspended mass (38) and the frame portion (42), to elastically couple the suspended mass (38) to the frame portion (42). The elastic group (40) comprises at least a first (41a), a second (41b), a third (41c) and a fourth (41d) spring, the springs (41a-41d) being of the folded type and being coupled to the suspended mass (38) at respective vertices of the suspended mass (38) in the first plane (XY), and each spring (41a-41d) has a cross-section with an area that depends on the active area of the respective suspended mass (38).

The present disclosure is directed to a stacked assembly including a polycrystalline Silicon Carbide (SiC) substrate on which a monocrystalline SiC layer and one or more epitaxial layers are stacked. The one or more epitaxial layers are completely separated from the polycrystalline SiC substrate by the monocrystalline layer, which is stacked on the polycrystalline SiC substrate such that the monocrystalline SiC layer is between the one or more epitaxial layers and a respective surface of the polycrystalline SiC substrate. The present disclosure is further directed to one or more embodiments of methods of manufacturing one or more embodiments of the stacked assemblies.

A semiconductor die (14) is arranged at a die pad (10) of a leadframe (21) comprising an array of electrically conductive leads (12, 22) around the die pad (10). The array including a first (12) and a second (22) set of electrically conductive leads (22).At least one conductive lead in the first set of electrically conductive leads (22) comprises a base lead portion (22A) co-planar with the die-pad (10) and a raised lead portion (22B), wherein the die pad (10) is arranged at a downset location with respect to said raised lead portion (22B).The semiconductor die (14) is electrically coupled to leads (12) in the second set of electrically conductive leads (12) via electrically conductive wires (16) extending therebetween.The semiconductor die (14) is electrically coupled to the at least one conductive lead (22) in the first set of electrically conductive leads (22) by applying onto the semiconductor die (14) and the electrically conductive wires (16) an electrically conductive clip (28) comprising an electrically conductive protrusion (280) electrically coupled to the semiconductor die (14) as well as at least one distal portion (282) electrically coupled to the raised lead portion (22B) of the at least one conductive lead (22) in the first set of electrically conductive leads (22).

La présente description concerne un procédé et un dispositif de communication en champ proche utilisant une trame d'interrogation (401) comprenant au moins une donnée paramétrable (402).

La présente description concerne un dispositif de commande (100) d'un commutateur de puissance (200) à trois électrodes (202, 204, 206), comprenant : - un circuit de détection (102) comprenant des transistors bipolaires (108, 110, 110) couplés à une première électrode de puissance (202) du commutateur de puissance, et configuré pour extraire un courant de détection dont la valeur est proportionnelle à celle d'une tension entre la première et une deuxième électrodes de puissance (202, 204) du commutateur de puissance lorsque le commutateur de puissance est bloqué ; - un circuit d'amorçage (104), couplé à une électrode de commande (206) du commutateur de puissance et au circuit de détection, et configuré pour délivrer un courant d'amorçage non nul sur l'électrode de commande lorsque le courant de détection est nul et qu'un signal de commande d'amorçage non nul est reçu sur une entrée de commande (106) du circuit d'amorçage.

Dispositif (100) de limitation d'un courant, comportant : - un amplificateur différentiel (110) configuré pour égaliser des tensions aux bornes d'un transistor de puissance (106) et d'un transistor de mesure (108) ; - un circuit de régulation (112) d'un courant de sortie du dispositif de limitation de courant, comprenant un amplificateur de transconductance (114) configuré pour limiter le courant de sortie lorsqu'un potentiel électrique de sortie de l'amplificateur différentiel est supérieur ou égal à un potentiel électrique de référence proportionnel à un courant de référence dont la valeur est égale à I<LIMIT>/(N.M), avec I<LIMIT> correspondant à une valeur limite de courant, N correspondant à un rapport de dimensions entre le transistor de puissance et le transistor de mesure, et M correspondant à un rapport de dimensions entre des transistors (116, 118) d'un miroir de courant couplé au transistor de mesure.

A double-sided cooling (DSC) semiconductor package (213) is summarized as including a first assembly having a plurality of pillars (202) that extend outward from a first heat sink or dissipation structure (102) and at least one die (204) that is pre-coupled to the first heat sink or dissipation structure (102). A second assembly includes a plurality of flanges (210, 240) that are pre-welded or pre-coupled to a second heat sink or dissipation structure (104). The first assembly and second assembly are pre-formed before being coupled together. After the first assembly and the second assembly have been formed, the first assembly is coupled to the second assembly. After the pre-formed stacked semiconductor assembly has been formed, a molding compound (215) is applied to form the first embodiment of the double-sided cooling (DSC) semiconductor package or device.

La présente description porte sur un circuit de commutation (205) comprenant au moins un premier transistor bipolaire configuré pour être couplé à au moins un composant électrique (106, 109, 506, 507) à commuter, le transistor bipolaire (60) ayant une première électrode de conduction couplée à un potentiel électrique de référence par l'intermédiaire d'au moins un composant résistif (61) ou inductif ou un deuxième transistor (71).

The present description concerns an encryption/decryption unit (120), implementing an encryption/decryption algorithm, and comprising a control unit (350):- dedicated to the encryption/decryption unit; and- configured to deny access, by a bus (162, 170, 172, 174) external to the encryption/decryption unit, during data decryption and encryption operations, to the content of memory elements (206, 208) used to store data decrypted by the encryption/decryption unit (120).

La présente description concerne un procédé de mise à jour d'un ou plusieurs programmes (222, 309) d'un microcontrôleur (100), le procédé comprenant la mise à jour individuelle de différentes images desdits un ou plusieurs programmes (222, 309), la mise à jour de chacune de ces images comprenant : - la sélection d'un programme à exécuter, parmi plusieurs programmes, lors d'un démarrage du microcontrôleur ; - la sélection d'un ou plusieurs emplacements mémoires desdits un ou plusieurs programmes (222, 309), dans lequel charger une image servant à la mise à jour ; et - la mise à jour de données de versions, et de dépendance d'images, desdits un ou plusieurs programmes (222, 309), contenues dans un programme de mises à jour (ROT).

An integrated photonics device (100), such as a thermal phase shifter, for instance, comprises: a substrate of integrated photonics material having an optical waveguide (110) extending therealong as well as first (112a) and second (112b) lateral strips extending sidewise of the optical waveguide (110) and thermally coupled therewith; first (115a) and second (115b) heat transfer formations, such as arrays of copper pillars, configured to transfer heat from a proximal end distanced away from the first lateral strip (112a) and the second lateral strip (112b) in the substrate of integrated photonics material towards a distal end thermally coupled to the first lateral strip (112a) and the second lateral strip (112b) in the substrate of integrated photonics material; and first (130a) and second (130b) electric heaters thermally coupled with the proximal ends of the first (115a) and second (115b) heat transfer formations. Heat generated by the first (130a) and second (130b) electric heaters is transferred to the optical waveguide (110) via the first (115a) and second (115b) heat transfer formations and the first (112a) and second (112b) lateral strips in the substrate of integrated photonics material.

A deployment circuit (105) for controlling the deployment of a pyrotechnic device (30) is disclosed. The deployment circuit (105) comprises a deployment driver circuit (20) configured to energize the pyrotechnic device (30) by connecting (20a, 20b) respective terminals (PR, PF) to a supply voltage (V_SUP), diagnostic circuitry (160) configured to perform diagnostic controls on the deployment circuit (105), a communication interface (SCLK, SDI, SDO, NCS) configured to be connected to a microcontroller (11), a terminal configured to be connected to the microcontroller (11) in order to provide a fault signal (FAULT) to the microcontroller (11) and a control circuit (110).Specifically, the control circuit (110) comprises a hardware Finite-State Machine configured to execute one or more diagnostic routines (300, 350, 360, 370), wherein each diagnostic routine (300, 350, 360, 370) comprises a sequence of diagnostic operations (301-307; 351-356; 363-364; 374-375). In each diagnostic operation, the control circuit (110) is configured to generate control signals for the diagnostic circuitry (160) in order to execute a respective diagnostic operation of the deployment circuit (105), monitor one or more signals (CS, DS) provided by the diagnostic circuitry (160), and determine whether the one or more signals (CS, DS) indicate one or more faults of the deployment circuit (105). In response to determining that the one or more signals (CS, DS) indicate one or more faults of the deployment circuit (105), the control circuit (110) asserts the fault signal (FAULT) and stores a fault code (ZF) indicative of the fault detected. Moreover, the control circuit (110) is configured to receive via the communication interface (SCLK, SDI, SDO, NCS) a request and, in response to the request, transmit the stored fault code (ZF).