Intel Patente

Techniques are provided herein to form semiconductor dies with a thermally conductive bond interface to enhance the thermal dissipation from the semiconductor devices. A frontside interconnect region is provided above a semiconductor device layer to, for example, route signals between various semiconductor devices in the device layer. A thermally conductive bond layer may be provided above the frontside interconnect region, such as on a top-most layer of the frontside interconnect region. The thermally conductive bond layer includes a metal such as titanium, ruthenium, copper, or generally any material having a thermal conductivity of at least 1.5 W/m·K. The bond layer may be formed on a material layer that is deposited first on the frontside interconnect region. The material layer may be any of diamond, silicon carbide, copper, or aluminum nitride, to name a few examples.

Embodiments disclosed herein may include an apparatus with a substrate. In an embodiment, an opening is formed through the substrate. In an embodiment, a layer is provided over a sidewall of the opening, and the layer comprises a first magnetic material, and a plug is in the opening. In an embodiment, the plug comprises a second magnetic material that is different than the first magnetic material. In an embodiment, a first via is through the plug, and a second via may be formed through the plug.

Bridge die interposer packages, and related apparatuses, systems, and techniques are discussed. An interposer package includes a bridge die having a routing structure to interconnect multiple integrated circuit (IC) dies of the package. Power is provided to the IC dies by a mesh power supply metallization and a mesh ground metallization that extend from outside a perimeter of the bridge die to within the perimeter and over the routing structure. The bridge die may be absent through silicon vias (TSVs) and may be hanging such that it is exposed at the bottom of the package.

An apparatus comprises a push-pull regulation loop (PPRL), an input terminal, an output terminal, and a plurality of flying capacitor (FC) circuits. The plurality of FC circuits comprises a corresponding plurality of capacitors. The PPRL comprises a PMOS transistor, an NMOS transistor, and a control circuit. The input terminal and the output terminal are coupled to a node of the PPRL via a rail. FC circuits of the plurality of FC circuits are coupled to each other. At least a first FC circuit of the plurality of FC circuits is coupled to the rail. A remaining subset of the plurality of FC circuits is coupled to the first FC circuit. An FC circuit of the plurality of FC circuits further comprises at least a first transistor switch and a second transistor switch coupled to a corresponding capacitor of the plurality of capacitors.

Integrated circuit structures having uniform grid metal gate and trench contact placeholder cut and non-selective fin trim isolation (FTI) are described. For example, an integrated circuit structure includes a vertical stack of horizontal nanowires or a fin. A gate structure is over the vertical stack of horizontal nanowires or the fin. A dielectric structure is laterally spaced apart from the gate structure. The dielectric structure is not over a channel structure. A dielectric gate cut plug is laterally between and in contact with the gate structure and the dielectric structure. The dielectric structure has an uppermost surface above an uppermost surface of the dielectric gate cut plug.

Embodiments herein relate to a voltage converter which can mitigate a voltage overshoot in an energy efficient and space-efficient manner. In one aspect, energy from an inductor is diverted away from the output and recycled from the output capacitance to the input of the voltage converter. Different implementations includes an augmented buck-boost converter, a switched-coupled-inductor buck converter, a buck-reverse-flyback hybrid converter, and an inductive shunt and recovery circuit.

Devices and methods for testing interconnect lanes of multichip packages with memory test algorithms are provided. The multichip packages that can be tested can comprise a plurality of semiconductor dies mounted on an active interposer.

An apparatus comprises a first OR gate, a second OR gate, a first NAND gate, and a second NAND gate. The first OR gate comprises a first input terminal, a second input terminal, and an output terminal. The second OR gate comprises a first input terminal, a second input terminal, and an output terminal. The first NAND gate comprises a first input terminal coupled to the output terminal of the first OR gate. The first NAND gate also comprises a second input terminal coupled to the output terminal of the second OR gate. The second NAND gate comprises an output terminal coupled to the first input terminal of the second OR gate.

An apparatus comprises a push-pull regulation loop (PPRL). The PPRL comprises a PMOS transistor, an NMOS transistor, and a first plurality of capacitors. The PPRL also comprises a control circuit coupled to the PMOS transistor, the NMOS transistor, and the first plurality of capacitors. The control circuit comprises a reference terminal and is to receive a randomized voltage reference signal via the reference terminal. The control circuit further adjusts a reset voltage available at the first plurality of capacitors based on the randomized voltage reference signal.

An apparatus and method for predicting I/O device interrupt frequency. For example, one embodiment of a method comprises: storing metrics related to interrupts associated with an input-output (IO) device coupled to compute circuitry; evaluating the metrics to identify periodic interrupts; generating a time for a predicted next interrupt for each periodic interrupt; and initiate waking the compute circuitry from a low power state prior to the time for the predicted next interrupt to allow the compute circuitry to be in an active state when the predicted next interrupt is received.

Integrated circuit (IC) devices having gate-all-around (GAA) transistors. An IC device may include adjacent GAA transistors with gate electrodes having different gate dielectric stacks separated by a dielectric wall. The gate dielectric stacks may include inner gate dielectric layers on nanoribbon channels and outer gate dielectric layers on the inner gate dielectric layers. The inner gate dielectric layers of the adjacent transistors may have different thicknesses or material compositions. The outer gate dielectric layers of the adjacent transistors may have different thicknesses or material compositions. The dielectric wall between gate electrodes and gate dielectric stacks may enable independent processing of the transistors gates by dividing the nanoribbon channels into separate gate tubs.

Some embodiments include apparatuses and methods of making the apparatuses. One of the apparatuses includes: a first supply node (V2); a second supply node (140); and a driver (110). The driver includes a first input path (221), a second input path (222), an output node (205), a first N-type transistor (M1), a second N-type transistor (M2), and a resistor (M3). The first N-type transistor (M1) includes a gate coupled to the first input path, a first terminal coupled to the first supply node, and a second terminal coupled to the output node. The second N-type transistor includes a gate coupled to the second input path, a first terminal coupled to the output node, and a second terminal. The resistor is coupled between the second terminal of the second N-type transistor and the second supply node.

Provided is an acoustic scan apparatus that includes a fluid circulation structure to facilitate sufficient acoustic coupling between a transducer and a die surface and at the same time, limits the amount of fluid contacting part of the die not desired to be contacted.

Outdiffusion of germanium from silicon-germanium source and drain regions of PMOS (p-channel metal-oxide-semiconductor) field effect transistors into metal contact layers located on the PMOS source and drain regions can reduce the concentration of germanium layer in the silicon-germanium in the vicinity of the silicon-germanium layer-metal contact layer interface. This region of reduced germanium concentration can increase the parasitic contact resistance, which can have a deleterious effect on PMOS transistor performance. Adding germanium to the metal contact layers can reduce or eliminate germanium outdiffusion and prevent parasitic contact resistance increases.

Provided is a temperature estimation tool for estimating temperatures in an integrated circuit device from functional block objects in the device.

Techniques for region-aware memory bandwidth monitoring are described. In an embodiment, an apparatus includes a processing core to access a memory, the memory to include a plurality of memory regions; a plurality of memory bandwidth telemetry counters; and a plurality of memory bandwidth monitoring (MBM) storage locations, one of the plurality of MBM storage locations corresponding to one of the plurality of memory regions and one of a plurality of resource monitoring identifiers (RMIDs), the one of the plurality of MBM storage locations to store a count from a corresponding memory bandwidth telemetry counter for the one of the plurality of memory regions and the one of the plurality of RMIDs.

Devices, transistor structures, systems, and techniques are described herein related to gate all around field effect transistors having a stack of nanowires (i.e., semiconductor structures) contacted by epitaxial source and drain structures at opposite ends of the nanowires. The transistors include a gate structure vertically between the nanowires. Spacer structures of silicon germanium oxide separate the ends of the nanowires spacer and separate the source and drains structures from the gate structure.

An apparatus, comprising a memory, configured to store a first data set, comprising kinodynamic data representing a plurality of human-directed movements of a robot; and a second data set, comprising linguistic descriptors of the plurality of human-directed movement of the robot; and a processor, configured to generate a third data set based on the first data set and the second data set, wherein the third data set comprises a plurality of motion primitives of the robot.

Embodiments disclosed herein include an apparatus that comprises a first substrate with a first pad on the first substrate, where the first pad is electrically conductive, and a second substrate over the first substrate with a second pad on the second substrate, where the second pad is electrically conductive. In an embodiment, the apparatus further comprises a patch between the first substrate and the second substrate. In an embodiment, the patch comprises a frame with an opening through the frame, and an interconnect within the opening. In an embodiment, the interconnect electrically couples the first pad to the second pad, and the interconnect comprises a liquid metal matrix with filler particles that are electrically conductive.

Examples of an integrated inductor structure including a conductive polymer separation layer as described herein. A conductive polymer layer between the seed layer and the magnetic material in an integrated inductor can act like an isolation layer between the magnetic material and seed layer to improve inductor performance (e.g., by reducing eddy current-induced inductor efficiency degradation). In one example, a microelectronic assembly includes a layer of glass with a first face and a second face, and an inductor in the layer, where the inductor includes a continuous portion of a conductive material between the first face and the second face, a magnetic material at least partially surrounding the conductive material, and a conductive polymer at least partially surrounding the magnetic material.

Techniques for quality of service (QoS) support for input/output devices and other agents are described. In embodiments, a system includes execution circuitry to execute a plurality of software threads; hardware to monitor or control allocating, among the plurality of software threads, one or more shared resources; and storage to store a data structure to configure and enable monitoring or allocating of the one or more shared resources among the plurality of software threads and one or more channels through which one or more devices are to be connected to the one or more shared resources, the data structure to define one or more resource management domains in the system and which one or more devices are included in which one or more resource management domains.

An apparatus comprises a push-pull regulation loop (PPRL), an input terminal, an output terminal, and a plurality of FC circuits. The PPRL comprises a PMOS transistor, an NMOS transistor, and a first plurality of capacitors. The input terminal and the output terminal are coupled to the PPRL via the first plurality of capacitors. The plurality of FC circuits includes a second plurality of capacitors. FC circuits of the plurality of FC circuits are coupled to each other and a rail between the input terminal and the output terminal. An FC circuit of the plurality of FC circuits comprises at least a first transistor switch and a second transistor switch coupled to a corresponding capacitor of the second plurality of capacitors.

Integrated circuit structures having backside conductive source or drain contacts, and methods of fabricating integrated circuit structures having backside conductive source or drain contacts, are described. For example, an integrated circuit structure includes a dielectric structure over a vertical stack of horizontal nanowires or fin. An epitaxial source or drain structure is laterally adjacent to and coupled to the vertical stack of horizontal nanowires or fin. A conductive source or drain contact structure is laterally adjacent to the dielectric structure and is on and in contact with the epitaxial source or drain structure. The conductive source or drain contact structure is laterally surrounded by a dielectric spacer.

Gate-all-around integrated circuit structures having gate dielectrics with differentiated transition layer thickness are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires or fin and a second vertical arrangement of horizontal nanowires or fin. A first gate stack is over the first vertical arrangement of horizontal nanowires or fin, where the first gate stack is an NMOS gate stack having a gate electrode over a gate dielectric, the gate dielectric having a transition layer comprising silicon and oxygen and having a first thickness. A second gate stack is over the second vertical arrangement of horizontal nanowires or fin, where the second gate stack is a PMOS gate stack having a gate electrode over a gate dielectric, the gate dielectric having a transition layer comprising silicon and oxygen and having a second thickness greater than the first thickness.

Gate-all-around integrated circuit structures having three-dimensional (3D) conductive contact structures are described. For example, an integrated circuit structure includes a first vertical stack of horizontal nanowires over a second vertical stack of horizontal nanowires. A first epitaxial source or drain structure is at an end of the first vertical stack of horizontal nanowires. A second epitaxial source or drain structure is at an end of the second vertical stack of horizontal nanowires. The second epitaxial source or drain structure is vertically beneath the first epitaxial source or drain structure. A conductive contact structure is through the first epitaxial source or drain structure and extending only partially into the second epitaxial source or drain structure.

Disclosed herein are devices, methods, and systems for dynamically updating a robot's system modeling parameters while the robot is working to complete a task. The dynamic modeling system receives a set of performance parameters (e.g., for optimization objectives) associated with a task of a robot, wherein the set of performance parameters comprise a first weight associated with an extent of compliance toward completing the task and a second weight associated with a modeling metric in system modeling parameters of the robot. The dynamic modeling system determines control parameters for moving the robot, wherein the control parameters are based on the extent of compliance in relation to the first weight and based on the modeling metric in relation to the second weight. The dynamic modeling system controls a motion of the robot according to the control parameters.

In one embodiment, a substrate includes a glass core layer with conductive through glass vias (TGVs). The substrate also includes a polymer layer between the glass core layer and the TGVs.

A system, including: processor circuitry; a robotic gripper; and a non-transitory computer-readable storage medium including instructions that, when executed by the processing circuitry, cause the processor circuitry to: receive image data of an object captured by a camera; analyze a visual feature of the object based on the received image data; generate illumination patterns based on the analyzed visual feature; and control arrays of light sources integrated into a plurality of fingers of a robotic gripper to project the illumination patterns within a grasp volume defined by the plurality of fingers during object manipulation to enhance detection of the visual feature of the object, wherein each light source in the arrays of light sources is individually controllable by the processor.

A legacy virtual machine (a virtual machine not operating in a secure environment) can be converted to a confidential virtual machine (a virtual that operates in a secure environment) on the fly, with little downtime experienced by the legacy virtual machine (VM) owner. A legacy VM operating either on a legacy platform (a platform not having confidential computing capabilities) or a confidential computing-capable platform can be converted to a confidential VM (CVM). The legacy VM can be migrated to another computing device as part of the conversion or be converted into a CVM that executes on the same computing device on which the legacy VM was running. A trusted security module can be responsible for starting a VM-to-CVM conversion session, validating the state of legacy virtual machine to be converted, provision a CVM with the state of the legacy virtual machine, and end a VM-to-CVM conversion session.

Techniques related to distributing the video encoding processing of an input video across hardware and software systems. Such techniques include evaluating the content of the video and determine whether or the encoding operation is best to be done on the hardware system only, software system only or a hybrid hardware and software system.

Package substrates with components included in cavities of glass cores are disclosed. An example apparatus includes: a glass layer having a first hole and a second hole, the second hole larger than an electronic component disposed therein, a width of the electronic component larger than a width of the first hole. The example apparatus further includes a conductive material that substantially fills the first hole; and a dielectric material that substantially fills a space within the second hole surrounding the electronic component.

Device stacking in integrated circuit layers using high accuracy bonding is described. In an example, an integrated circuit structure includes a first device layer above a first interconnect structure, the first device layer including nanowire-based transistors or fin-based transistors. The integrated circuit structure includes a second device layer below a second interconnect structure, the second device layer including nanowire-based transistors or fin-based transistors, and the second interconnect structure bonded directly to the first interconnect structure.

A device has a first diplexer with a first port and a second port, configured to pass a first signal and a second signal, and a third port, configured to pass a first combined signal including the first signal and the second signal. The device has a second diplexer with a fourth port, configured to pass a third signal; a fifth port, configured to pass a fourth signal; and a sixth port, configured to pass a second combined signal including the third signal and the fourth signal. A dual-feed antenna has a first antenna interface, connected to the third port, and a second antenna interface, connected to the sixth port; and concurrently transmits or receives the first combined signal and the second combined signal. One of the first signal or the second signal, and one of the third signal or the fourth signal are in a common frequency band.

A kernel on a neural processing unit may perform matrix multiplications (MatMuls) on tensors of various dimensions. A neural network may be trained through a forward operation and backward operation, both of which may be offloaded to the kernel. For the forward operation, the kernel may execute a layer by performing a MatMul on an input tensor and weight tensor and produce an output tensor. A loss may be computed. For the backward operation, the kernel may compute a weight gradient of the loss by performing a MatMul on the input tensor and a gradient of the output tensor and compute an input gradient of the loss by performing a MatMul on the gradient of the output tensor and the weight tensor. The gradient of the output tensor may be computed using an automatic differentiation module. The weight tensor may be updated based on the input gradient and weight gradient.

A test system performs ESD (electrostatic discharge) verification of a circuit definition. The system performs a bottom-up ESD analysis to generate a verified IO (input/output) instance, and then performs a top-down ESD analysis based on multiple instances of the verified IO instance. The system generates an ESD verification model 10 instance with ESD protection circuitry and the ESD victim circuitry as separate cells at the same level of verification hierarchy, and verifies the model IO instance at a worst case connection test case. The system then scales out the IO instance into an array of instances to verify ESD protection between the model IO instances.

Disclosed examples include video frame segmenter circuitry to generate segmentation data of first video frame pixel data, the segmentation data including metadata corresponding to a foreground region and a background region, the foreground region corresponding to the first video frame pixel data. The disclosed examples also include video encoder circuitry to generate a first foreground bounding region and a first background bounding region based on the segmentation data, determine a first virtual tile of the first video frame pixel data, the first virtual tile located in the first foreground bounding region, encode the first virtual tile into a video data bitstream without encoding the first background bounding region, and transmit the video data bitstream via a network.

A circuitry may include: a first digital-to-time converter, DTC, configured to generate a first output signal by sampling a phase modulation command signal; a second DTC configured to generate a second output signal based on the phase modulation command signal with a programmable delay relative to the first output signal; and a phase inverter configured to invert a phase of one of the first output signal or the second output signal.

An apparatus is described, where the apparatus may include: an interface configured to communicate with a first further communication device attachable to a communication device and a second further communication device external to the communication device and the first further communication device; and a processor configured to: determine a result representing whether the first further communication device is in an idle mode; instruct, based on the result, the first further communication device to perform channel measurements; obtain channel measurement results of the first further communication device from the interface; and configure the interface with a configuration that is based on the channel measurement results of the first further communication device to communicate with the second further communication device.

Described herein are nanoribbon transistors with lined cavity spacers deposited near the ends of the nanoribbons, including between the ends of adjacent nanoribbons. The cavity spacers include a liner layer next to the gate stack, and a fill material nested within the liner layer and adjacent to the source or drain. The liner layer is a non-oxide dielectric. For example, the liner may be a low-k nitride. The liner layer may be conformally deposited, and a portion of the liner layer may extend between the gate stack and the source or drain. Using a non-oxide material prevents removal of the liner during an oxide clean step prior to nanoribbon release.

An apparatus may include: a common input terminal; a first inductor and a second inductor, each coupled to the common input terminal, wherein the first inductor and the second inductor are disposed in an electromagnetic coupling configuration; a lower frequency band output terminal coupled to the first inductor; a higher frequency band output terminal coupled to the second inductor; wherein the first inductor and the second inductor are to separate signals received from the common input terminal into the lower and the higher frequency band output terminals based on frequencies of the received signals. An apparatus may include: a first transformer magnetically couple a signal within a first frequency band and generate a first magnetic field with a first orientation; and a second transformer configured to magnetically couple a signal within a second frequency band that is different from the first frequency band.