Intel Patente

Techniques are provided herein to form an integrated circuit having backside conductive contacts (238/240) as part of a gate tie-down structure. Backside cavities beneath a gate structure and an adjacent source region (106b) may be formed using backside lithography and anisotropic etching. The backside cavities are subsequently filled with a conductive material to form the backside contacts. A semiconductor device includes a gate structure around (108) or otherwise on a semiconductor region (104) that extends from a first source region to a second source or drain region. The substrate beneath the semiconductor device is removed and replaced with a backside dielectric material (130). Lithographic operations may be performed on the backside dielectric material along with one or more anisotropic etches to form a first cavity beneath the gate structure and a second cavity beneath the first source region. The backside conductive contacts are then formed within the backside cavities.

Techniques for tag checking for dynamically repeating memory accesses are described. In an embodiment, an apparatus includes instruction decoder circuitry to decode a single instruction, the single instruction having a format including an opcode field, the single instruction having a first opcode value in the opcode field; and execution circuitry coupled to the instruction decoder circuitry, the execution circuitry to perform operations in response to decoding of the single instruction, the operations including performing repeating memory tag checking operations in connection with repeating memory access operations.

An apparatus and method including: graphics processing cores to execute a mesh shader to process a triangle list associated with a mesh and generate a corresponding tristrip; clipper circuitry to clip the tristrip to a view volume, the clipper circuitry to: read corresponding header data including render target array index (RTAI) and view port index (VPI) values corresponding to a current vertex of the tristrip; perform a vertex cache lookup to determine corresponding RTAI and VPI values associated with a previously processed vertex, if any; read vertex data corresponding to the current vertex from memory and processing with new VPI and RTAI values when the RTAI and VPI values of the current vertex do not match those of a previously processed vertex; and perform clip operations based on previously processed vertex data when the RTAI and VPI values of the current vertex match those of the previously processed vertex.

An example processor includes vector registers to store sub-matrices of two source matrices and execution circuitry to perform a cross-product matrix multiplication. A decoder interprets an instruction specifying the source matrices and the operation. The execution circuitry multiplies each combination of sub-matrices from the two source matrices-first with first, first with second, second with first, and second with second-to generate four corresponding sub-matrices of a result matrix, which are stored in a third vector register. This architecture enables efficient parallel matrix computations for high-performance processing tasks.

An example processor executes an instruction having an operand field to indicate a multi-register cross-product matrix multiplication to be performed with the first plurality of sub-matrices and the second plurality of sub-matrices to generate the third plurality of sub-matrices. Execution circuitry execute the instruction, the execution circuitry to generate each sub-matrix of the third plurality of sub-matrices in a corresponding vector register of the third plurality of vector registers by multiplying a sub-matrix in a corresponding vector register of the first plurality of vector registers and a sub-matrix in a corresponding vector register of the second plurality of vector registers.

A processor or other apparatus of an aspect includes a cache to store cache lines and a circuitry coupled with the cache. The circuitry is to receive a memory access request for data at a memory address from a first security domain. The data at the memory address is to be shared by a plurality of security domains including the first security domain. A side-channel protection is to be used for the data. The circuitry is to implement the side-channel protection for the data. This includes not providing a cache line corresponding to the memory address from the cache to the first security domain, when the cache line exists in the cache and is valid, if the first security domain has not previously accessed the cache line in the cache. Other processors, methods, systems, and instructions are disclosed.

Techniques are provided herein to form semiconductor dies (or integrated circuits) with a thermally conductive layer adjacent to a bond interface to enhance the thermal dissipation from the semiconductor devices. A semiconductor die or integrated circuit includes any number of semiconductor devices within a device layer. A frontside interconnect region is provided above the device layer to, for example, route signals between the various semiconductor devices in the device layer. A thermally conductive layer may be provided above the frontside interconnect region, such as on a top-most layer of the frontside interconnect region. The thermally conductive layer includes a material having a thermal conductivity of, for example, at least 1.5 W/m·K. A bond layer may be provided adjacent (e.g., directly above or directly below) the thermally conductive layer and may be any suitable dielectric material, such as silicon dioxide.

Systems and methods for providing a temporal noise reducer (TNR) architecture that improves TNR performance by adjusting for lighting differences between image frames. Temporal noise reduction is a core feature of a video processing pipeline, where TNR can be used to decrease noise in video streams. Some TNRs compensate for the motion of objects between frames, but lighting changes can also lead to additional noise. As an object's position moves from frame to frame, the lighting of the object may change. A lightweight tone-mapping and color-correction operator is added to the TNR feedback loop, matching the radiometric properties of a TNR reference frame to the radiometric properties of the current frame to compensate for radiometric differences, thereby increasing the effectiveness of TNR in handling incremental lighting changes and speeding up its response to abrupt lighting changes.

An apparatus and method for progress tracking strided vector loads and stores. For example, an example method comprises: decoding a progress tracking strided load instruction including fields to indicate a destination vector register in which to load source data elements, memory locations of the source data elements, and a register to store a progress indication; initiating execution of the progress tracking strided load instruction; loading one or more of the source data elements to corresponding locations in the destination vector register; updating the progress indication in accordance with the one or more source data elements loaded or a next source data element to be loaded; and in response to an interruption of the execution of the progress tracking strided load instruction, re-starting the execution of the instruction from an execution point based on the progress indication.

Systems, apparatus, articles of manufacture, and methods to compensate for impedance and reduce crosstalk in integrated circuit packages are disclosed. An example apparatus includes a metal interconnect within a substrate of an integrated circuit package. The metal interconnect includes a contact pad in a first metal layer of the substrate and a via pad in a second metal layer of the substrate. The metal interconnect defines a conductive path for an electric signal that is to pass through both the contact pad and the via pad. The example apparatus further includes a conductive material having a length defining a segment of the conductive path between the contact pad and the via pad. At least a portion of the length of the conductive material extends along a course that corresponds and is adjacent to a portion of a perimeter of the contact pad.

Systems and methods for determining a texture map for a high resolution image based on a downscaled low resolution version of the image. A texture map is used in image signal processing and image restoration systems to provide a location-specific indication of whether a particular area of an image includes high texture, low texture, edges, or flat regions. Using a low resolution version of the image, semantic cues are integrated with texture information to enable efficient, accurate, and cost-effective texture predictions and generate a texture classification map. The texture classification map based on the low resolution image is upscaled to a high resolution texture classification map. The texture classification map information can then be used to determine a selected filter to apply to each pixel and/or area in the high resolution image. The system provides spatially consistent decisions and improved noise robustness in texture to facilitate accurate image restoration.

Disclosed herein are IC structures with nanoribbon transistors and backside capacitors, and related methods and devices. In one aspect, an IC structure includes a nanoribbon including a semiconductor material and a transistor including a channel portion and first and second source/drain (S/D) regions, wherein the channel portion includes a portion of the semiconductor material of the nanoribbon and has a front side and a back side, and the first and second S/D regions are at the opposite ends of the channel portion. The IC structure further includes a contact structure in conductive contact with the first S/D region and a capacitor in conductive contact with the second S/D region, wherein the contact structure is at the front side of the channel portion and the capacitor is at the back side of the channel portion.

Systems, apparatus, articles of manufacture, and methods to enable attachment of surface mounting technology (SMT) components of different sizes to an underlying substrate are disclosed. An example apparatus includes a circuit board; a first pad on the circuit board, the first pad to be electrically coupled to a first terminal of a surface mounting technology (SMT) component, the first pad having a first edge and a second edge opposite the first edge, the first edge shorter than the second edge; and a second pad on the circuit board, the second pad to be electrically coupled to a second terminal of the SMT component, the second pad having a third edge and a fourth edge opposite the third edge, the third edge shorter than the fourth edge.

This disclosure describes systems, methods, and devices related to optimized buffer reporting. A device may transmit a request frame to an access point to enable a dynamic buffer status reporting mode. The device may initiate frame exchanges with the access point using a buffer status report trigger frame. The device may cause to send a multi-station block acknowledgment frame containing buffer status information.

In some embodiments, pick and place tools can pick and place multiple dies with different die sizes from different source wafers at a time to increase the throughput. In addition, some of these tools may incorporate non-contact die handling during pick and place processes. In some examples, the non-contact mechanisms can use Bernoulli effects or acoustic wave or vibration techniques to hold and release dies.

This disclosure describes systems, methods, and devices related to optimized feedback integration. A device may receive a buffer status report protocol (BSRP) trigger frame. The device may transmit a response in a non-high throughput (non-HT) duplicate physical protocol data unit (PPDU) format, the response including a multi-station block acknowledgment frame. The device may include unavailability information in a multi-station block acknowledgment frame.

Systems, apparatus, articles of manufacture, and methods are disclosed. An example memory module includes: a memory die a first pseudo-split die having first interface circuitry; and a second pseudo-split die having second interface circuitry; and a multiplexer external to the memory die, the multiplexer having a first port connected to the first interface circuitry, a second port connected to the second interface circuitry, and a third port connected to memory controller circuitry.

Embodiments disclosed herein may include an apparatus with a substrate. In an embodiment, an opening is formed through the substrate. In an embodiment, a layer is provided over a sidewall of the opening, and the layer comprises a first magnetic material, and a plug is in the opening. In an embodiment, the plug comprises a second magnetic material that is different than the first magnetic material. In an embodiment, a first via is through the plug, and a second via may be formed through the plug.

Techniques are provided herein to form semiconductor dies with a thermally conductive bond interface to enhance the thermal dissipation from the semiconductor devices. A frontside interconnect region is provided above a semiconductor device layer to, for example, route signals between various semiconductor devices in the device layer. A thermally conductive bond layer may be provided above the frontside interconnect region, such as on a top-most layer of the frontside interconnect region. The thermally conductive bond layer includes a metal such as titanium, ruthenium, copper, or generally any material having a thermal conductivity of at least 1.5 W/m·K. The bond layer may be formed on a material layer that is deposited first on the frontside interconnect region. The material layer may be any of diamond, silicon carbide, copper, or aluminum nitride, to name a few examples.

Camera tuning process is a time consuming and labor-intensive process. To address this issue, camera tuning system including a multi-modal large language model and a retrieval-augmented generation system can be implemented to intelligently and efficiently handle a camera tuning task in real-time. The multi-modal large language model can evaluate image quality and can be finetuned using high-quality labeled data and synthetically generated labeled data. The retrieval-augmented generation system can incorporate camera configuration knowledge into a vector database and can leverage a retrieved context to generate a configuration solution that addresses image quality issues identified by the multi-modal large language model. The resulting camera tuning system is a unified process that can identify image quality issues and provide configuration solutions that address both technical and aesthetic image quality concerns.

A cold plate comprises a plurality of fins. The individual fins have an opening, and the openings collectively define a first channel through the plurality of fins. During operation of an integrated circuit component attached to the cold plate, coolant is pumped through the cold plate. The coolant flows in a first direction through the first channel and then in a second through second channels located between the fins. The first direction is substantially orthogonal to the second direction. The first channel can comprise a tube that has openings that direct coolant to flow into the second channels. The first channel is located close to the base plate of the cold plate so that there is a high degree of heat transfer between an integrated circuit component attached to the cold plate and coolant flowing through the cold plate.

Bridge die interposer packages, and related apparatuses, systems, and techniques are discussed. An interposer package includes a bridge die having a routing structure to interconnect multiple integrated circuit (IC) dies of the package. Power is provided to the IC dies by a mesh power supply metallization and a mesh ground metallization that extend from outside a perimeter of the bridge die to within the perimeter and over the routing structure. The bridge die may be absent through silicon vias (TSVs) and may be hanging such that it is exposed at the bottom of the package.

Integrated circuit (IC) devices having gate-all-around (GAA) transistors. An IC device may include adjacent GAA transistors with gate electrodes having different gate dielectric stacks separated by a dielectric wall. The gate dielectric stacks may include inner gate dielectric layers on nanoribbon channels and outer gate dielectric layers on the inner gate dielectric layers. The inner gate dielectric layers of the adjacent transistors may have different thicknesses or material compositions. The outer gate dielectric layers of the adjacent transistors may have different thicknesses or material compositions. The dielectric wall between gate electrodes and gate dielectric stacks may enable independent processing of the transistors gates by dividing the nanoribbon channels into separate gate tubs.

A legacy virtual machine (a virtual machine not operating in a secure environment) can be converted to a confidential virtual machine (a virtual that operates in a secure environment) on the fly, with little downtime experienced by the legacy virtual machine (VM) owner. A legacy VM operating either on a legacy platform (a platform not having confidential computing capabilities) or a confidential computing-capable platform can be converted to a confidential VM (CVM). The legacy VM can be migrated to another computing device as part of the conversion or be converted into a CVM that executes on the same computing device on which the legacy VM was running. A trusted security module can be responsible for starting a VM-to-CVM conversion session, validating the state of legacy virtual machine to be converted, provision a CVM with the state of the legacy virtual machine, and end a VM-to-CVM conversion session.

A system, including: processor circuitry; a robotic gripper; and a non-transitory computer-readable storage medium including instructions that, when executed by the processing circuitry, cause the processor circuitry to: receive image data of an object captured by a camera; analyze a visual feature of the object based on the received image data; generate illumination patterns based on the analyzed visual feature; and control arrays of light sources integrated into a plurality of fingers of a robotic gripper to project the illumination patterns within a grasp volume defined by the plurality of fingers during object manipulation to enhance detection of the visual feature of the object, wherein each light source in the arrays of light sources is individually controllable by the processor.

In one embodiment, a substrate includes a glass core layer with conductive through glass vias (TGVs). The substrate also includes a polymer layer between the glass core layer and the TGVs.

Disclosed herein are devices, methods, and systems for dynamically updating a robot's system modeling parameters while the robot is working to complete a task. The dynamic modeling system receives a set of performance parameters (e.g., for optimization objectives) associated with a task of a robot, wherein the set of performance parameters comprise a first weight associated with an extent of compliance toward completing the task and a second weight associated with a modeling metric in system modeling parameters of the robot. The dynamic modeling system determines control parameters for moving the robot, wherein the control parameters are based on the extent of compliance in relation to the first weight and based on the modeling metric in relation to the second weight. The dynamic modeling system controls a motion of the robot according to the control parameters.

Gate-all-around integrated circuit structures having three-dimensional (3D) conductive contact structures are described. For example, an integrated circuit structure includes a first vertical stack of horizontal nanowires over a second vertical stack of horizontal nanowires. A first epitaxial source or drain structure is at an end of the first vertical stack of horizontal nanowires. A second epitaxial source or drain structure is at an end of the second vertical stack of horizontal nanowires. The second epitaxial source or drain structure is vertically beneath the first epitaxial source or drain structure. A conductive contact structure is through the first epitaxial source or drain structure and extending only partially into the second epitaxial source or drain structure.

Gate-all-around integrated circuit structures having gate dielectrics with differentiated transition layer thickness are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires or fin and a second vertical arrangement of horizontal nanowires or fin. A first gate stack is over the first vertical arrangement of horizontal nanowires or fin, where the first gate stack is an NMOS gate stack having a gate electrode over a gate dielectric, the gate dielectric having a transition layer comprising silicon and oxygen and having a first thickness. A second gate stack is over the second vertical arrangement of horizontal nanowires or fin, where the second gate stack is a PMOS gate stack having a gate electrode over a gate dielectric, the gate dielectric having a transition layer comprising silicon and oxygen and having a second thickness greater than the first thickness.

An apparatus comprises a push-pull regulation loop (PPRL), an input terminal, an output terminal, and a plurality of FC circuits. The PPRL comprises a PMOS transistor, an NMOS transistor, and a first plurality of capacitors. The input terminal and the output terminal are coupled to the PPRL via the first plurality of capacitors. The plurality of FC circuits includes a second plurality of capacitors. FC circuits of the plurality of FC circuits are coupled to each other and a rail between the input terminal and the output terminal. An FC circuit of the plurality of FC circuits comprises at least a first transistor switch and a second transistor switch coupled to a corresponding capacitor of the second plurality of capacitors.

Techniques for quality of service (QoS) support for input/output devices and other agents are described. In embodiments, a system includes execution circuitry to execute a plurality of software threads; hardware to monitor or control allocating, among the plurality of software threads, one or more shared resources; and storage to store a data structure to configure and enable monitoring or allocating of the one or more shared resources among the plurality of software threads and one or more channels through which one or more devices are to be connected to the one or more shared resources, the data structure to define one or more resource management domains in the system and which one or more devices are included in which one or more resource management domains.

Examples of an integrated inductor structure including a conductive polymer separation layer as described herein. A conductive polymer layer between the seed layer and the magnetic material in an integrated inductor can act like an isolation layer between the magnetic material and seed layer to improve inductor performance (e.g., by reducing eddy current-induced inductor efficiency degradation). In one example, a microelectronic assembly includes a layer of glass with a first face and a second face, and an inductor in the layer, where the inductor includes a continuous portion of a conductive material between the first face and the second face, a magnetic material at least partially surrounding the conductive material, and a conductive polymer at least partially surrounding the magnetic material.

Embodiments disclosed herein include an apparatus that comprises a first substrate with a first pad on the first substrate, where the first pad is electrically conductive, and a second substrate over the first substrate with a second pad on the second substrate, where the second pad is electrically conductive. In an embodiment, the apparatus further comprises a patch between the first substrate and the second substrate. In an embodiment, the patch comprises a frame with an opening through the frame, and an interconnect within the opening. In an embodiment, the interconnect electrically couples the first pad to the second pad, and the interconnect comprises a liquid metal matrix with filler particles that are electrically conductive.

An apparatus, comprising a memory, configured to store a first data set, comprising kinodynamic data representing a plurality of human-directed movements of a robot; and a second data set, comprising linguistic descriptors of the plurality of human-directed movement of the robot; and a processor, configured to generate a third data set based on the first data set and the second data set, wherein the third data set comprises a plurality of motion primitives of the robot.

Devices, transistor structures, systems, and techniques are described herein related to gate all around field effect transistors having a stack of nanowires (i.e., semiconductor structures) contacted by epitaxial source and drain structures at opposite ends of the nanowires. The transistors include a gate structure vertically between the nanowires. Spacer structures of silicon germanium oxide separate the ends of the nanowires spacer and separate the source and drains structures from the gate structure.

Techniques for region-aware memory bandwidth monitoring are described. In an embodiment, an apparatus includes a processing core to access a memory, the memory to include a plurality of memory regions; a plurality of memory bandwidth telemetry counters; and a plurality of memory bandwidth monitoring (MBM) storage locations, one of the plurality of MBM storage locations corresponding to one of the plurality of memory regions and one of a plurality of resource monitoring identifiers (RMIDs), the one of the plurality of MBM storage locations to store a count from a corresponding memory bandwidth telemetry counter for the one of the plurality of memory regions and the one of the plurality of RMIDs.

An apparatus includes a first multiplier circuit, a second multiplier circuit, a first adder circuit, and a second adder circuit. The first multiplier circuit receives a sensed voltage signal and generates a first weighted sensed voltage signal based on the sensed voltage signal. The second multiplier circuit receives a first buffered sensed voltage signal and generates a second weighted sensed voltage signal based on the first buffered sensed voltage signal. The first adder circuit generates a combined sensed voltage signal based on the first weighted sensed voltage signal and the second weighted sensed voltage signal. The second adder circuit generates a duty ratio signal based on a first weighted duty ratio signal and the combined sensed voltage signal.

A method of an aspect includes predicting a value that a load instruction of a first iteration of a loop would load and executing a plurality of instructions occurring after the load instruction in the first iteration of the loop to generate a plurality of results. Each of the plurality of results depends only on the value, one or more constant values, values derived from the value and/or the one or more constant values, or any combination thereof. The method also includes producing the plurality of results for the plurality of instructions during each of one or more iterations of the loop after the first iteration without re-executing the plurality of instructions. Other methods, apparatus, and systems are also disclosed.

Gate-all-around integrated circuit structures having a heterogeneous or mixed cFET architecture are described. For example, an integrated circuit structure includes a first vertical stack of horizontal nanowires over a second vertical stack of horizontal nanowires, the first vertical stack of horizontal nanowires including (110) silicon nanowires, and the second vertical stack of horizontal nanowires including (100) silicon nanowires, or the first vertical stack of horizontal nanowires including (100) silicon nanowires, and the second vertical stack of horizontal nanowires including (110) silicon nanowires. First epitaxial source or drain structures are at ends of the first vertical stack of horizontal nanowires. Second epitaxial source or drain structures are at ends of the second vertical stack of horizontal nanowires, the second epitaxial source or drain structures vertically beneath and having a different composition than the first epitaxial source or drain structures.

Semiconductor devices and systems with a protective diode cap, and methods of forming the same, are disclosed herein. In one example, a semiconductor device includes a fin, p-type and n-type epitaxial structures over the fin, and a dielectric liner under the fin, where the dielectric layer does not include oxygen.