Murata Manufacturing

The disclosure relates to microelectromechanical system comprising an ASIC layer, a handle layer, a device layer and a cap layer vertically attached to each other in a given order. The device layer is electrically connected to the ASIC layer through the handle layer.

The disclosure relates to microelectromechanical (MEMS) devices. The MEMS device comprises an ASIC layer, a MEMS device layer and a cap layer and bonding layers therebetween form an enclosure for movable MEMS elements. The MEMS device layer and the cap layer comprise at least one ASIC signal through-silicon-via that electrically connects signals of an ASIC active circuitry the respective metal pad on the outer face of the cap layer.

The disclosure relates to a microelectromechanical (MEMS) device and to a method of manufacturing a MEMS device. The MEMS device comprises a a cap layer, two MEMS device layers and an ASIC layer, while the cap layer and the ASIC layer enclose functional elements of the two MEMS device layers in an enclosure. Digital signals, ground and operating voltage of ASIC circuitry are coupled with outside of the MEMS device through one or more ASIC signal through-silicon-vias traveling through the two MEMS device layers and the cap layer.

The disclosure relates to a microelectromechanical system comprising an ASIC layer, an interposer layer, a MEMS layer with movable structures and a cap layer stacked with each other in a listed order. The interposer layer and the cap layer form one isolated enclosure, and the ASIC layer and the cap layer form another isolated enclosure, wherein pressures in the isolated enclosures are different. An advantage of the arrangement of the disclosure is that it allows to set different pressures in the isolated enclosures reliably without extra process steps.

A microelectromechanical device comprises a MEMS device layer a handle layer and a cap layer. The device also comprises an interposer layer between the handle layer and the MEMS device layer. The interposer layer comprises an insulating layer on the surface of the handle layer and a polysilicon layer on the insulating layer. The device layer comprises a mobile mass element. The polysilicon layer lies beneath the mass element and is electrically connected to a first external contact in the cap layer through the device layer.

The disclosure relates to a aspects of a method for manufacturing electronic and/or microelectromechanical system, MEMS, devices using a lid frame that carries a plurality of such devices. Use of the lid frame enables performing manufacturing steps as well as testing and/or calibration of devices packaged into individually produced housings with manufacturing, testing and calibration equipment that is designed to handle lead frames.

An electrical device comprising,- a substrate region (100),- a first electrode formed in a first doped diamond layer (101), on the substrate region (100),- a dielectric layer (102, 105, 106, 108, 110, 104, 107) on the first doped diamond layer (101) comprising two adjacent regions, a first region called intermediate layer (102, 105, 106, 108, 110) formed in a dielectric diamond material layer and a second region (104, 107) formed in a dielectric material,- a second electrode formed in a conductor material layer (103, 113, 123, 133), located on the dielectric layer,wherein- said first region in the dielectric diamond material having a first constant thickness- the second region comprises a dielectric material and has an increasing thickness from said first constant thickness on the intermediate layer (102, 105, 106, 108, 110) side to a second thickness on its other side opposite to the intermediate layer, said increase of thickness having a curved shape,- the second electrode (103, 113, 123, 133) comprises a first region (103a) having a first constant thickness above the intermediate layer (102, 105, 106, 108, 110) and a termination region (103b, 113b) extending the first region in a curved shape above the dielectric material.

The invention concerns a wafer comprising: - a metal layer deposited on a substrate, said metal layer comprising at least: • a first region made of said metal; and • a porous region comprising a plurality of substantially straight pores that extend from a top surface of the first porous region towards the substrate, the porous region being thicker than the first region; - at least one integrated device formed inside the pores of the porous region; the wafer further comprising: - a test arrangement comprising: • an insulating layer deposited on both the first region and the porous region, • a first contact pad and a second contact pad deposited on the insulating layer above the porous region; and a third contact pad deposited on the insulating layer above the first region.

An integrated electrical device comprising an energy storage component, comprising:a support comprising a porous region (103) including a plurality of substantially straight pores (POR) that extend from a top surface of the porous region towards the bottom of the porous region,an insulating layer (104) having an opening (OP) delimiting a portion of the porous region,a bottom electrode layer (105),an intermediate region (106, 1061, 106T, 106T) comprising a dielectric or an ionic conductor, the intermediate region having an inner portion (1061) arranged on an inner portion of the bottom electrode layer and a top portion (106T, 106T') arranged on a top portion of the bottom electrode layer, the inner portion of the intermediate region having a first thickness (T1) and the top portion of the intermediate region having a second thickness (T2) greater than the first thickness,a top electrode layer (107) arranged on the intermediate region.

The present invention relates to an electrical device (100) comprising a capacitor for high-voltage applications and method for manufacturing thereof. In particular, the proposed electrical device (100) includes a capacitor comprising:- a bottom electrode (110) comprising a semiconductor substrate (111),- a dielectric (120) extending conformally on the bottom electrode (110),- a top electrode (130) on the dielectric (120),wherein the substrate (111) comprises:- a first region of a first doping type (113) extending from a bottom surface of the substrate (111-BS) up to a top surface of the substrate (111-TS),- second regions of a second doping type (114) having opposite charge carriers in comparison with the first doping type and extending from the top surface of the substrate (111-TS) down to a given depth (111-D).