IHP – Innovations for High Performance Microelectronics Patente

The present invention relates to a method for fabricating an electronic or optoelectronic device (100). The method comprises the steps of:- providing a layer stack comprising along a stacking direction a wafer (105) and one or more dielectric mask layers;- structuring the one or more dielectric mask layers (107) by selectively etching at least one window into the one or more dielectric mask layers; and- selectively growing a nanostructure (102) of the electronic or optoelectronic device in the at least one window by means of epitaxy.

A reflection device for wireless communication comprises a two-dimensional array of reflective elements (109,119) and a control device (111,120) for controlling the multiple reflective elements such that the multiple reflective elements reflect the impinging electromagnetic waves in a phase-controlled fashion into a selectable reflection angle. The reflection device is configured to reflect and transform impinging electromagnetic waves having a first type of waveform, e.g. plane waves, such that the reflected electromagnetic waves have a second type of waveform, e.g. orbital angular momentum (OAM) waves, and vice versa. Instead of using OAM waves as second type of electromagnetic waves, LOS-MIMO can be used as well. Furthermore, a transformation between LOS-MIMO waves to OAM-waves and vice versa, is equally possible.

For generation of a physical-layer secret key for use in wireless communication, a first transceiver and a second transceiver, both with beamforming capability, in a sequence of repetitions covering a plurality of beam pairs from a beamforming codebook defining a set of beam pairs, select a transmit beam angle and a receive beam angle in respective random order unknown to the respective other transceiver, for probe signal exchange and determining respective versions of channel state information. The channel state information versions are used to determine, after quantization and reconciliation, sub-keys associated with the respective beam pairs, which are combined to obtain a composite physical-layer secret key.

A calibration method for operating a CW short-range radar system in obtaining calibrated intermediate frequency in-phase and quadrature outputs comprises measuring at least one reflective static calibration target at a plurality of at least four different target ranges and processing the received CW radar measurement signal by performing a quadrature downconversion of the received CW radar beam intensity and phase to obtain measured intermediate frequency in-phase outputs and intermediate frequency quadrature outputs. These are used to solve a system of equations for calibration parameter values including an amplitude mismatch a phase mismatch between the quadrature signals, and individual DC offsets of the quadrature signals.

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Es wird eine SDTMR-Speicherzelle (100) zum Speichern digitaler Daten mit mindestens drei bistabilen Speicherelementen (FF1,FF2,FF3) vorgeschlagen, die in einer Normalbetriebsart ein digitales Eingangssignal und ein Taktsignal empfangen. Jedes bistabile Speicherelement gibt ein Ausgangssignal an einen Voter (101) ab, der an einem ersten Ausgang der Speicherzelle ein Ausgangssignal gemäß der Majorität der digitalen Eingangssignale erzeugt. Die Speicherzelle hat auf Basis der Triple-Modular-Redundancy (TMR) fehlerkorrigierende Eigenschaften. Die Speicherzelle ist wahlweise in eine Scanbetriebsart umschaltbar, in welcher die bistabilen Speicherelemente zu einem Schieberegister verbunden sind. In der Scanbetriebsart ist es möglich, interne Einzelbitfehler zu detektieren, trotz der fehlerkorrigierenden Eigenschaften, welche die Speicherzelle im Normalbetrieb hat. Weiterhin wird ein Verfahren zur Erzeugung von Testmustern vorgeschlagen, um die SDTMR-Zellen auf interne Bitfehler zu prüfen. Dabei greift das Verfahren sowohl auf die Netzliste einer Schaltung, welche SDTMR-Zellen enthält, als auch auf die Netzliste der verwendeten SDTMR-Zelle zu. Das Testmuster gestattet es, die Schaltung auf interne Bitfehler zu prüfen.

An apparatus and a method for recovering clock and data from a multilevel pulse amplitude modulated signal received as input signal (Din) is suggested. The apparatus (500) comprises a phase detector (101), a low-pass filter (102), a voltage-controlled oscillator (103), and a feedback loop forming a CDR loop (107). The voltage-controlled oscillator outputs a clock signal (CKout) that is provided to the phase detector (101). The phase detector receives an MSB signal from a sampler. The apparatus also comprises an interleave circuit (501) configured to receive the input signal (Din) and to generate two output signals (HR1 ,HR2) having a smaller symbol rate than the input signal. The apparatus further comprises a logical gate (508) configured to receive the output signals from the interleave circuit (501) and to generate an enable signal for the phase detector (101) indicating symmetrical transitions in the input signal. Lastly, the apparatus comprises a converter (502) converting the output signals (HR1,HR2) from the interleave circuit (501) into an MSB and an LSB bit stream.

A lens (100) for terahertz radiation, which can be used in an antenna arrangement (400), comprises a cylindrical lens body made of silicon having a planar front surface and a planar back surface. The lens body has a front body region (30) which forms a silicon metamaterial with a relative permittivity that decreases in a lateral direction with increasing radial distance from a cylinder axis. A back body region (20) is immediately adjacent to the front body region and extends to the back surface. It consists of bulk silicon having a laterally constant relative permittivity. The front body region comprises holes that are distributed on the front surface in rings that are concentric with respect to the cylinder axis. The holes extend from the front surface to respective hole bottoms at an equal bottom level in a depth direction. The hole bottoms interface with the back body region.

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Die Erfindung betrifft Verfahren zur gleichzeitigen Herstellung von Hochgeschwindigkeits (HS-npn)- und Hoch-Volt (HV-npn)-SiGe-Heterobipolartransistoren, mittels nichtselektiver Basisabscheidung, deren Kollektorgebiet seitlich von STI umschlossen ist und die über eine selbstjustierte Basis-Emitter-Anordnung sowie epitaktisch verstärkte Basisanschlussgebiete verfügen. Einige Aspekte der Erfindung umfassen Prozessfolgen, die zu verbesserten Eigenschaften der HV-Transistoren führen. Ein weiterer Gesichtspunkt der Erfindung beinhaltet die Ersetzung einzelner Siliziumdioxid-Schichten durch Isolator-Schichtkombinationen. Unter Ausnutzung der Ätzratenunterschiede unterschiedlicher Oxid-Arten bei nasschemischer Behandlung gelingt es, laterale Abmessungen der Emitter- bzw. Kollektorfenster zu verringern und damit das Hochfrequenzverhalten zu verbessern. Gleichzeitig werden diese Möglichkeiten eingesetzt, um für die elektrischen Eigenschaften günstige Formen der Isolatorseitenwände am Emitter- bzw. Kollektorfenster zu gestalten. Ein anderer Aspekt der Erfindung bezieht sich auf die Strukturierung der Emitter-Poly-Silizium-Schicht mit Hilfe eines darüber liegenden Vierschichtstapels, der es ermöglicht, auch bei variabler Höhe des Emitter-Poly-Siliziums die laterale und vertikale Dicke der Verkapselung des Emitters unabhängig voneinander den Erfordernissen anzupassen und zugleich eine schadensfreie Entfernung der Hilfsschichten sicherzustellen. Eine nächste Ausführung der Erfindung berührt die Einbringung von Dotierstoff in das externe Basisgebiet. Abweichend vom üblichen Vorgehen wird hier zusätzlich eine spezielle Implantation der externen Basisgebiete vor deren epitaktischer Verstärkung vorgenommen. Die Kollektorgebiete der HS und HV Transistoren werden mittels unterschiedliche selektiv implantierte, SIC, Implantationen unabhängig von einander optimiert.

The invention relates to a refractive index sensor device (100) for detecting a presence of an analyte in a sample (130). The refractive index sensor device comprises a sensor layer (102). The sensor layer comprises a number of PIN-diode stripes (140, 142, 144, 146), each of the PIN-diode stripes being formed by a p-type semiconductor stripe (148), an intrinsic semiconductor material stripe (152) and an n-type semiconductor stripe (150), and an insulating material (154).The PIN-diode stripes run parallel to each other within the sensor layer along an in-plane direction that is vertical to a stacking direction (106) of layers of the refractive index sensor device, said PIN-diode stripes being electrically and spatially separated from each other by the insulating material.A nanohole array (104) is arranged on top of the sensor layer along the stacking direction. The nanohole array is formed by a plate-shaped element (116) having a number of feedthroughs (118, 120, 122, 124, 126) extending through said plate-shaped element and running parallel to the stacking direction. The feedthroughs are configured such that impinging light (128) can travel through the feedthroughs to be absorbed in the sensor layer.

The present invention relates to a method for backside thinning of an integrated circuit, herein referred to as IC. The method comprises the steps of:- providing the IC, wherein the IC comprises a Si-containing substrate forming the backside of the IC, a Si-based insulator-containing shallow trench isolation, herein referred to as STI, arranged on the Si-containing substrate and one or more functional IC components arranged within the STI and/or on the STI opposite the Si-containing substrate,- providing a polishing pad,- applying a slurry onto the polishing pad and/or the backside of the IC, the slurry being configured to provide an at least Si-selective removal upon exertion of a mechanical shear force,- bringing the backside of the IC and the polishing pad into contact with each other, and- thinning the IC to a thickness of the Si-containing substrate of 1 µm or less by exerting a mechanical shear force to the IC's backside while maintaining the contact between the IC and the polishing pad up.

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An integrated optoelectronic device (100) comprises a substrate (102) with a silicon layer (104) that comprises one or more electronic components. An interconnect stack (114) is arranged on the substrate (102) and comprising a plurality of metal levels (M1, M2, M3). An optical waveguide, herein FEOL wave-guide (130), on the substrate (102) has an optical FEOL coupling section (130.1). A photonic component (122) is arranged in the interconnect stack (114) at a vertical distance from the substrate (102). An optical waveguide in the interconnect stack (114), herein BEOL waveguide (128), is optically coupled to the photonic component (122) and has an optical BEOL coupling section (128.2). An optical interconnect structure (132) is arranged and configured for optically coupling radiation from the BEOL coupling section (128.2) into the FEOL coupling section (130.1) and vice versa. The optical interconnect structure (132) comprises a vertical stack of optically coupled wave-guide elements (132.1-132.4) made of a first dielectric material, which each are embedded in a second dielectric material and which in a desired wavelength range have an index of refraction of a higher value than the embedding second dielectric material. The optically coupled waveguide elements (132.1-132.4) are arranged and configured for receiving optical radiation in the desired wavelength range from the BEOL coupling section (128.2) or the FEOL coupling section (130.1) by coupling the optical radiation into at least one of the waveguide elements, and for cooperatively forming and sustaining, using the coupled optical radiation, one or more supermodes of optical radiation that vertically extend across the vertical stack of coupled optically coupled waveguide elements (132.1-132.4), and for coupling the one or more supermodes into the FEOL coupling section (130.1) or the BEOL coupling section (128.2), respectively.

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A method of determining a position of at least one transceiver node comprises, anchor node by anchor node, transmitting respective positioning frames suitable for reception by a transceiver node and by the other anchor nodes. The transceiver node receives the positioning frames transmitted by the anchor nodes and ascertains respective times of reception for each. A solver stage determines the coordinates (x s , y s , z s ) of the respective transceiver node and the time t s of transmission of the first positioning frame by an anchor node of first rank in the positioning sequence by numerically solving a non-linear system of at least five equations.

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A device for performing accelerated elliptic curve point multiplication determines for each of the iterations of a main loop operation sequence a respective set of respective dummy clock cycle positions, and controls computational blocks to perform a partial multiplication of zero-operands in dummy clock cycles corresponding to the respective determined dummy clock cycle positions of the set of dummy clock cycle positions for the respective main loop iteration. For any of the sets that has two or more dummy clock cycle positions within the same main loop iteration, each two of the dummy clock cycle positions are separated from each other by at least one clock cycle of performing a partial multiplication of non-zero operands, and at least two of the sets of the dummy clock cycle positions differ from each other.

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A variable gain amplifier for amplifying a differential pair of input voltage signals, comprising a control input for receiving a differential pair of gain control voltage signals, a differential signal input for receiving a differential pair of input voltage signals, a current commuting stage receiving the pair of input voltage signals and the gain control voltage, and comprising a pair of cascode circuits for providing a differential pair of current components of respective current amounts that depend on the respective input voltage signal and on the received gain control voltage, a differential load stage receiving the current components and having respective resistive loads of a respective load resistance amount for generating a differential pair of output voltage signals having respective output voltage amounts that depend on the respective current amounts and on the load resistance amounts and a differential signal output having respective differential signal output nodes for providing the differential pair of output voltage signals, wherein the variable gain amplifier further comprises a common-mode bias servo stage that receives a reference voltage of a reference voltage amount and the differential pair of output voltage signals, and that comprises a pair of closed loop differential amplifiers, each configured to generate a respective DC bias voltage of a DC bias voltage amount depending on a difference between the respective output voltage amount and the reference voltage amount, and each feeding the respective generated DC bias voltage back to the respective differential signal output node.

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The invention relates to a gain-control stage (100) for generating gain-control signals (V_c+, V_c-) for controlling an external variable-gain amplifying unit (101). The gain-control stage comprises a first (102) and a second differential amplifier unit (112) that receive, at a respective input interface (104,114) a reference voltage signal (V_Ref) and a variable gain-control voltage signal (V_GC). The second differential amplifier unit is configured to provide, via a second output interface (120), a control voltage signal (Vi) to a controllable first current source (106) of the first differential amplifier unit (102). The first differential amplifier unit (102) is configured to provide, via a first output interface (110), the first and the second gain-control signal (V_C+, V_C-) in dependence on the variable gain-control voltage signal (V_GC), the reference voltage signal (V_Ref) and a first biasing current (I_B1) that depends on the control voltage signal.