imec Patente

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The disclosure proposes an electro-optical modulator, and a corresponding method of fabricating the electro-optical modulator. The electro-optical modulator comprises: a cladding layer; a first and second waveguide core; a ferroelectric layer; and at least two electrodes configured to generate an electric-field across the ferroelectric layer for modulating an optical wave as it passes through the second waveguide core. The ferroelectric layer comprises a first end in the second section, and extends at least in the second section above the first waveguide core, in the third section above the first and the second waveguide core, and in the fourth section above the second waveguide core, wherein in the third section the second waveguide core extends above the first waveguide core, and wherein the second waveguide core is closer to the ferroelectric layer in the fourth section, than the first waveguide core is to the ferroelectric layer in the second section.

The present invention relates to a method for manufacturing a plurality of electrodes (15) wherein the electrodes (15) comprise noble metal, the method comprising: a. providing a substrate (10) having a dielectric layer (11) in physical contact therewith, wherein the dielectric layer (11) comprises at least a sacrificial part (12), wherein the sacrificial part (12) comprises a top surface (121), b. forming a conductive layer (13) on the dielectric layer (11) and in physical contact with the top surface (121) of the sacrificial part (12), wherein the conductive layer (13) comprises the noble metal, thereafter c. providing a masking layer (14) over the conductive layer (13), thereafter d. patterning the masking layer (14) to expose at least the conductive layer (13) above the sacrificial part (12) thereby defining a plurality of electrodes (15) wherein the smallest distance (d1, d1') between the plurality of electrodes (15) is not larger than 500nm, thereafter e. etching the conductive layer (13) by ion-beam thereby forming the plurality of electrodes (15) comprising the noble metal, thereafter f. etching at least a portion of the sacrificial part (12) by dry etching such that the resistance at the smallest distance (d1, d1') between the plurality of electrodes (15) is at least 1e8 ohm, g. removing the masking layer (14). The present invention also relates to an electrode array (100) obtained by the method described in the present disclosure. The present invention also relates to an electroactive device for bio-material processing comprises the electrode array obtained by the method described in the present disclosure.

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The disclosure relates to a method for forming an interconnection structure, comprising:forming a first dielectric layer pattern over a substrate;covering the first dielectric layer pattern with metal and planarizing the metal to expose an upper surface of the first dielectric layer pattern and form a first metal layer pattern;forming a second dielectric layer pattern over the first dielectric layer pattern and the first metal layer pattern;covering the second dielectric layer pattern with metal and planarizing the metal to expose an upper surface of the second dielectric layer pattern and form a second metal layer pattern;forming a mask pattern of a mask material over the second dielectric layer pattern and the second metal layer pattern; andin an etching process comprising using the mask pattern as an etch mask, transferring: a first, second and third sub-pattern of the mask pattern into a first portion of the first metal layer pattern to form a set of lower metal features, a second sub-pattern of the mask pattern into a first portion of the second metal layer pattern and a second portion of the first metal layer pattern to form a set of stacked metal features, and a third sub-pattern of the mask pattern into a second portion of the second metal layer pattern to form a set of upper metal features.

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A Josephson junction stack is produced including a first superconducting electrode layer (3), a barrier layer (4',5) directly on the first superconducting electrode layer and a second superconducting electrode layer (6) directly on the barrier layer. The superconducting electrode layers (3,6) are formed of a superconducting nitride material, and the barrier layer consists of a stack of an amorphous Si layer (4') and directly on said amorphous Si layer: a passivation layer (5) formed of a mixture of Si with a second element configured to prevent the formation of silicon nitride during or after the deposition of the second superconducting electrode layer. The Josephson junction device is produced by patterning the stack.

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A micro-electronic component (1) according to the invention, for example an integrated circuit chip (1), comprises a front-end-of-line (FEOL) portion and a back-end-of-line (BEOL) portion at its front side. A back side power delivery network (PDN) is furthermore present at the back side of the component, with via connections (49) connecting the PDN to the FEOL and BEOL portions. The back side PDN is different from prior art designs, in that it comprises a 'dry part' and a 'wet part' : the dry part includes multiple interconnect levels of the PDN embedded in a dielectric material (57), as known in the art. The 'wet part' comprises the remaining PDN levels which are however not embedded in a dielectric but which are part of a manifold structure configured to receive therein a flow of cooling fluid in order to remove heat generated by the devices in the FEOL portion.

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A method for forming a buried metal line (110) in a semiconductor substrate (120) is disclosed. The method comprises forming, at a position between a pair of semiconductor structures (131, 132), a metal line trench (112) in the semiconductor substrate at a level below a base of each semiconductor structure of the pair, and forming the metal line in the metal line trench by means of area selective deposition of a metal line material (114), followed by embedding the pair of semiconductor structures in an insulating layer (140).

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An input circuitry for receiving electrode signals comprises: a plurality of channels (110) for providing a multiplexed electrode signal input, each channel (110) comprising a multiplexing switch (114) for selecting one channel (110) at a time, and an input transistor (112) configured to be connected to an electrode (102; 402; 502), wherein the input transistor (112) is configured to receive an electrode signal at a gate; and a reference input transistor (142), which is configured to be connected to a reference voltage at a gate; wherein an electrode signal received at a selected channel (110) together with the reference voltage form input signals to an instrumentation amplifier; wherein the input circuitry (100) is configured such that the input transistor (142) of the selected channel (110) forms part of a first flipped voltage follower (120) and the reference input transistor (142) forms part of a second flipped voltage follower (140).

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