imec Patente

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A coated cathode comprising: an active material (10) for supplying and storing Li+ ions, an electrically conductive additive (12), and a coating (11), different from the active material (10), that coats surfaces of the active material (10), wherein the coating (11) comprises amorphous halogen-doped titanium oxide, and wherein the coating (11) has a thickness of from 1 to 20 nm.

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An ultrasound transducer comprising:an array of ultrasound transducing elements;a plurality of transducer drive lines;an array of control circuits, wherein each individual control circuit of the array of control circuits comprises a drive switch and a memory element, the drive switch being a switch having an on-state and an off-state, the drive switch comprising at least one thin-film transistor, the memory element being configured to store and control the state of the drive switch;wherein each individual ultrasound transducing element of the array of ultrasound transducing elements has one associated control circuit of the array of control circuits and one associated transducer drive line of the plurality of transducer drive lines, wherein the ultrasound transducer is configured to, for each individual ultrasound transducing element:drive the individual ultrasound transducing element by the associated transducer drive line when the drive switch of the associated control circuit is in the on-state.

A method (100) for forming a nanosheet-based transistor device is provided. The method (100) comprises forming (105) a shallow trench isolation, STI, structure (212) in a substrate (202), forming (110) a fin-shaped structure (214) from the substrate (202), a bottom sacrificial layer (204), and a stack of layers (208, 210), forming (115) a dummy gate stack (216) over a channel region of the fin-shaped structure (214), forming (120) a source/drain, S/D, recess (218) at a S/D region (218) of the fin-shaped structure (214), the S/D recess (218) extending through the stack of layers (208, 210) and the bottom sacrificial layer (204), removing (125) the bottom sacrificial layer (204) thereby forming a void space, depositing (130) a bottom dielectric insulation, BDI, layer (220) in the void space, extending (135) the S/D recess (218) further into the substrate (202), depositing (140) a via buried power rail, VBPR, plug (222) in the extended S/D recess (218), forming (145) an epitaxial, EPI, structure (224) to form a S/D feature (224) above the VBPR plug (222) in the S/D recess (218), removing (150) the dummy gate stack (216), selectively removing (155) the plurality of sacrificial layers (210) in the channel region, forming (160) a replacement metal gate, RMG, structure (226) around each of the plurality of released channel layers (208), thinning (165) the substrate (202) from a backside thereof, selectively etching (170) the VBPR plug (222) to expose the S/D feature (224), and forming a backside S/D electrical contact (238) at the S/D feature (224).

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A photovoltaic module (100) which comprises at least one string (130) of solar cells (110) wherein the solar cells (110) are electrically connected in series using a plurality of connecting elements (120), wherein each connecting element (120) electrically connects a frontside of one of the solar cells (110) of the at least one string (130) with a backside of the neighboring solar cell (110) of the at least one string (130); a weave (140) of electrically insulating yarns on which the solar cells are positioned; at least one electronic device (143) comprising a first terminal (143a), and a second terminal (143b), wherein the at least one electronic device is fixed to the weave (140) and wherein the first terminal (143a), and the second terminal (143b) are respectively electrically connected with the connecting elements at the backsides of neighboring solar cells of the at least one string (130).

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The disclosure relates to a method for forming a semiconductor device, the method comprising: forming a device structure on a substrate, the device structure comprising a fin structure comprising a pair of source/drain bodies and a channel region between the pair of source/drain bodies, the channel region comprising at least one channel layer, and the device structure further comprising a gate structure extending across the channel region of the fin structure; forming a metal layer over the source/drain bodies; etching the metal layer to define respective source/drain contacts on the source/drain bodies; and depositing an interlayer dielectric layer over the gate structure and the source/drain contacts.

A computer-implemented method of training a self-coherent detector module (200) to recover distorted optical transmission signals, and processing devices adapted to perform the method are disclosed. The detector module comprises an optical filter unit (210), a detection unit (221) for detecting an amplitude component of an optical input, and digital signal processing circuitry (230) configured to retrieve a phase component of the optical input from the amplitude component. The method comprises iteratively computing updates (104) of adjustable filter coefficients of the filter unit, based on a received first dataset (100), and replacing training signals (105) of the first dataset, taking the updated filter coefficients into account. An initial set of filter coefficients is pre-trained (102) on a received second dataset (103). Training signals of the first and second dataset comprise distorted optical transmission signals that are subjected to filtering by the filter unit.

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The present disclosure provides a multibit memory cell (100), including a plurality of SOT tracks including at least a first SOT track (110) and a second SOT track (112) separate from the first SOT track, and a plurality of MTJs including at least a first MTJ (120) provided on the first SOT track, and a second MTJ (122) and a third MTJ (124) provided on the second SOT track. The cell further includes an electrically conductive path (130) connecting the first MTJ and the second MTJ together, and a plurality of terminals (140-145, of which some may be optional) for providing a first SOT write current for the first MTJ, a second SOT write current for the second MTJ, and at least one of the second SOT write current for the third MTJ, a third SOT write current for the third MTJ, and an STT write current through the third MTJ. The junction resistances of the various MTJs are such that a combined multibit memory state of the MTJs is readable by a read current (160) through all the MTJs in series.

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