imec Patente

According to an aspect there is provided a device for mechanical phenotyping of cells, said device comprising:a sample vessel configured to accommodate a sample fluid comprising cells at an analysis position;an ultrasound generation unit integrated with the sample vessel,wherein the ultrasound generation unit is configured to generate an acoustic wave and to transmit the acoustic wave into the sample vessel at the analysis position for causing the acoustic wave to interact with the sample fluid forming a response acoustic wave being affected by the sample fluid; andan ultrasound detection unit integrated with the sample vessel, wherein the ultrasound detection unit is configured to detect the response acoustic wave and to generate a signal representing information of a cell in the sample fluid.

According to an aspect, there is provided a method for forming a memory structure for a 3D NAND flash memory, the method comprising: forming a layer stack over a substrate, the layer stack comprising an alternating sequence of gate layers and inter-gate spacer layers; forming recessed areas in a sidewall surrounding a memory hole in the layer stack by laterally etching back the gate layers relative to the inter-gate spacer layers from the memory hole; forming an initial charge trap layer in each recessed area; depositing a tunneling oxide layer in the memory hole; depositing a channel layer on the tunneling oxide layer; forming an access trench in the layer stack; forming gate cavities in the layer stack by laterally etching back the gate layers from the access trench in a direction towards the memory hole, wherein the gate cavities expose the initial charge trap layers; oxidizing a portion of the initial charge trap layer in each gate cavity such that the oxidized portion forms a blocking oxide layer and a non-oxidized portion of the initial charge trap layer remains to form a final charge trap layer between the blocking oxide and the memory hole; and subsequent to forming the blocking oxide layer and the final charge trap layers, forming gate layers in the gate cavities by depositing gate material in the gate cavities via the access trench.

A method for forming a memory structure for a 3D NAND flash memory, the method comprising:forming a layer stack over a substrate, the layer stack comprising an alternating sequence of gate layers and inter-gate spacer layers;forming recessed areas in a sidewall surrounding a memory hole in the layer stack by laterally etching back the gate layers relative to the inter-gate spacer layers from the memory hole;forming a discrete blocking oxide layer in each recessed area, wherein a thickness of each blocking oxide layer in a lateral direction is less than a depth of each recessed area in the lateral direction;conformally depositing a continuous liner layer on exposed surfaces in the memory hole, wherein the liner layer covers the blocking oxide layer in each recessed area;depositing a continuous sacrificial layer on the liner layer;etching back the sacrificial layer such that the liner layer is exposed outside the recessed areas and discrete portions of the sacrificial layer remain in the recessed areas;removing exposed portions of the liner layer while using the discrete sacrificial layer portions as an etch mask such that discrete portions of the liner layer covered by the discrete sacrificial layer portions remain in the recessed areas;removing the discrete portions of the sacrificial layer in the recessed areas;forming a discrete charge trap layer in each recessed area, wherein each charge trap layer is deposited on the discrete liner layer portion remaining in each recessed area by a first area-selective deposition process while using the discrete liner layer portion as a seeding layer;subsequent to forming the charge trap layers, depositing a tunneling oxide layer in the memory hole; anddepositing a channel layer on the tunneling oxide layer.

The disclosure relates to an integrated optical structure (10). The integrated optical structure (10) comprises an optical waveguide structure (11); a beam structure (12) which is suspended at a first distance to the optical waveguide structure (11), wherein the beam structure (12) comprises a first section (12A) of a first material and a second section (12B) of a second material, wherein the first material is a conductive material and the second material is a non-conductive material or a semiconductor; an electrode structure (21) arranged at a second distance to the beam structure (12); and an electrical contact structure configured to apply a voltage between the electrode structure (21) and the first section (12A) of the beam structure (12) inducing an electrostatic force acting between the electrode structure (21) and the first section (12A); wherein the beam structure (12) is designed to be elastically bent towards or away from the optical waveguide structure (11) by the electrostatic force causing a change in an optical property, in particular a phase, of an optical signal propagating through the optical waveguide structure (11).

A semiconductor structure, comprising: a semiconductor-based substrate; a barrier layer disposed on the substrate; an electroplating seed layer disposed on the barrier layer; wherein the barrier layer is configured for mitigating atom diffusion from the seed layer into the substrate; a capping layer disposed on the seed layer and configured for resisting oxidation of the seed layer; and a solder bump disposed on the capping layer.

This disclosure relates to droplet manipulation and sensing of a capacitive value of an electrode element used for the droplet manipulation. To this end, the disclosure presents an input-controlled oscillator circuit connectable to the electrode element. A node of the oscillator circuit is connectable to the electrode element. The oscillator circuit comprises an input stage connected to the node for providing a current or current pulse for charging an electrode of an electrode pair of the electrode element based on a control input. The oscillator circuit also comprises an oscillator core circuit connected to the node for cyclically discharging the electrode of the electrode element, to generate an oscillation with a frequency depending on the electrode element capacitance. The oscillator core circuit produces a voltage signal at an output node, which is based on a capacitance value of the electrode element and on the control input shifting the oscillation frequency.

A target layer (25) that needs to be patterned is formed on a support substrate (26). An etch stop layer (27) and a first mask layer (28) are produced in that order on the target layer. According to embodiments of the invention, the first mask layer is patterned into a regular 2-dimensional array of openings (30). In a first directional etching step, the openings in the first mask layer are enlarged to thereby form a pattern of parallel first trenches (31) in the first mask layer (28). A second mask layer (32) is produced, possibly after thinning the patterned first mask layer. The second mask layer is patterned into the same regular array of openings (30) and thereafter the second mask layer is subjected to a second directional etching step, which enlarges the openings in the second mask layer to thereby form second parallel trenches (33) extending in a direction that crosses the direction of the first trenches,. The second directional etching also removes exposed portions of the first mask layer (28), so that the latter is eventually patterned into a pattern of pillars (34). After stripping the second mask layer (32) relative to said pillars, the pattern of pillars is transferred to the target layer (25).

A method for forming a microfluidic device includes: providing a substrate with electrodes having distal ends buried in the substrate; forming interconnect and dielectric layers; exposing the substrate surface by forming a hole through layers; filling the hole with sacrificial material; forming a composite layer with a first structure as a placeholder for a microfluidic compartment and a second structure enclosing the first structure; selectively etching the substrate to expose electrodes and filled hole surface; and removing sacrificial material, thereby forming a through-hole and a microfluidic compartment fluidically connected. The electrodes form a ring around the hole with the hole positioned within the ring boundary, enabling culturing of three-dimensional biological cell structures.

A method for fabricating one or more airbridge structures and one or more 3D integration modules on a patterned metallization layer of a wafer comprising qubits or superconducting electronics, the method comprising: providing the wafer with the patterned metallization layer; depositing an integrated metallization layer, either before or after providing and patterning a first resist layer; forming one or more airbridge structures which are contacting the patterned metallization layer at openings in the first resist layer, wherein the one or more airbridge structures are made of a superconductive material at operating temperatures; and fabricating 3D integration modules by electroplating predefined regions of the integrated metallization layer.

The present disclosure relates to an isolator device, which is realized by employing non-reciprocal coupling of electromagnetic modes of a transmission line. A device and method are presented, which enable broadband isolation in a bandwidth of interest. This is achieved by controlling a multitude of controllable impedance elements, which are distributed along a transmission line, to generate a set of impedance modulations in the transmission line, and with the impedance modulations new tones in the electromagnetic waves propagating supported by a first subset of modes in the transmission line. Depending on the direction of propagation of the electromagnetic waves, the new tones may constructively or destructively interfere, respectively leading to or preventing parametric coupling from the first subset of modes to a second subset of modes of the transmission line.

The present disclosure relates to transmission lines, and is particularly concerned with coupling of electromagnetic waves between two transmission lines. A device and method are presented, which enable broadband non-reciprocal coupling of the electromagnetic waves between two asymmetric transmission lines. This is achieved by controlling individually a set of tunable impedance elements, which are distributed along at least one of the transmission lines, to generate a set of impedance modulations in the transmission line, and with each impedance modulation new tones in the electromagnetic waves propagating in the transmission line. Depending on the direction of propagation of the electromagnetic waves, the new tones may constructively or destructively interfere with modes of the other transmission line, leading to the non-reciprocal coupling.

The disclosure relates to a NAND flash memory device (10). The NAND flash memory device (10) comprises: a semiconductor channel layer (12) extending along a first axis; a first dielectric layer (13) arranged above the semiconductor channel layer (12); a charge storage layer (14) arranged on the first dielectric layer (13); a second dielectric layer (15) arranged on the charge storage layer (14); and a plurality of gate structures (19) arranged above the second dielectric layer (15) and along the first axis; wherein each gate structure (19) comprises a first section (16) and a second section (17), wherein the first section (16) and the second section (17) are designed to have different work functions, and wherein the first section (16) and the second section (17) are arranged next to each other along the first axis.

There is provided a method for forming an interconnect structure for an integrated circuit device, the method comprising: forming a workpiece for a second interconnect layer on a sacrificial substrate, wherein the workpiece comprises at least a first workpiece metal layer epitaxially grown on a growth surface of the sacrificial substrate; bonding the workpiece to an initial interconnect structure of a device wafer, the initial interconnect structure comprising a first interconnect layer surrounded by an interlayer dielectric layer; subsequent to the bonding, removing the sacrificial substrate from the first workpiece metal layer; and patterning the workpiece comprising the first workpiece metal layer to form a second interconnect layer over the first interconnect layer.

In a quantum dot device according to the invention, a plurality of gates (1,2) is provided on a gate dielectric layer (4) formed on a semiconductor substrate (3) configured to confine qubits in well-defined quantum dots. Via connections (10,18) which are directly contacting the gates include at least one or more via connections formed of an electrically conductive ferromagnetic material, whereas the via connections which are contacting the remaining gates are not formed of a ferromagnetic material. Also, the material of the gates (1,2) is electrically conductive but not ferromagnetic. The invention thereby enables addressing and controlling individual qubits associated to gates contacted by ferromagnetic via connections (10) which are configured to act as permanent magnets in the operative quantum dot device.

This disclosure is concerned with imaging at least one or more objects contained inside a liquid sample. A method of the disclosure comprises generating at least one hologram of the one or more objects contained in the liquid sample by using in-line lens-free imaging. The at least one hologram includes at least one artifact, which is at least caused by the presence of the liquid sample and affects the at least one characteristic of the one or more objects contained in the liquid sample. The method comprises removing fully or partially the at least one artifact or the cause of the at least one artifact. The method further comprises generating an image, after or during removing the at least one artifact or the cause of the at least one artifact, the image comprising the one or more objects. The method also comprises recognizing the at least one characteristic of the one or more objects based on the image.

An ultrasonic transducer (100) comprising: a substrate (110) comprising a frontside (110a) configured to face an external medium (190) for propagation of an ultrasound wave; and a membrane (120) arranged to be suspended at a distance from a cavity surface (135) of the substrate (110a) for defining a cavity (130) between the membrane, the cavity surface (135), and at least one cavity wall (140), wherein the membrane is configured to transversally vibrate; wherein the ultrasonic transducer (100) comprises a venting hole (160) at the frontside (110a) and a venting channel (180) configured to connect the cavity (130) to the venting hole (160); wherein the transducer (100) has an acoustic resonance frequency and the membrane (120) has a membrane resonance frequency, and wherein the ultrasonic transducer (100) is configured to provide transduction for the ultrasound wave having a frequency corresponding to the acoustic resonance frequency.

The disclosure relates to an integrated photonic chip (10) for optical coupling. The photonic chip comprises a substrate (11), a spot size converter (12) formed on a frontside surface of the substrate (11), a mirror (13) formed on the frontside surface of the substrate, and a meta-lens (14) formed in or on a backside surface of the substrate (11). The spot size converter (12) enlarges a diameter of a light beam in the photonic chip (10) from a smaller mode size to a larger mode size. The mirror receives the larger mode size light beam (15a) from the spot size converter (12), and reflects the light beam at an angle into the substrate. The meta-lens collimates the light beam (15b) reflected by the mirror and expanded when passing through the substrate, and outputs the collimated light beam (15c) towards the optical device.

A pattern is produced in a die area (25) of a layer (30,33) formed on a support substrate (32) by at least two process sequences, each comprising a lithography step and an etch step, performed in adjacent subportions of the die area. One or more parallel line shaped features (28) of the pattern extend from the first subportion (25a) of the die area to the second subportion (25b), i.e. across the border (27) between the die areas. Mutually aligned and spaced apart first and second parts of the line features are printed in the respective process sequence steps and transferred to the layer in the form of negative or positive pattern features in the patterned layer, i.e. in the form of trenches (28'a,28'b) in the layer or in the form of lines separated by mutually aligned trenches (37a;37b). In either case, directional etching is thereafter applied to stretch the aligned trenches and thereby obtain the desired line features (28) extending from one subportion of the die area to the other subportion.

A stack of alternatingly applied etch stop layers (27) and mask layers (28) is produced on a target layer (25) present on a support substrate (26). The target layer is to be patterned according to a pattern comprising parallel line features (34,34'). The top mask layer is patterned according to a pattern of openings (30) and thereafter these openings are elongated by directional etching relative to the etch stop layer, to form a pattern of elongated openings (31,31'). This pattern is transferred to the subsequent mask layer (28) and in said subsequent mask layer, the elongated openings are further elongated by directional etching. This sequence is repeated down to the bottom mask layer. In said bottom mask layer, the pattern of openings has been elongated to a set of lines (34,34'), which are then transferred to the target layer. By repeating the elongation process a number of times, the obtainable elongation is increased compared to a process wherein only one directional etch step is applied.

The method comprises the steps of producing a stack of at least two layers (30,31,32) on a support substrate (25), by lithography and anisotropic etching, producing an opening (33) through said stack of at least two layers, and thereafter applying at least a first directional etching process step, using an etch beam configured to remove the material of one or more upper layers (32) of the stack selectively with respect to the layer or layers (30,31) directly underneath said one or more upper layers, to thereby enlarge the opening in the one or more upper layers (32) while essentially maintaining the in-plane dimensions of the opening in the layer or layers (30,31) directly underneath the one or more upper layers (32). The method can be applied to a stack of several layers which can be enlarged stepwise with respect to further underlying layers of the stack. Directional etching can be done in two opposite directions, possibly applying different etch chemistries in the two directions, to thereby enable the creation of complex three-dimensional structures without requiring expensive multiple lithography steps.

A layer (28) is produced on an etch stop layer (27) formed on a support substrate. The layer is patterned by forming at least one opening (30) having upright sidewalls through the full thickness of the layer. The opening is enlarged by a sequence of directional etch steps wherein the angle of incidence of the applied plasma beam (8) is increased at every subsequent step compared to the previous step, so that the plasma beam impinges on the full height of the sidewall of the opening (30) or enlarged opening (31) at every step. Subsequent directional etch steps can be performed in the same scanning direction at each step, or the scanning direction can be changed at every step or combinations of equal and differing scanning directions can be applied, enabling thereby to obtain various shapes of pattern features. The adjustment of the angle of incidence enables a higher etch rate in the scanning direction and thereby a higher obtainable elongation compared to methods wherein repeated directional etch steps are performed applying he same angle of incidence at each step.

An imaging system (100) for medical imaging is provided. The imaging system comprises at least one training device (101), and at least one imaging device (102) operably coupled to the at least one training device (101), wherein the at least one imaging device (102) being configured to be attached to the skin of a person at a predefined location. In this regard, the at least one imaging device (102), in combination with the at least one training device (101), is configured to generate a first set of images corresponding to the predefined location, whereby the at least one training device (101) is configured to generate training data corresponding to the predefined location based on the first set of images. Furthermore, the at least one imaging device (102) is further configured to exclusively generate a second set of images corresponding to the predefined location based on the training data.

In an aspect there is provided a computer-implemented method for designing an IC comprising CFET devices. The method comprises obtaining a functional description of the integrated circuit, and generating, based on the functional description, a layout of the integrated circuit. The layout defines first and second cell rows extending in parallel in a horizontal direction of the layout, and having equal row heights in a vertical direction of the layout. Generating the layout comprises placing first and second cells of a standard cell library in the layout. Each cell has a cell height equal to the row height, and comprises first and second cell edges extending in parallel in the horizontal direction. Each cell further comprises at least one CFET device having an active pattern extending in the horizontal direction. Each cell further comprises at least one local interconnect (LI) disposed on the second cell edge and configured to connect to a top and/or bottom S/D of a CFET device of the cell. The first and second cells are placed in the first and second cell rows, respectively, such that: the first cell edge of the first cell aligns with a first row boundary, the first cell edge of the second cell aligns with a second row boundary, and the second cell edges of the first and second cells align with and abut each other along a third row boundary between the first and second cell rows. The placement of the first and second cells is constrained such that the local interconnects of the first and second cells do not overlap.

The invention relates to a bicelle entity comprising a bicelle structure with a rim and first and second amphiphilic compounds, the first having a longer hydrophobic chain, and at least one extension configured to bind a DNA origami envelope or its extension. It further relates to a DNA origami envelope adapted for such binding and to a complex formed by their assembly. A kit comprising the bicelle entity and the DNA origami envelope is also provided. The invention additionally concerns a hybrid pore device incorporating the complex with a solid-state pore. Methods are disclosed for manufacturing the complex by assembling the bicelle entity and DNA origami envelope, and for producing the hybrid pore device by integrating the complex with the solid-state pore.

A method for screening entities with different characteristics for their effect on biological cells of a biological cellular material, comprising: laterally constraining said entities having different characteristics in different locations of said biological cellular material, thereby preventing mixing of said entities having different characteristics; applying a transfection activation field to said different locations to allow said entities to be delivered into said biological cells, thereby allowing said entities to have an effect on said biological cells; and detecting said effect.

A microfluidic device (100) comprising: a monolithic semiconductor substrate (10) with thermal conductivity ks; one or more heaters (20) on its top surface, each with a heating element (21); a thermal insulation layer (40) between the heaters (20) and the substrate (10), with thermal conductivity ki at least 50 times smaller than ks; and one or more liquid cooling units (30) with cooling fins (31) on the substrate's bottom surface. Each fin (31) has an extremity (32) within 100 µm of a heating element (21). A cover (60) encloses the cooling units (30), forming cooling channels (61) and including inlet (62) and outlet (63) ports for liquid circulation.

A method for identifying biomarkers of a health condition, comprising: providing a first neuronal circuit with neuronal cells from a first individual organism on a multi-electrode array, applying stimuli to the circuit, obtaining electrophysiological recordings, deriving cell-level and/or circuit-level features from the recordings, associating derived features with presence or absence of the health condition, comparing associated data with reference data, and determining if reference features or derived features are biomarkers for the condition.

A device for delivering charged entities into biological cells of a biological cellular material, comprising a microelectrode array for supporting the biological cellular material, the microelectrode array comprising individually addressable electrodes made of an electrically-conductive CMOS-compatible material having an oxide top layer, and the charged entities electrostatically coupled to the oxide top layer. The oxide top layer may be a native oxide top layer. The charged entities can be negatively charged entities electrostatically attached to positively charged carriers directly attached to the oxide top layer, or positively charged entities encapsulated in a negatively charged carrier electrostatically coupled to the native oxide top layer. The electrically-conductive CMOS-compatible material can be a metal, metal nitride, or metal oxide. Charged entities differing in their characteristics may be electrostatically coupled to distinct electrodes of the microelectrode.

In a first aspect, the present invention relates to a gas diffusion electrode (15) for electrochemical gas conversion, comprising: i) a porous solid structure (20), comprising a network (30) formed of a plurality of interconnected electrically conductive wires, and a catalytic surface (32) for catalysing the electrochemical gas conversion, said catalytic surface (32) being a surface of the network (30) as such or of a catalyst (31) coating the network (30); and ii) an electrolyte (50) in the porous solid structure (20) and in contact with the catalytic surface (32); wherein-in operation-at least one side of the porous solid structure (20) is directly exposed to a gas flow comprising the gas to be converted (60), or indirectly exposed to said gas flow through a diffusion layer having a thickness of 10 µm or less, preferably 1 µm or less.

Disclosed is a two-electrode device, such as a Josephson junction or a capacitor, comprising top and bottom electrodes (18, 27) formed of superconducting NbTiN which are separated by a non-superconducting interlayer (17), wherein the bottom electrode is larger than the interlayer and the top electrode. The electrodes and the interlayer are formed by two separate patterning steps and embedded in an enveloping dielectric material (25, 28, 35) that is subsequently planarized by a first CMP stopping on the upper surface of the top electrode (18), thereby forming a first planarized surface (36). Thereafter, a via opening (39) is formed, exposing the upper surface of the bottom electrode (27), filled with an electrically conductive material (40), and planarized by a second CMP. Wiring conductors (57, 58) are then formed on the second planarized surface (36').

A device (100) for analysis of a test object (10) using photo-acoustic effect comprises: an optical arrangement (102) configured to output spatially separated light comprising a plurality of wavelengths, wherein light of different wavelengths of the plurality of wavelengths is separated into different spatial directions; and a spatial light modulator (130) configured to receive the spatially separated light, wherein the spatial light modulator (130) comprises a plurality of individually controllable regions (132), wherein each individually controllable region (132) is configured to receive a portion of the spatially separated light for associating each individually controllable region (132) with a specific wavelength of the plurality of wavelengths, wherein each individually controllable region (132) is configured to modulate the portion of the spatially separated light with a modulation frequency for generating modulated light for inducing a photo-acoustic effect in the test object.

The present disclosure relates to a semiconductor structure for a 3D DRAM comprising one 1T1C memory cell architecture and vertical bit lines. The semiconductor structure comprises a stack of semiconductor layers and dielectric layers alternatingly arranged along a first axis. Further, a first and second pillar of memory cells arranged displaced along a second axis and extending along the first axis through the stack. Each memory cell comprises a part of one of the semiconductor layers, and one transistor structure and one capacitor with a semiconductor channel and a metal gate that at least partly surrounds the semiconductor channel. The metal gates of memory cells in the same pillar are isolated from each other, and metal gates of memory cells that comprise parts of the same semiconductor layer form an integral metal structure.

A hardware random number generator (HW-RNG) for drawing samples from a multivariate target distribution through simulation of a Markov chain is disclosed. The HW-RNG (100) has a pipeline architecture operating in cycles. The HW-RNG comprises sets of p-bit devices (112-1; 112-2; 112-N), a programming unit (150) to program the sets of p-bit devices according to a corresponding set of adaptive proposal distributions, selection circuitry (121) to select one of the sets of p-bit devices, a sampling circuit (130) configured to produce a candidate sample from the proposal distribution associated with a selected one of the sets of p-bit devices, and a scheduling unit (140). The scheduling unit (140) is configured to accept the candidate sample with an acceptance probability, and recompute at least one of the proposal distributions that is conditionally dependent on the accepted candidate sample. A programming phase for each set of p-bit devices lasts for x cycles, and there are N > x sets of p-bit devices.

A method (1000) for use in millimeter-wave beamforming comprises acquiring (1004) a direction of a first beam (103) and a direction of a second beam (105); selecting (1008) an analog beamforming profile based on an angular separation between said first beam (103) and said second beam (105); and communicating (1010) through said first beam (103) and said second beam (105) according to the selected analog beamforming profile.

A processor core (1) of the SIMT type and a related method of operation are disclosed. The processor core comprises frontend circuitry (10), a plurality of lanes (20a-f), a multi-banked and arbitration-free scratchpad memory (40), and an interconnect (50) to couple active ones of the plurality of lanes to different ones of the scratchpad memory banks. There are at least as many banks as lanes in the processor core. Each lane comprises a thread-private register file (21a-f) and address generation logic (22a-f) to independently calculate an effective address of an operand within the scratchpad memory. An execution pipeline of the processor core, associated with the thread-parallel execution of vector memory instructions, comprises at least the address generation logic of the different lanes, the interconnect, and the different banks as pipeline components. The processor core is implemented as a stack of dies (2a, 2b) including the frontend circuitry and the plurality of lanes on a first die (2a) and the scratchpad memory on a second die (2b).

A hardware random number generator (HW-RNG) and related method are disclosed. The HW-RNG comprises a sample generation stage, adapted to produce primary samples from a plurality of primitive probability distributions, a sample processing stage and a control unit. The sample generation stage includes sets of programmable p-bit devices, a programming unit to adjust the mean values for each set of p-bit devices, and a distinct sampling circuit for each set of p-bit devices. The sample processing stage comprises function logic blocks and selection circuitry configured to route at least one subset of the primary samples to a corresponding function logic block. The control unit is configured to obtain information relating to a composition of basis distributions representative of a target distribution, instruct the function logic block to perform at least arithmetic operation identified by the information, instruct the programming unit to program the sets of p-bit devices according to the composition of basis distributions, and generate the select signal to operatively couple the function logic block to sampling circuits that produce primary samples of random variables defined by the composition of basis distributions.

There is provided a nearfield beam shaping device. The device comprises a linear transformer comprising: an input for receiving a light beam; a plurality of optical gates; a plurality of single-mode waveguides. The optical gates distribute the power of the light into portions, each portion being distributed to a respective single-mode waveguide. The optical gates provide control of phase of the light in the single-mode waveguides. The device comprises a mode transformer comprising: a plurality of mode transformer inputs, each being connected to a respective single-mode waveguide; a multimode waveguide, the mode transformer inputs being coupled to the multimode waveguide for exciting a plurality of spatial modes therein; and an output for outcoupling the plurality of modes from the mode transformer. The device controls, based on at least the control of the phase of the portions of light in the single-mode waveguides, the relationship between the modes in the multimode waveguide for controlling the nearfield beam shape of an output light beam based on the plurality of modes outcoupled from the mode transformer.

A Single Instruction Multiple Threads (SIMT) processor core comprising: (a) a configurable dataflow backend operative to support subword parallelism for execution of mixed-precision arithmetic operations, wherein the backend includes multiple dataflow network stages, each dataflow network stage including one or more functional units configurable to process multiple subwords within a register in parallel; (b) a configuration memory storing configuration data defining operational configurations of the dataflow network stages in the backend, wherein the configuration memory is accessible via a configuration index mechanism operative to select configuration data from the configuration memory to control the dataflow network stages in the backend, and wherein the configuration index mechanism is configured for enabling the dataflow backend to support multiple variations of mixed-precision arithmetic operations without requiring dedicated instructions for each variation.

A programmable processing unit, method of operating a processing unit, and a computer-readable storage medium are provided. The programmable processing unit comprises a plurality of vector portions, providing registers and vector operation units, and a controller. The controller comprises control logic configured to obtain an instruction involving vector operations and invoke a plurality of threads to execute the instruction on respective vector input data. At least one of the plurality of threads executes a vector operation on respective vector input data using the plurality of vector portions.

A method for preparing a plurality of optical structures (120) for transfer printing is provided, a method for transfer printing, an assembly of optical structures (320) for transfer printing, and an optoelectronic device comprising at least one of the plurality of optical structures (120) is provided. The method for preparing the plurality of optical structures (120) for transfer printing comprises: obtaining an assembling structure (110) comprising an optical material, wherein the assembling structure (110) comprises a pattern in the optical material, the pattern comprising trenches (130) at a first side (112) of the assembling structure (110) for defining the plurality of optical structures (120), each of the plurality of optical structures (120) comprising an interface surface (122) in the optical material, the interface surface (122) being arranged at the first side of the assembling structure (110); bonding the assembling structure (110) to a temporary bonding layer (140) and a temporary carrier layer (150), wherein the interface surface (122) and the trenches (130) faces the temporary bonding layer (140) and the temporary carrier layer (150), the temporary bonding layer (140) being arranged between the assembling structure (110) and the temporary carrier layer (150); and removing a portion of the assembling structure (110) in order to form and separate the plurality of optical structures (120), wherein the plurality of optical structures (120) are defined for transfer printing from the temporary carrier layer (150).