NXP Semiconductors Patente

The disclosure relates to voltage glitch detection in an integrated circuit for detection of fault injection attacks. Example embodiments include an integrated circuit (411) comprising: a hardware accelerator (412) including a computing module (413₁, 413₂) configured to perform a computing function; and a glitch detector (416₁, 416₂) including a delay function (413₁, 413₂) and a comparator (419₁, 419₂) arranged to compare an output from the delay function (413₁, 413₂) with an expected result to provide an output for detecting a glitch, wherein the delay function (413₁, 413₂) of the glitch detector (416₁, 416₂) is provided at least in part by the computing function of the computing module (413₁, 413₂) in the hardware accelerator (412).

A computer-implemented method is provided which simplifies the configuration of smartcard readers and enables use-case specific APDUs to be provided. The command-response interactions associated with smartcard interactions can be identified using a script by the user. The interaction can be used to execute an instruction by associated logic.

An apparatus comprising a phase locked loop circuit including: an input configured to receive an oscillating reference signal having a reference period; a current-controlled-oscillator, CCO, configured to generate an oscillating output signal based on an input signal; an error detector configured to generate one or more error signals based on a phase difference between the reference signal and one or more feedback signals wherein the feedback signals are based on the oscillating output signal; and a charge pump circuit configured to receive at least a first of the error signals, determine a voltage indicative of a duration of the first error signal during a first part of the reference period, and provide a control current to the CCO for at least a remaining part of the reference period, wherein the control current comprises at least part of the input signal to the CCO and is based on the determined voltage.

The present disclosure relates to an Ethernet Phy comprising: an analog interface for connecting to a communication media, a digital interface, and a wake-up interface, wherein the Ethernet Phy is configured to change from a sleep mode to an active mode, or vice versa, wherein the Ethernet Phy is configured to receive a first analog signal via the analog interface, wherein the first analog signal represents an Ethernet frame, wherein the Ethernet Phy is configured to transmit the Ethernet frame in the active mode only via the digital interface, wherein the Ethernet Phy is configured to receive a first wake-up signal in the sleep mode via the wake-up interface representing a first wake-up identifier or a second wake-up identifier, wherein the Ethernet Phy is configured to change from the sleep mode to the active mode in response to the case where the first wake-up signal representing one of the first or second wake-up identifier, and wherein the Ethernet Phy is configured to remain in the sleep mode in response to the case where the first wake-up signal representing the other one of the first or second wake-up identifier. The present disclosure also relates to a method for the Ethernet Phy.

The present disclosure relates to a module for a first Ethernet node of a group of Ethernet nodes, the module comprising a media access control, MAC, interface, a physical coding sublayer, PCS, interface, and a priority manager, PM, interface, wherein the module is configured to receive and/or transmit sequences of a cycle over the interfaces, wherein the cycle comprises a start sequence, a series of multiple priority sequences, an announcement sequence, and a data sequence, wherein the start sequence consists of a sequence of a predefined start symbol and a predefined advertisement symbol, wherein each priority sequence consists of a sequence of a predefined commit symbol and a dedicated priority symbol, which is assigned to the respective priority sequence and indicates a priority of an Ethernet frame ready to be sent by one of the group of Ethernet nodes, wherein the announcement sequence consists of a sequence of the start symbol, a predefined commit symbol and a winner node symbol indicating one of the Ethernet nodes being ready to send the Ethernet frame having the highest priority, and wherein the data sequence comprises the Ethernet frame having the highest priority. The present disclosure also relates to an Ethernet node including the module and a communication system including several Ethernet nodes.

In accordance with a first aspect of the present disclosure, an ultra-wideband (UWB) communication device is provided, comprising: a transmitting unit configured to initiate a device detection session by transmitting a pre-discovery message and to transmit, during said device detection session, at least one discovery message in order to discover one or more external devices; a receiving unit configured to receive, during said device detection session, one or more responses to the discovery message, wherein said responses have been transmitted by said external devices. In accordance with a second aspect of the present disclosure, a corresponding method of operating a UWB communication device is conceived.

A Zener diode includes a P+ anode, a poly mesh ring residing on the surface of the semiconductor substrate and surrounding the P+ anode, an N+ cathode residing opposite the poly mesh ring from the P+ anode, an outer spacer on an outer portion of the poly mesh ring adjacent the N+ cathode, and an inner spacer on an inner portion of the poly mesh ring adjacent to the P+ anode. The poly mesh ring may be a polysilicon layer residing upon a TEOS layer. The Zener diode may reside in a low dope N-well with a Zener junction including a N-well high region adjacent and below the P+ anode. The Zener diode may reside in a high dope N-well with a Zener junction including a P- structure formed in the high dope N-well in an upper portion of the semiconductor substrate and adjacent and surrounding the P+ anode.

There is provided a system and method for detecting location and orientation of a plurality of devices in a surround sound system, the plurality of devices comprising a lead device and a plurality of follower devices. The method comprises a discovery stage in which the lead device discovers the plurality of follower devices. The method further comprises a primary mapping stage in which an ultra-wideband, UWB, connection is created between the lead device and a first group of the plurality of follower devices which are within a field of view, FoV, of the lead device. The method also comprises an orientation detection stage in which a location (X_Fa,Y_Fa) and an orientation Φ_L of each one of the follower devices of the first group is calculated.

Process handler for executing secure operations is disclosed. A token is provided to a user device by a process initiator based on an input received from a user of the user device. The token and user data associated with the input are further received by the process handler from the process initiator and stored by the process handler. When the user device is in proximity of the process handler, the process handler establishes a secure ultrawideband ranging session with the user device and further receives the token from the user device. A match between the received token from the user device and the stored token in the process handler is identified. The process handler validates the user device based on the match. Based on the validation of the user device, the process handler executes the secure operation on the user data.

An automotive controller for controlling a heating, ventilation and air conditioning, HVAC, system of a vehicle, the automotive controller configured to: receive radar data representing an internal cabin of the vehicle; process the radar data to identify an obstructed vent of the HVAC system; and output a control signal to the HVAC system for disabling the obstructed vent.

The present disclosure relates to a coordinator Ethernet node for an Ethernet communication system, the coordinator Ethernet node comprising: an interface for coupling to a shared media of the Ethernet communication system, wherein the coordinator Ethernet node is configured to transmit a first beacon via the interface and to trigger a first arbitration cycle by transmitting the first beacon, wherein the coordinator Ethernet node is configured to transmit a second beacon via the interface after the end of the first arbitration cycle and to trigger a second arbitration cycle by transmitting the second beacon, wherein each arbitration cycle comprises for the coordinator Ethernet node and each follower Ethernet node of the Ethernet network an associated field, referred to as TO field, representing a transmit opportunity for the respective Ethernet node, and wherein at least one of the arbitration cycles comprises a further field, referred to as a diagnostic field for diagnosing the shared media. The present disclosure also relates to a method for the coordinator Ethernet node.

In accordance with a first aspect of the present disclosure, a user authentication device is provided, comprising: a face recognition unit configured to receive a visual input and to extract a biometric marker from said visual input, the biometric marker being a face; a user identification unit configured to identify a user based on the biometric marker extracted by the face recognition unit; a liveness detection unit configured to detect whether the user identified by the user identification unit is a living person, by extracting one or more additional biometric markers from the visual input received by the face recognition unit. In accordance with further aspects of the present disclosure, a corresponding operating method is conceived, and a computer program for carrying out said method is provided.

A processor includes fetch circuitry configured to fetch instructions and a speculation control circuit. The fetch circuitry is configured to, in response to a first interrupt received by the processor, fetch a first interrupt handler instruction for the received first interrupt. The speculation control circuit is configured to, in response to the first interrupt received by the processor, begin speculative pushing of registers onto a memory stack in accordance with a predetermined register order prior to completion of the fetch of the first interrupt handler instruction for the first interrupt, in which a register tracking value is updated with each speculative push.

Radar module assemblies and systems for an automotive distributed coherent radar, DCR, system are disclosed in which the radar module assembly comprises: a radar module including processing circuitry for generating a plurality of radar signals based on a signal at a carrier frequency; a first major surface, having a plurality of antennae thereon, each configured to be fed with a respective one of the plurality of radar signals through a respective waveguide feed and to transmit the respective one of the plurality of radar signals; a launcher configured to launch a synchronization signal from the module, wherein the synchronisation signal is based on the carrier frequency; and an electromagnetic lens on a side face of the radar module and configured to focus the synchronization signal into an inter-module direction.

A method, system, apparatus, and program code are provided for authenticating a user by generating a user prompt identifying a mental task to be performed by the user, scanning the user for a biometric brain activity signal when the user performs the mental task so that the biometric brain activity signal reflects brainwave activity of the user when performing the mental task, and then comparing the biometric brain activity signal to a reference biometric template signal to determine whether to authenticate the user based on whether the biometric brain activity signal matches the reference biometric template signal.

A technique of identifying features of objects in a physical environment of a set of radar sensors includes accessing a plurality of bin identifiers assigned to respective radar detections made by the set of radar sensors, the bin identifiers specifying respective bins. A bin has at least (i) a first dimension representing a range of distance values and (ii) a second dimension representing a range of Doppler values. The technique further includes selecting radar detections based on the bin identifiers, the selecting producing a plurality of samples, and processing the plurality of samples to determine one or more features of the objects.

A cell-averaging constant false alarm rate, CA-CFAR, radar processor configured to: receive a two-dimensional radar data array (202); for each of a plurality of pairs of one-dimensional vectors (204-1, 204-2): perform a convolution between the two-dimensional radar data array (202) and a first one-dimensional vector (204-1) of the pair of one-dimensional vectors to obtain an intermediate convolution result (210); and perform a convolution between the intermediate convolution result (210) and a second one-dimensional vector (204-2) of the pair of one-dimensional vectors to obtain an intermediate CA-CFAR result (208); and combine the intermediate CA-CFAR results to provide a CA-CFAR output.

An electronic device realizes an antenna-in-package (AiP). The device includes a first die having a first metal layer that defines an antenna patch, a second metal layer that defines a parasitic patch above and vertically aligned with the antenna patch, and an amplifier having an output terminal electrically coupled to the antenna patch. The device further includes a second die having a metal layer that defines a reflecting patch and an interconnect that joins the first die with the second die in a vertical stack with the first die above the second die such that the antenna patch is spaced apart from, parallel to, and vertically aligned with the reflecting patch.

A multichannel RF transceiver includes a global biasing circuit (102) comprising: a reference current source (306), a reference diode (307), a first current mirror transistor (304) and a first replica impedance (310); and a plurality of second current mirror transistors (305<1-N>), each having a gate connected to a gate of the first current mirror transistor (304). A plurality of RF amplifiers each comprise a second replica impedance (313) connected between a biasing node (314) connected to a drain of a respective one of the plurality of second current mirror transistors (305<1-N>) and a first RF amplifier transistor (315) connected to an RF input (317) and to the biasing node (314). The first and second replica impedances (310, 313) cause a replica reference current (IReplicaref) through the first and second replica impedances (310, 313) to be smaller than a reference current (ICref) from the reference current source (306).

There is disclosed a transceiver circuit comprising: a receiver channel configured to receive a signal comprising a sequence of symbols comprising interference; an interference detection unit configured to determine a difference signal for each symbol; an interference filter comprising a plurality of filter taps each associated with a different interference symbol of an interference signal, wherein each filter tap comprises: a filter coefficient generator configured to generate a filter coefficient based on: the difference signal; and the interference symbol of the filter tap; and a filter signal generator configured to generate a filter signal based on the filter coefficient and the interference symbol and the filter signal generator is configured to output the filter signal for combination with the received symbol, and wherein each filter signal generator is configured to operate in one of: an activated mode; and a deactivated mode, and the transceiver circuit comprises a tap control unit configured to control whether each filter signal generator of the filter tap operates in the activated mode or the deactivated mode based on a comparison of the filter coefficient to a predetermined threshold value.

An inverter and a ring oscillator (100) comprising a plurality of the inverters arranged in a ring is disclosed. Each inverter (200) comprises an inverter input (210) and an inverter output (220), wherein the inverter output (220) of each inverter (200) in the ring is coupled to the inverter input (210) of the respective next inverter (200) in the ring. At least one (200) of the plurality of inverters comprises: a first NMOS transistor (250), comprising a first gate terminal (252) coupled to the respective inverter input (210), a first drain terminal (254) coupled to the respective inverter output (220), and a first source terminal (256); and a second NMOS transistor (260), comprising a second gate terminal (262), a second drain terminal (264) and a second source terminal (266), wherein said second source terminal (266) is coupled to said first drain terminal (254).

An electronic component includes a transmission structure and a shield structure below the transmission structure. The transmission structure includes a central trace and a pair of lateral traces. The shield structure includes multiple switchable shield elements that extend below the central trace. At least one of the shield elements is selectively electrically connectable to a lateral shield trace, causing the component to assume multiple values of characteristic impedance and phase shift. An associated device and a method of operation are further disclosed.

A method of forming a semiconductor device is provided. The method include forming an interposer having a first set of conductive connection pads exposed at a first major side of an interposer substrate and a second set of conductive connection pads exposed at a second major side of the interposer substrate. A first semiconductor wafer is mounted on the first major side of the interposer substrate and a second semiconductor wafer is mounted on the second major side of the interposer substrate. A sandwich-like structure is formed by the first semiconductor wafer, interposer, and second semiconductor wafer. The sandwich-like structure is singulated to form a plurality of individual semiconductor device units. A plurality of sidewall connection pads are exposed along an outer perimeter of the interposer.

A glitch detection circuit (200) is arranged detect a glitch on a digital supply (150) and comprises a glitch sense threshold generator (132), a path delay circuit (133) comprising two parallel paths, wherein the first path provides a first output of a slow signal path of the digital supply to be detected that is used as a positive glitch threshold signal (530) and the second path provides a second output of a slow signal path of the digital supply to be detected that is used as a negative glitch threshold signal (540). A comparator circuit (134) is arranged to compare the digital supply to be detected with the first output of a slow signal path and the second output of a slow signal path; wherein the output of the comparator circuit indicates a power glitch on the digital supply in response to the positive or negative glitch threshold signals.

A level shifter test circuit, method of testing a level shifter test circuit and a semiconductor chip are provided. The circuit comprises a first level shifter for translating a signal from a first domain to a second domain. The first level shifter configured to receive the signal as an input from the first domain; and output a translated signal which has been translated by the first level shifter for the second domain, wherein the translated signal is split between a first output signal and a first level shifter feedback signal. The circuit further comprises test logic configured to receive the first level shifter feedback signal and test operation of the first level shifter.

To detect a spoofing signal transmitted by an attacker, a spoofing detection circuit forms a ranging circuit group by first selecting two or more ranging circuits each disposed at different locations. The spoofing detection circuit then requests and receives a set of measurements over a period of time from each ranging circuit in the ranging circuit group. Based on the received sets of measurements, the spoofing detection circuit estimates one or more locations for a target, a path of the target, or both. The spoofing detection circuit then determines whether the estimated locations or path of the target indicate spatial consistency or temporal consistency. Based on the estimated locations, estimated path, or both not indicating a spatial consistency, temporal consistency, or both, the spoofing detection circuit determines that a spoofing signal was received by the ranging circuit group.

Disclosed is a DCR system comprising: first and second radar units and a processer, the radar units each comprising: first and second antennas, aligned in a first direction, and offset in a second, orthogonal, direction, and a linear array of antennas distributed along the first direction and including the first or second antenna; wherein: the second radar unit is configured to receive, at is second antenna, a first signal, being a reflection, from a target, of a first FMCW signal transmitted by the first radar unit first antenna; the first radar unit is configured to receive, at its second antenna, a second signal, being a reflection, from the target, of a second FMCW signal transmitted by the second radar unit first antenna; and the processor is configured to estimate phase noise from the first signal and the second signal.

A radar system (120) comprising a first transmitter (124) and a first receiver (125), a second transmitter (126) and a second receiver (127) and a processor (122), wherein the processor (122) is configured to determine a channel sequence for frequency stitching; divide the channel sequence into a first portion and a second portion; instruct the first transmitter (124) to transmit, over a first time period, an RF signal on each RF channel of the first portion of the channel sequence; instruct the second transmitter (126) to transmit, over a second time period, an RF signal on each RF channel of the second portion of the channel sequence, wherein the second time period at least partially overlaps with the first time period; and generate a frequency-stitched channel impulse response from reflected RF signals received at each receiver in response to the RF signals transmitted.

The present disclosure relates to a radar system and related method, where the radar system includes test circuitry and a controller. The controller causes the test circuitry to inject a first pair of test tones having first test tone frequencies and first test tone magnitudes into first and second receiver modules, receive a first and second output signals from the first and second receiver modules, respectively, detect interference based on the first pair of test tones and the first and second output signals, modify, in response to detecting the interference, the first test tone frequencies to produce second test tone frequencies, cause, in response to detecting the interference, the test circuitry to inject a second pair of test tones having the second test tone frequencies into the first receiver module and the second receiver module.

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A latch includes two outputs and two inputs where the outputs latch complementary values indicative of voltages at the latch inputs. The latch includes two sets of one or more inverters. For each set of inverters, the signal input of the first in series inverter is connected to a latch input and the output of the last in series inverter is connected to a latch output. The first in series inverters for each set of one or more inverters has a signal input connected to one latch input and a supply voltage input configured to be biased by the other latch input. During a reset phase, the latch outputs are configured to be set to the same output value state. During a latching phase, the latch outputs are configured to be latched at complementary output value states. In some embodiments, the latch is used in a comparison circuit.

A vehicle includes a compliance security module (CSM) configured to ensure that the vehicle is capable of functioning in accordance with one or more policies. The CSM can be configured to obtain the one or more policies, authenticate the one or more policies, monitor the components of the vehicle and/or inform policy-related components of the vehicle of the one or more policies. The CSM can be configured to validate that the vehicle will comply with one or more policies, for example, by generating and transmitting a compliance certificate to an enforcing authority.

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