imec Patente

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An integrated optical structure (1) for phase front engineering of optical beams (2) comprising:- a substrate (100);- a plurality of optical layers (201;202) formed on said substrate (100) and comprising:o an optical phased array (21;22) comprising a plurality of optical waveguides (220); ando a coupling section (20) for each of said optical waveguides (220) configured to control the phase of an optical beam (2) coupling out of said optical waveguide (220); and- a slab waveguide (300) formed between two of said optical layers (201;202) and in optical communication with said coupling sections (20) of said two optical layers (201;202); and wherein said slab waveguide (300) comprises a slab waveguide outcoupling structure (301) configured for transmission of optical beams (2) out of and/or for reception of optical beams (2) into the plane (7) of said substrate (100).

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A photonic integrated circuit (1, 2, 3) comprising a waveguide (100, 200, 300) for guiding an electro-magnetic wave (110, 210, 310), and a thermomechanical compensator comprising a thermomechanical actuator (120, 220, 320) for interacting with the electro-magnetic wave (110, 210, 310), when present in the waveguide (100, 200, 300), for affecting an effective refractive index experienced by said electro-magnetic wave (110, 210, 310). The thermomechanical compensator is arranged so that a position of the actuator (120, 220, 320) with respect to said waveguide (100, 200, 300) depends on an ambient temperature so as to reduce or minimize an aggregate phase shift of said electro-magnetic wave (110, 210, 310) within at least part of the photonic integrated circuit (1, 2, 3) resulting from a change of said ambient temperature.

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An electric field gradient focusing device (1) comprising: i. a fluidic channel (11) having an inlet (111) and an outlet (112) for a fluid, ii. a first actuation means configured for inducing a fluid flow in the fluidic channel (11) from the inlet (111) to the outlet (112) via AC electroosmosis, and iii. a second actuation means configured for generating a DC electric field gradient along at least part of the fluidic channel (11).

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An integrated circuit (1) comprising: a plurality of interconnects (2) forming at least four repair chains (A, B, C, D), each repair chain (A, B, C, D) comprising: a plurality of primary interconnects (21) for providing a signal path (3), a spare interconnect (22), and circuitry (4) configured for offsetting, within each repair chain, signal paths (3) so as to avoid the use of a defective primary interconnect (23), when present, within the repair chain (A, B, C, D), wherein one signal path (3) is offset to the spare interconnect (22), wherein the plurality of interconnects (2) is arranged so that spatially neighbouring interconnects (2) belong to different repair chains (A, B, C, D).

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The invention is related to semiconductor components such as integrated circuit chips, comprising a multilayer structure such as a back end of line portion, with a plurality of MIM capacitors integrated between two levels of the multilayer structure. The capacitors are realized as an assembly of capacitors, in the form of a stack of at least three electrically conductive layers (20,21,22;50-53) , separated by dielectric layers (23,24,54-56), and formed conformally on a topography defined by a plurality of dielectric pillars (13) distributed on a bottom conductive plate (10) formed on a first level (Mn) of the multilayer interconnect structure. By realizing a height difference between different pillars or different groups of pillars, the intermediate conductive layers of the stack become available for contacting said layers by via connections (5,8,35,60-63,70-72) of the next level of the interconnect structure. In this way, a circuit comprising multiple parallel capacitors can be realized, which significantly increases the capacitance of the overall assembly. The method of the invention includes the deposition of a thick dielectric layer (11a) and one or more additional dielectric layers (11a,11b, 11c, 11d) thereon. Openings (30,40,41) are produced in the additional layers before patterning the layers to form the pillars, so that the thicknesses of the additional layers determine the height differences between the pillars. By carefully controlling said thicknesses in relation to the thicknesses of the layers of the capacitor assembly, contacting of the intermediate conductive layers of the stack is enabled.

A device (1) comprising an ovonic threshold switch (2) formed of a mixture consisting of at least 0.90 parts by mole of a composition of three chemical elements consisting of 0.15 to 0.70 parts by mole of one or two chemical elements selected from Si, Ge, and Sn, 0.15 to 0.70 parts by mole of S, and optionally 0.05 to 0.45 parts by mole of one chemical element selected from N, Sb, and P, wherein each of the three chemical elements is present in an amount of at least 0.05 parts by mole, and at most 0.10 parts by mole of chemical elements different from said three chemical elements, wherein the parts by mole of the mixture add up to 1.00.

A charge sensor circuitry (110; 210; 310; 410) comprises: a detector element (112; 212; 312; 412) configured to generate a charge signal at an internal node (114; 214; 314; 414); wherein the charge sensor circuitry comprises a first transistor (118; 218; 318; 418) comprising a gate (122; 222; 322; 422) for receiving a first control signal and at least one second transistor (124, 126; 224, 226; 324; 424) comprising a first gate (128; 228; 328; 428) connected to the internal node and a second gate (130; 230; 330; 430) for receiving a second control signal; wherein the charge sensor circuitry is configured to, in a first mode, output a first output signal through the first transistor; wherein the charge sensor circuitry is configured to, in a second mode, reset the internal node through the first transistor and output a second output signal through the at least one second transistor.

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