imec Patente

The disclosure relates to an integrated photonic chip (10) for optical coupling. The photonic chip comprises a substrate (11), a spot size converter (12) formed on a frontside surface of the substrate (11), a mirror (13) formed on the frontside surface of the substrate, and a meta-lens (14) formed in or on a backside surface of the substrate (11). The spot size converter (12) enlarges a diameter of a light beam in the photonic chip (10) from a smaller mode size to a larger mode size. The mirror receives the larger mode size light beam (15a) from the spot size converter (12), and reflects the light beam at an angle into the substrate. The meta-lens collimates the light beam (15b) reflected by the mirror and expanded when passing through the substrate, and outputs the collimated light beam (15c) towards the optical device.

A layer (28) is produced on an etch stop layer (27) formed on a support substrate. The layer is patterned by forming at least one opening (30) having upright sidewalls through the full thickness of the layer. The opening is enlarged by a sequence of directional etch steps wherein the angle of incidence of the applied plasma beam (8) is increased at every subsequent step compared to the previous step, so that the plasma beam impinges on the full height of the sidewall of the opening (30) or enlarged opening (31) at every step. Subsequent directional etch steps can be performed in the same scanning direction at each step, or the scanning direction can be changed at every step or combinations of equal and differing scanning directions can be applied, enabling thereby to obtain various shapes of pattern features. The adjustment of the angle of incidence enables a higher etch rate in the scanning direction and thereby a higher obtainable elongation compared to methods wherein repeated directional etch steps are performed applying he same angle of incidence at each step.

A stack of alternatingly applied etch stop layers (27) and mask layers (28) is produced on a target layer (25) present on a support substrate (26). The target layer is to be patterned according to a pattern comprising parallel line features (34,34'). The top mask layer is patterned according to a pattern of openings (30) and thereafter these openings are elongated by directional etching relative to the etch stop layer, to form a pattern of elongated openings (31,31'). This pattern is transferred to the subsequent mask layer (28) and in said subsequent mask layer, the elongated openings are further elongated by directional etching. This sequence is repeated down to the bottom mask layer. In said bottom mask layer, the pattern of openings has been elongated to a set of lines (34,34'), which are then transferred to the target layer. By repeating the elongation process a number of times, the obtainable elongation is increased compared to a process wherein only one directional etch step is applied.

The method comprises the steps of producing a stack of at least two layers (30,31,32) on a support substrate (25), by lithography and anisotropic etching, producing an opening (33) through said stack of at least two layers, and thereafter applying at least a first directional etching process step, using an etch beam configured to remove the material of one or more upper layers (32) of the stack selectively with respect to the layer or layers (30,31) directly underneath said one or more upper layers, to thereby enlarge the opening in the one or more upper layers (32) while essentially maintaining the in-plane dimensions of the opening in the layer or layers (30,31) directly underneath the one or more upper layers (32). The method can be applied to a stack of several layers which can be enlarged stepwise with respect to further underlying layers of the stack. Directional etching can be done in two opposite directions, possibly applying different etch chemistries in the two directions, to thereby enable the creation of complex three-dimensional structures without requiring expensive multiple lithography steps.

A pattern is produced in a die area (25) of a layer (30,33) formed on a support substrate (32) by at least two process sequences, each comprising a lithography step and an etch step, performed in adjacent subportions of the die area. One or more parallel line shaped features (28) of the pattern extend from the first subportion (25a) of the die area to the second subportion (25b), i.e. across the border (27) between the die areas. Mutually aligned and spaced apart first and second parts of the line features are printed in the respective process sequence steps and transferred to the layer in the form of negative or positive pattern features in the patterned layer, i.e. in the form of trenches (28'a,28'b) in the layer or in the form of lines separated by mutually aligned trenches (37a;37b). In either case, directional etching is thereafter applied to stretch the aligned trenches and thereby obtain the desired line features (28) extending from one subportion of the die area to the other subportion.

An imaging system (100) for medical imaging is provided. The imaging system comprises at least one training device (101), and at least one imaging device (102) operably coupled to the at least one training device (101), wherein the at least one imaging device (102) being configured to be attached to the skin of a person at a predefined location. In this regard, the at least one imaging device (102), in combination with the at least one training device (101), is configured to generate a first set of images corresponding to the predefined location, whereby the at least one training device (101) is configured to generate training data corresponding to the predefined location based on the first set of images. Furthermore, the at least one imaging device (102) is further configured to exclusively generate a second set of images corresponding to the predefined location based on the training data.

In an aspect there is provided a computer-implemented method for designing an IC comprising CFET devices. The method comprises obtaining a functional description of the integrated circuit, and generating, based on the functional description, a layout of the integrated circuit. The layout defines first and second cell rows extending in parallel in a horizontal direction of the layout, and having equal row heights in a vertical direction of the layout. Generating the layout comprises placing first and second cells of a standard cell library in the layout. Each cell has a cell height equal to the row height, and comprises first and second cell edges extending in parallel in the horizontal direction. Each cell further comprises at least one CFET device having an active pattern extending in the horizontal direction. Each cell further comprises at least one local interconnect (LI) disposed on the second cell edge and configured to connect to a top and/or bottom S/D of a CFET device of the cell. The first and second cells are placed in the first and second cell rows, respectively, such that: the first cell edge of the first cell aligns with a first row boundary, the first cell edge of the second cell aligns with a second row boundary, and the second cell edges of the first and second cells align with and abut each other along a third row boundary between the first and second cell rows. The placement of the first and second cells is constrained such that the local interconnects of the first and second cells do not overlap.

The invention relates to a bicelle entity comprising a bicelle structure with a rim and first and second amphiphilic compounds, the first having a longer hydrophobic chain, and at least one extension configured to bind a DNA origami envelope or its extension. It further relates to a DNA origami envelope adapted for such binding and to a complex formed by their assembly. A kit comprising the bicelle entity and the DNA origami envelope is also provided. The invention additionally concerns a hybrid pore device incorporating the complex with a solid-state pore. Methods are disclosed for manufacturing the complex by assembling the bicelle entity and DNA origami envelope, and for producing the hybrid pore device by integrating the complex with the solid-state pore.

In a first aspect, the present invention relates to a gas diffusion electrode (15) for electrochemical gas conversion, comprising: i) a porous solid structure (20), comprising a network (30) formed of a plurality of interconnected electrically conductive wires, and a catalytic surface (32) for catalysing the electrochemical gas conversion, said catalytic surface (32) being a surface of the network (30) as such or of a catalyst (31) coating the network (30); and ii) an electrolyte (50) in the porous solid structure (20) and in contact with the catalytic surface (32); wherein-in operation-at least one side of the porous solid structure (20) is directly exposed to a gas flow comprising the gas to be converted (60), or indirectly exposed to said gas flow through a diffusion layer having a thickness of 10 µm or less, preferably 1 µm or less.

A method for screening entities with different characteristics for their effect on biological cells of a biological cellular material, comprising: laterally constraining said entities having different characteristics in different locations of said biological cellular material, thereby preventing mixing of said entities having different characteristics; applying a transfection activation field to said different locations to allow said entities to be delivered into said biological cells, thereby allowing said entities to have an effect on said biological cells; and detecting said effect.

A device for delivering charged entities into biological cells of a biological cellular material, comprising a microelectrode array for supporting the biological cellular material, the microelectrode array comprising individually addressable electrodes made of an electrically-conductive CMOS-compatible material having an oxide top layer, and the charged entities electrostatically coupled to the oxide top layer. The oxide top layer may be a native oxide top layer. The charged entities can be negatively charged entities electrostatically attached to positively charged carriers directly attached to the oxide top layer, or positively charged entities encapsulated in a negatively charged carrier electrostatically coupled to the native oxide top layer. The electrically-conductive CMOS-compatible material can be a metal, metal nitride, or metal oxide. Charged entities differing in their characteristics may be electrostatically coupled to distinct electrodes of the microelectrode.

A method for identifying biomarkers of a health condition, comprising: providing a first neuronal circuit with neuronal cells from a first individual organism on a multi-electrode array, applying stimuli to the circuit, obtaining electrophysiological recordings, deriving cell-level and/or circuit-level features from the recordings, associating derived features with presence or absence of the health condition, comparing associated data with reference data, and determining if reference features or derived features are biomarkers for the condition.

A microfluidic device (100) comprising: a monolithic semiconductor substrate (10) with thermal conductivity ks; one or more heaters (20) on its top surface, each with a heating element (21); a thermal insulation layer (40) between the heaters (20) and the substrate (10), with thermal conductivity ki at least 50 times smaller than ks; and one or more liquid cooling units (30) with cooling fins (31) on the substrate's bottom surface. Each fin (31) has an extremity (32) within 100 µm of a heating element (21). A cover (60) encloses the cooling units (30), forming cooling channels (61) and including inlet (62) and outlet (63) ports for liquid circulation.

Disclosed is a two-electrode device, such as a Josephson junction or a capacitor, comprising top and bottom electrodes (18, 27) formed of superconducting NbTiN which are separated by a non-superconducting interlayer (17), wherein the bottom electrode is larger than the interlayer and the top electrode. The electrodes and the interlayer are formed by two separate patterning steps and embedded in an enveloping dielectric material (25, 28, 35) that is subsequently planarized by a first CMP stopping on the upper surface of the top electrode (18), thereby forming a first planarized surface (36). Thereafter, a via opening (39) is formed, exposing the upper surface of the bottom electrode (27), filled with an electrically conductive material (40), and planarized by a second CMP. Wiring conductors (57, 58) are then formed on the second planarized surface (36').

A device (100) for analysis of a test object (10) using photo-acoustic effect comprises: an optical arrangement (102) configured to output spatially separated light comprising a plurality of wavelengths, wherein light of different wavelengths of the plurality of wavelengths is separated into different spatial directions; and a spatial light modulator (130) configured to receive the spatially separated light, wherein the spatial light modulator (130) comprises a plurality of individually controllable regions (132), wherein each individually controllable region (132) is configured to receive a portion of the spatially separated light for associating each individually controllable region (132) with a specific wavelength of the plurality of wavelengths, wherein each individually controllable region (132) is configured to modulate the portion of the spatially separated light with a modulation frequency for generating modulated light for inducing a photo-acoustic effect in the test object.

A hardware random number generator (HW-RNG) for drawing samples from a multivariate target distribution through simulation of a Markov chain is disclosed. The HW-RNG (100) has a pipeline architecture operating in cycles. The HW-RNG comprises sets of p-bit devices (112-1; 112-2; 112-N), a programming unit (150) to program the sets of p-bit devices according to a corresponding set of adaptive proposal distributions, selection circuitry (121) to select one of the sets of p-bit devices, a sampling circuit (130) configured to produce a candidate sample from the proposal distribution associated with a selected one of the sets of p-bit devices, and a scheduling unit (140). The scheduling unit (140) is configured to accept the candidate sample with an acceptance probability, and recompute at least one of the proposal distributions that is conditionally dependent on the accepted candidate sample. A programming phase for each set of p-bit devices lasts for x cycles, and there are N > x sets of p-bit devices.

The present disclosure relates to a semiconductor structure for a 3D DRAM comprising one 1T1C memory cell architecture and vertical bit lines. The semiconductor structure comprises a stack of semiconductor layers and dielectric layers alternatingly arranged along a first axis. Further, a first and second pillar of memory cells arranged displaced along a second axis and extending along the first axis through the stack. Each memory cell comprises a part of one of the semiconductor layers, and one transistor structure and one capacitor with a semiconductor channel and a metal gate that at least partly surrounds the semiconductor channel. The metal gates of memory cells in the same pillar are isolated from each other, and metal gates of memory cells that comprise parts of the same semiconductor layer form an integral metal structure.

A method (1000) for use in millimeter-wave beamforming comprises acquiring (1004) a direction of a first beam (103) and a direction of a second beam (105); selecting (1008) an analog beamforming profile based on an angular separation between said first beam (103) and said second beam (105); and communicating (1010) through said first beam (103) and said second beam (105) according to the selected analog beamforming profile.

A semiconductor device (100) for controlling a current flowing between a source terminal (102) and a drain terminal (104), as well as a method for forming such a device, is disclosed. The semiconductor device is formed from a layer stack of GaN layers, in which a vertical junction field-effect transistor, JFET, structure (120) and a lateral high electron mobility transistor, HEMT, structure (130) is provided to control the current.

A programmable processing unit, method of operating a processing unit, and a computer-readable storage medium are provided. The programmable processing unit comprises a plurality of vector portions, providing registers and vector operation units, and a controller. The controller comprises control logic configured to obtain an instruction involving vector operations and invoke a plurality of threads to execute the instruction on respective vector input data. At least one of the plurality of threads executes a vector operation on respective vector input data using the plurality of vector portions.

A Single Instruction Multiple Threads (SIMT) processor core comprising: (a) a configurable dataflow backend operative to support subword parallelism for execution of mixed-precision arithmetic operations, wherein the backend includes multiple dataflow network stages, each dataflow network stage including one or more functional units configurable to process multiple subwords within a register in parallel; (b) a configuration memory storing configuration data defining operational configurations of the dataflow network stages in the backend, wherein the configuration memory is accessible via a configuration index mechanism operative to select configuration data from the configuration memory to control the dataflow network stages in the backend, and wherein the configuration index mechanism is configured for enabling the dataflow backend to support multiple variations of mixed-precision arithmetic operations without requiring dedicated instructions for each variation.

There is provided a nearfield beam shaping device. The device comprises a linear transformer comprising: an input for receiving a light beam; a plurality of optical gates; a plurality of single-mode waveguides. The optical gates distribute the power of the light into portions, each portion being distributed to a respective single-mode waveguide. The optical gates provide control of phase of the light in the single-mode waveguides. The device comprises a mode transformer comprising: a plurality of mode transformer inputs, each being connected to a respective single-mode waveguide; a multimode waveguide, the mode transformer inputs being coupled to the multimode waveguide for exciting a plurality of spatial modes therein; and an output for outcoupling the plurality of modes from the mode transformer. The device controls, based on at least the control of the phase of the portions of light in the single-mode waveguides, the relationship between the modes in the multimode waveguide for controlling the nearfield beam shape of an output light beam based on the plurality of modes outcoupled from the mode transformer.

A hardware random number generator (HW-RNG) and related method are disclosed. The HW-RNG comprises a sample generation stage, adapted to produce primary samples from a plurality of primitive probability distributions, a sample processing stage and a control unit. The sample generation stage includes sets of programmable p-bit devices, a programming unit to adjust the mean values for each set of p-bit devices, and a distinct sampling circuit for each set of p-bit devices. The sample processing stage comprises function logic blocks and selection circuitry configured to route at least one subset of the primary samples to a corresponding function logic block. The control unit is configured to obtain information relating to a composition of basis distributions representative of a target distribution, instruct the function logic block to perform at least arithmetic operation identified by the information, instruct the programming unit to program the sets of p-bit devices according to the composition of basis distributions, and generate the select signal to operatively couple the function logic block to sampling circuits that produce primary samples of random variables defined by the composition of basis distributions.

A processor core (1) of the SIMT type and a related method of operation are disclosed. The processor core comprises frontend circuitry (10), a plurality of lanes (20a-f), a multi-banked and arbitration-free scratchpad memory (40), and an interconnect (50) to couple active ones of the plurality of lanes to different ones of the scratchpad memory banks. There are at least as many banks as lanes in the processor core. Each lane comprises a thread-private register file (21a-f) and address generation logic (22a-f) to independently calculate an effective address of an operand within the scratchpad memory. An execution pipeline of the processor core, associated with the thread-parallel execution of vector memory instructions, comprises at least the address generation logic of the different lanes, the interconnect, and the different banks as pipeline components. The processor core is implemented as a stack of dies (2a, 2b) including the frontend circuitry and the plurality of lanes on a first die (2a) and the scratchpad memory on a second die (2b).

A method for preparing a plurality of optical structures (120) for transfer printing is provided, a method for transfer printing, an assembly of optical structures (320) for transfer printing, and an optoelectronic device comprising at least one of the plurality of optical structures (120) is provided. The method for preparing the plurality of optical structures (120) for transfer printing comprises: obtaining an assembling structure (110) comprising an optical material, wherein the assembling structure (110) comprises a pattern in the optical material, the pattern comprising trenches (130) at a first side (112) of the assembling structure (110) for defining the plurality of optical structures (120), each of the plurality of optical structures (120) comprising an interface surface (122) in the optical material, the interface surface (122) being arranged at the first side of the assembling structure (110); bonding the assembling structure (110) to a temporary bonding layer (140) and a temporary carrier layer (150), wherein the interface surface (122) and the trenches (130) faces the temporary bonding layer (140) and the temporary carrier layer (150), the temporary bonding layer (140) being arranged between the assembling structure (110) and the temporary carrier layer (150); and removing a portion of the assembling structure (110) in order to form and separate the plurality of optical structures (120), wherein the plurality of optical structures (120) are defined for transfer printing from the temporary carrier layer (150).

In an aspect there is provided a 3D IC, comprising:a stack of device tiers comprising a first and a second device tier;a data processing circuit comprising a set of launch and capture circuits, and a set of processing stages,wherein each processing circuit is connected between a launch circuit and a capture circuit,wherein the data processing circuit is partitioned between the first and second device tiers such that the set of launch and capture circuits is arranged in the first device tier and the set of processing stages is arranged in the second device tier.

According to an aspect, there is provided a 3D IC device comprising: a first semiconductor device tier comprising a first set of active devices; a second semiconductor device tier comprising a second set of active devices; a clock distribution network comprising a plurality of clock signal routing interconnects arranged in an interconnect structure arranged at a side of the first semiconductor device tier facing the second semiconductor device tier; and a logic circuit comprising a plurality of registers, each register comprising first active devices arranged along a data path of the register and second active devices arranged along a clock path of the register, wherein the first active devices are comprised in the first set of active devices of the first semiconductor device tier, and wherein the second active devices are comprised in the second set of active devices of the second semiconductor device tier and connected to the clock distribution network to receive a clock signal.

According to an aspect, there is provided a 3D IC device comprising:a first semiconductor device tier comprising a first set of active devices;a second semiconductor device tier comprising a second set of active devices;a clocked circuit comprising first active devices comprised in the first set of active devices of the first semiconductor device tier; anda clock distribution network comprising a plurality of clock signal routing interconnects arranged in an interconnect structure arranged at a side of the first semiconductor device tier facing the second semiconductor device tier, and a set of active clock devices formed by second active devices comprised in the second set of active devices of the second semiconductor device tier;wherein the clocked circuit is connected to the clock distribution network to receive a clock signal

Example embodiments relate to a computer-implemented method for reducing self-interference (130) from a transmitter array (220, 250) at a receiver array (230, 260), the computer-implemented method comprising: generating (201) a set of beamforming antenna pairs (210) by selecting at least two non-identical antenna pairs (214, 215) from transmitter antennas (221 - 223) within the transmitter array (220) or from receiver antennas (261, 262, 263) within the receiver array (260); determining (202) a null space of the self-interference (217) at the receiver array (230, 260) comprising null space vectors (216) of the respective beamforming antenna pairs (211 - 213); and determining (203) beamforming coefficients (218) for the respective antennas within the set of beamforming antenna pairs (210) that reduce self-interference at the receiver array based on a linear combination (219) of the null space vectors (216) of the respective beamforming antenna pairs (211 - 213).

The present invention provides a complementary metal-oxide-semiconductor (CMOS) field effect device comprising a substrate; a first n-doped S/D region and a second n-doped S/D region; a first p-doped S/D region and a second p-doped S/D region; a first channel layer arranged above the substrate, the first channel layer comprising: a first sub-layer and a second sub-layer; wherein the first and second n-doped S/D regions are arranged at a first lateral side of the first channel layer, and the first and second p-doped S/D regions are arranged at a second lateral side of the first channel layer, the second lateral side being opposite to the first lateral side; wherein a conduction band edge of the first sub-layer has an energy below a conduction band edge of the second sub-layer; and wherein a valence band edge of the first sub-layer has an energy below a valence band edge of the second sub-layer; and a gate structure abutting the first and second sublayers of the first channel layer.

A Gallium-Nitride inverter is disclosed using only n-type enhancement mode transistors, thereby achieving Direct-Coupled-FET (DCFL) logic.

The invention relates to a system (100) for generating multiple probability streams with varying probabilities for stream processing applications. The system comprises at least one probabilistic bit (110) configured to produce a fixed probability output and a digital logic circuit (120) designed to process the outputs from the probabilistic bit. The digital logic circuit performs logic operations to transform the fixed probability outputs into multiple streams with different probabilities. This approach reduces the complexity associated with analog control of probabilistic bits by shifting the probability adjustment to the digital domain. The system enables efficient and scalable probability stream generation suitable for applications such as stochastic computing, bit stream computing, and neural networks. Its versatility and reduced hardware requirements make it an ideal solution for error-tolerant stream processing tasks, providing a balance between accuracy, speed, and implementation simplicity.

A device (100; 200; 300) for Fourier Transform spectroscopy comprises: a first light propagating unit (120; 220; 320) receiving a first portion of a light signal and being configured to couple out fractions of the first portion by a sequence of first out-coupling elements (124; 224; 324) with a remaining fraction of the first portion continuing propagation along the first waveguide (122; 222; 322); a second light propagating unit (130; 230; 330) receiving a second portion of the light signal and being configured to couple out fractions of the second portion by a sequence of second out-coupling elements (132; 232; 332) with a remaining fraction of the second portion of the light signal continuing propagation along the second waveguide (132; 232; 332); wherein optical path lengths between sequential out-coupling elements are different in the second waveguide (132; 232; 332) and the first waveguide (122; 232; 332).

A reservoir computing method and related system. The method comprises providing a pulse wave representation of a reservoir input and a MOSFET-based compute node of a reservoir computing system. A body terminal of the MOSFET is configured to apply a bias signal to the body region. The MOSFET is operable in floating mode in the absence of the bias signal. The MOSFET displays a history-dependent threshold voltage when driven by input pulses in floating mode. The method further includes removing the bias signal from the body terminal; applying input pulses to a gate terminal of the MOSFET, thus causing history-dependent variations in the threshold voltage; and acquiring an output sequence related to the compute node while the MOSFET threshold voltage is varying, by repeatedly applying readout pulses to the gate terminal of the MOSFET and simultaneously detecting a current through a channel region of the MOSFET.

A magnetic memory cell (100) includes a magnetic memory element (110) with at least one magnetic layer (111), configured to store information in distinct magnetization states. The magnetic layer (111) generates a stray magnetic field corresponding to its magnetization state. A magnetic field detection device (120) is positioned in proximity to the magnetic memory element (110) to detect variations in the stray magnetic field. The detection device (120) comprises a magnetostrictive (121) and piezoelectric (122) or a piezomagnetic (121) and piezoelectric (122) layer assembly. The magnetostrictive (121) or piezomagnetic (121) layer undergoes mechanical deformation in response to stray field changes, while the piezoelectric layer (122) generates an electrical signal representing the stored information. A writing mechanism (130) is configured to alter the magnetization state of the magnetic layer (111), enabling reliable data storage and retrieval.

The invention is related to a micro-electronic component comprising superconducting digital logic circuitry, including at least one capacitor that comprises a bottom and top electrode (6',8') formed of superconducting NbTiN, and a dielectric interlayer (7') formed of orthorhombic HZO. A method for producing the capacitor includes method steps for producing of NbTiN electrodes defined by atomic concentrations of its constituent elements which enable superconductivity as well as the formation of HZO in the orthorhombic phase that remains stable throughout the sequence of method steps for producing the capacitor. The invention thereby enables producing capacitors for integration in an SDL circuit, for example to be used for the power supply in the circuit, which exhibit superior electrical performance combined with advanced scalability to nanosized dimensions.

The present invention provides a method for forming a semiconductor device (100), comprising: providing a substrate (102) having a frontside (102a) and a backside (102b); forming a fin (104) on the frontside (102a), the fin (104) comprising a fin base (105), the fin (104) extending across a gate zone (150) and across a source/drain zone (160); forming gate spacers (125) in the gate zone (150), the gate spacers (125) comprising a second dielectric material (108b); forming an interlayer dielectric layer (166) in the source/drain zone (160), the interlayer dielectric layer (166) comprising a third dielectric material (108c); depositing a bottom dielectric layer (156), the bottom dielectric layer (156) comprising a fourth dielectric material (108d); wherein the second dielectric material (108b), the third dielectric material (108c), and the fourth dielectric material (108d) comprise different materials; removing the substrate (102), wherein a backside surface exposes the second dielectric material (108b), the third dielectric material (108c), and the fourth dielectric material (108d).

In an aspect there is provided a semiconductor device comprising:a first and second power rail structure extending in parallel, each comprising a bottom power rail and a top power rail arranged above the bottom power rail;a row of local interconnects arranged between and extending in parallel to the first and second rows of CFET devices;a first and second row of complementary field-effect transistor, CFET, devices extending in parallel to the first and second power rail structures, wherein the first row of CFET devices is arranged between the first power rail structure and the row of local interconnects, and the second row of CFET devices is arranged between the second power rail structure and the row of local interconnects;a logic cell comprisingat least one CFET device of the first row of CFET devices configured to implement a first logic gate, and a first local interconnect of the row of local interconnects configured to interconnect a top and bottom source/drain, S/D, of a first CFET device of the at least one CFET device of the first row of CFET devices; andat least one CFET device of the second row of CFET devices configured to implement a second logic gate, and a second local interconnect of the row of local interconnects configured to interconnect a top and bottom S/D of a second CFET device of the at least one CFET device of the second row of CFET devices,wherein the first logic gate is connected to first input and output pins of the logic cell and the second logic gate is connected to second input and output pins of the logic cell, andwherein the first power rail structure is configured to power the first logic gate and the second power rail structure is configured to power the second logic gate.

A method for producing a semiconductor structure (100) is provided. The method comprises: providing (12) a semiconductor fin (110) on a substrate (102), the semiconductor fin (110) comprising a first side surface (111), a second side surface (112) opposing the first side surface (111), and a top surface (113), wherein a mask (120) covers the top surface (113) of the semiconductor fin (110); exposing (14) a portion (114) of the top surface (113) of the semiconductor fin (110) by removing (15) a portion (124) of the mask (120), the exposed portion (114) of the top surface (113) and the first side surface (111) forming an exposed top corner (130) of the semiconductor fin (110); rounding (16) the exposed top corner (130) of the semiconductor fin (110) by oxidizing (17) the exposed portion (114) of the top surface (113) and the first side surface (111).

A system (100) for localization of an anatomical part in a subject comprises: an array of ultrasound transducers (110); a control unit (120) configured to activate a selected subset of at least one ultrasound transducer (110) for controlling the subset to assume a localization mode, wherein the at least one ultrasound transducer (110) is configured to transmit pulse(s) of ultrasound signals and detect the reflected pulse(s) for forming pulse echo data representing an ultrasound response for each pulse as a function of a time delay, wherein the control unit (120) is further configured to sequentially activate different selected subsets; a processing unit (130) configured to analyze the pulse echo data in relation to a characteristic pattern, and to identify one or more ultrasound transducers (110) being located to acquire pulse echo data representing the anatomical part for determining a location of the anatomical part in the subject.