Infineon Technologies Austria

A mechanism for controlling current flow through conductive elements for a particle trapping device. A control arrangement is configured to control the operation of a switch arrangement to control the current flow between an input electrical interface and return electrical interface, via the conductive elements, to remain substantially constant, even whilst switching which conductive elements conduct the current.

An ion trap device includes a dielectric substrate and a via hole extending through the dielectric substrate from a first main surface of the dielectric substrate to a second main surface of the dielectric substrate. The ion trap device further includes an electrically conductive etch stop layer arranged on the first main surface of the dielectric substrate, wherein the etch stop layer covers the via hole. The ion trap device further includes a metal layer of an ion trap at least partially arranged on the etch stop layer and an electrically conductive material arranged in the via hole, wherein the etch stop layer electrically couples the electrically conductive material and the metal layer.

A semiconductor package includes a semiconductor chip having a first surface and a second surface opposite the first surface. The semiconductor chip is a lateral semiconductor device. A plurality of chip pads is arranged on the first surface of the semiconductor chip. The semiconductor chip is mounted on a carrier, wherein the semiconductor chip is bonded to the carrier with the first surface facing the carrier. A heatsink is disposed over the semiconductor chip. The heatsink is bonded to the semiconductor chip with the second surface of the semiconductor chip facing the heatsink. A conductor loop is bonded to the carrier, wherein a loop section of the conductor loop is connected to the heatsink. The conductor is a wire or a ribbon.

Disclosed is a method, The method includes: forming a plurality of trenches (110) in a first surface (101) of a semiconductor body (100) such that the trenches (110) are separated from each other by semiconductor mesa regions (120); and forming a channel region (13) of a first doping type in each of the mesa regions (120). Forming the channel region (13) includes implanting first type do-pant atoms at least into a first sidewall (121) of the respective mesa region (120), and implanting the first type dopant atoms into the first sidewall (121) includes at least two implantation processes that are different from each other with regard to at least one process parameter.

The disclosed concepts relate to a matrix transformer comprising a plurality of ferromagnetic legs, a plurality of primary windings, and a plurality of secondary windings. Each secondary winding is wound around each leg a same number of times. For each leg, the sum of the number of turns made by the plurality of primary windings around the respective leg is the same. Further, a total number of turns made by each respective primary winding around the plurality of legs does not equal an integer multiple of the number of legs. As a result, for a given/target number of legs (e.g., due to form-factor requirements), and for a given number of turns of the secondary winding (e.g., only one turn to minimize conduction losses), a greater number of turns ratios between the primary and secondary windings are possible, as the restriction of having the number of turns of each primary winding equal to an integer multiple of the number of legs is removed.

A driver chip configured to drive a gate of a power transistor comprises: a charger part configured to charge a gate of a power transistor, a logic part configured to control the charger part, a feedback loop configured to connect the gate of the power transistor to the logic part, wherein the logic part is configured to determine, using the feedback loop, a time interval it takes for charging a gate voltage up to a predetermined voltage, wherein the driver chip is configured to control a slew rate of a drain-source voltage of the power transistor using a closed-loop control scheme, and wherein the time interval is a feedback parameter of the closed-loop control scheme.

A semiconductor chip comprising a plurality of first transistors and a plurality of second transistors is provided. The plurality of first transistors are configured such that they may be more robust than the second transistors against the application of high fields during turn on, such as those that may be experienced during hard switching. Specifically, the first transistors may have a larger gate to drain spacing, and/or may be designed to have additional barrier, passivation, and/or buffer layers. There is further provided control circuitry that, during turn on, controls the gate terminals of each of the first transistors to allow conduction between the respective drain terminals and source terminals before controlling the gate terminals of each of the second transistors to allow conduction between the respective drain terminals and source terminals. Furthermore, during turn off, the control circuitry controls the gate terminals of each of the second transistors to block conduction between the respective drain terminals and source terminals before controlling the gate terminals of each of the first transistors to block conduction between the respective drain terminals and source terminals. Accordingly, the first transistors and control scheme may ensure that the first and second transistors are collectively robust, whilst second transistors can be designed to suit other needs, such as a smaller footprint, smaller source-drain on resistance, lower cost and reduced complexity of the overall semiconductor chip.

The invention relates to a semiconductor die (1) with a semiconductor body (10), the semiconductor die (1) comprising: a vertical transistor device (20); an additional transistor device (40) comprising a channel region (43.1) configured for a vertical current flow; an isolation trench (60) extending into the semiconductor body (10); an isolation well (70) made of a second doping type; the isolation well (70) being arranged vertically below the additional transistor device (40), the isolation trench (60) being arranged laterally between the additional transistor device (40) and the vertical transistor device (20), wherein the isolation trench (60) extends to a depth (65) which lies vertically between an upper end (70.1) of the isolation well (70) and the second side (10.2) of the semiconductor body (10).

The disclosure relates to a semiconductor die (1) with a semiconductor body (10), the semiconductor die (1) comprising: a vertical transistor device (20) with a first load region (21) and a second load region (22) at opposite sides (10.1, 10.2) of the semiconductor body (10); an additional transistor device (40) with a source region (41) at a first side (10.1) of the semiconductor body (10), a gate trench (45), a body region (47) aside the gate trench (45) and a drain region (42) below the body region (47); an electrical isolation (60) in the semiconductor body (10); a vertical contact element (80) extending from the first side (10.1) into the semiconductor body (10); wherein the electrical isolation (60) is arranged laterally between the vertical transistor device (20) and the additional transistor device (40), and wherein the vertical contact element (80) makes electrical contact to the drain region (42) of the additional transistor device (40) and connects the drain region (42) to the first side (10.1) of the semiconductor body (10).

A method for operating a power converter and a power converter are disclosed. The method includes adjusting a common mode voltage (Vcm) at first and second output nodes (p, n) of a power converter. The power converter includes: a first input node (a) configured to receive a first input voltage (Va), and a second input node (b) configured to receive a second input voltage (Vb); a first intermediate capacitor (21) connected between a first intermediate node (x) and a midpoint (m), and a second intermediate capacitor (22) connected between the midpoint (m) and a second intermediate node (y); a first output capacitor (41) connected between a first output node (p) and the midpoint (m), and a second output capacitor (42) connected between the midpoint (m) and a second output node (q); an input converter (1) coupled to the first input node (a) and configured to provide an intermediate voltage (Vdc) between the first intermediate node (x) and the second intermediate node (y); a first output converter (31) coupled between the first intermediate capacitor (21) and the first output capacitor (41), and a second output converter (32) coupled between the second intermediate capacitor (22) and the second output capacitor (42); and a balancing circuit (5) coupled to the first intermediate capacitor (21) and the second intermediate capacitor (22), wherein the second input node (b) is coupled to the midpoint (m). Adjusting the common mode voltage includes: obtaining a duty cycle (D31, D32) of operation of at least one of the first and second output converters (31, 32); and adjusting a duty cycle (D5) of operation of the balancing circuit (5) dependent on the obtained duty cycle (D31, D32; D3) of the at least one of the first and second output converters (31, 32).