Infineon Technologies Austria Patente

A semiconductor package includes a pre-package, a pre-package carrier on which the pre-package is mounted and an encapsulant embedding the pre-package and the pre-package carrier. The pre-package includes a power transistor chip having a first side and a second side opposite the first side. The power transistor chip is a lateral semiconductor device. A plurality of source load pads and a plurality of drain load pads are arranged at the first side of the power transistor chip. A pre-package body embeds the power transistor chip at least at its first side, the pre-package body comprising a first side facing away from the first side of the power transistor chip. A structured metal layer is disposed over the first side of the pre-package body. The structured metal layer comprises one continuous source load structure and one continuous drain load structure. A pre-package vertical interconnect runs through material of the pre-package body and is configured to connect at least some of the source load pads to the source load structure and at least some of the drain load pads to the drain load structure. The pre-package is mounted on the pre-package carrier with the structured metal layer facing the pre-package carrier.

A transistor device for high voltage and cryogenic applications. The transistor device comprises a drain extension region extending from a drain region towards a source region. The drain extension region is separated from the source region by a body region which is gated by a first gate electrode. The drain extension region increases the separation of the drain region with respect to the source region and the first gate electrode, reducing a risk of source-drain or gate-drain breakdown. A second gate electrode, different to the first gate electrode, is positioned over the drain extension region. A distance between the second gate electrode and the drain region, along a surface of the drain extension region, is no greater than 400 nm. The second gate electrode controls the conductivity of the drain extension region using an applied voltage, enabling the drain extension region to conduct at cryogenic temperatures.

A gate drive circuit for driving at least a first and a second power transistor between switching states, wherein the first and second power transistor are arranged in parallel between a first load node and a second load node, the gate drive circuit comprising: a control signal input node configured to receive a common control signal, temperature input nodes to receive a temperature signals indicative of a temperature of the power transistors, a delay determination unit configured to determine a delay signal comprising at least one of a turn-on delay value and a turn-off delay value based on a comparison of the temperatures of the first and second power transistors, a drive signal generation unit configured to generate a respective drive signals for driving the first and second power transistors based on the common control signal and the delay signal such that a time difference between a turn-on timing of the drive signals corresponds to the turn-on delay value and/or such that a time difference between a turn-off timing of the drive signals corresponds to the turn-off delay value, a first driver stage configured to provide the first drive signal at a first driving node and a second driver stage configured to provide the second drive signal at a second driving node.

The disclosed concepts relate to a power converter comprising a plurality of converter paths. Each converter path comprises an input node, an output node, a first winding, and a second winding. The first winding is connected in series between the input node and the second winding, and the second winding is connected in series between the first winding and the output node. Each converter path is configured to conduct current in a same direction between the input node and the output node. Further, each first winding of the converter paths is inductively coupled to a second winding of a different converter path to form a respective transformer.

The disclosed concepts relate to a power converter comprising a plurality of converter paths, each converter path comprising an input node, an output node, a first winding, and a second winding. The first winding is coupled in series between the input node and the second winding, and the second winding is coupled in series between the first winding and the output node. Each converter path is configured to conduct current in a same direction between the input node and the output node. The power converter further comprises one or more cores. Each winding of each converter path is inductively coupled to a winding of a different converter path by extending through a respective hole of one of the cores thereby forming a respective pair of inductively coupled windings. At least two of the pairs of inductively coupled windings extend through a same core.

The disclosed concepts relate to a power converter comprising a plurality of converter paths, each converter path comprising an input node, an output node, a first winding, and a second winding. The first winding is coupled in series between the input node and the second winding, and the second winding is coupled in series between the first winding and the output node. Each converter path is configured to conduct current in a same direction between the input node and the output node. Each winding of each of the converter paths is inductively coupled to a winding of a different converter path, thereby forming a respective pair of inductively coupled windings. Each of the plurality of converter paths further comprise an additional series inductance.

The disclosed concepts relate to elementary cells for a circular voltage regulator, a circular voltage regulator comprising a plurality of elementary cells, and methods of forming a circular voltage regulator using the elementary cells. Each elementary cell comprises one or more segments, each segment comprising a elementary cell input node configured for connection to a elementary cell output node of a segment, a elementary cell output node configured for connection to a elementary cell input node of a segment, a first half converter path comprising an input node coupled to the elementary cell input node, an output node, and a second winding coupled in series between the input node and the output node, and a second half converter path comprising an input node configured for connection to a respective phase input, an output node coupled to the elementary cell output node, and a first winding coupled in series between the input node and the output node. In some cases, each segment comprises one or more full converter paths, each full converter path comprising an input node configured for connection to a respective phase input, an output node, a first winding, and a second winding, wherein the first winding is coupled in series between the input node and the second winding, and the second winding is coupled in series between the first winding and the output node. The first half converter path, the second half converter path, and the one or more full converter paths are each configured to conduct current in a same direction between the respective input node and the respective output node. The second winding of the first half converter path is inductively coupled to a winding of one of the full converter paths, the first winding of the second half converter path is inductively coupled to a winding of one of the full converter paths, and each remaining winding of the full converter paths is inductively coupled to a remaining winding of a different converter path.

The disclosed concepts relate to the operation of a power converter (i.e., a circular voltage regulator) comprising at least four converter paths. Each converter path comprises an input node, an output node, a first winding, and a second winding, wherein the first winding is coupled in series between the input node and the second winding, and the second winding is coupled in series between the first winding and the output node. Each converter path is configured to conduct current in a same direction between the input node and the output node, and each winding of each of the converter paths is inductively coupled to a winding of a different converter path. Operating said power converter comprises receiving a phase firing sequence describing a sequence of selected converter paths amongst the converter paths, and providing a sequence of firing voltages to input nodes of the converter paths based on the phase firing sequence. At least one consecutive pair of selected converter paths in the phase firing sequence do not comprise windings that are inductively coupled with each other.

A mechanism for controlling current flow through conductive elements for a particle trapping device. A control arrangement is configured to control the operation of a switch arrangement to control the current flow between an input electrical interface and return electrical interface, via the conductive elements, to remain substantially constant, even whilst switching which conductive elements conduct the current.

An ion trap device includes a dielectric substrate and a via hole extending through the dielectric substrate from a first main surface of the dielectric substrate to a second main surface of the dielectric substrate. The ion trap device further includes an electrically conductive etch stop layer arranged on the first main surface of the dielectric substrate, wherein the etch stop layer covers the via hole. The ion trap device further includes a metal layer of an ion trap at least partially arranged on the etch stop layer and an electrically conductive material arranged in the via hole, wherein the etch stop layer electrically couples the electrically conductive material and the metal layer.

A semiconductor package includes a semiconductor chip having a first surface and a second surface opposite the first surface. The semiconductor chip is a lateral semiconductor device. A plurality of chip pads is arranged on the first surface of the semiconductor chip. The semiconductor chip is mounted on a carrier, wherein the semiconductor chip is bonded to the carrier with the first surface facing the carrier. A heatsink is disposed over the semiconductor chip. The heatsink is bonded to the semiconductor chip with the second surface of the semiconductor chip facing the heatsink. A conductor loop is bonded to the carrier, wherein a loop section of the conductor loop is connected to the heatsink. The conductor is a wire or a ribbon.

Disclosed is a method, The method includes: forming a plurality of trenches (110) in a first surface (101) of a semiconductor body (100) such that the trenches (110) are separated from each other by semiconductor mesa regions (120); and forming a channel region (13) of a first doping type in each of the mesa regions (120). Forming the channel region (13) includes implanting first type do-pant atoms at least into a first sidewall (121) of the respective mesa region (120), and implanting the first type dopant atoms into the first sidewall (121) includes at least two implantation processes that are different from each other with regard to at least one process parameter.

The disclosed concepts relate to a matrix transformer comprising a plurality of ferromagnetic legs, a plurality of primary windings, and a plurality of secondary windings. Each secondary winding is wound around each leg a same number of times. For each leg, the sum of the number of turns made by the plurality of primary windings around the respective leg is the same. Further, a total number of turns made by each respective primary winding around the plurality of legs does not equal an integer multiple of the number of legs. As a result, for a given/target number of legs (e.g., due to form-factor requirements), and for a given number of turns of the secondary winding (e.g., only one turn to minimize conduction losses), a greater number of turns ratios between the primary and secondary windings are possible, as the restriction of having the number of turns of each primary winding equal to an integer multiple of the number of legs is removed.

A driver chip configured to drive a gate of a power transistor comprises: a charger part configured to charge a gate of a power transistor, a logic part configured to control the charger part, a feedback loop configured to connect the gate of the power transistor to the logic part, wherein the logic part is configured to determine, using the feedback loop, a time interval it takes for charging a gate voltage up to a predetermined voltage, wherein the driver chip is configured to control a slew rate of a drain-source voltage of the power transistor using a closed-loop control scheme, and wherein the time interval is a feedback parameter of the closed-loop control scheme.

A semiconductor chip comprising a plurality of first transistors and a plurality of second transistors is provided. The plurality of first transistors are configured such that they may be more robust than the second transistors against the application of high fields during turn on, such as those that may be experienced during hard switching. Specifically, the first transistors may have a larger gate to drain spacing, and/or may be designed to have additional barrier, passivation, and/or buffer layers. There is further provided control circuitry that, during turn on, controls the gate terminals of each of the first transistors to allow conduction between the respective drain terminals and source terminals before controlling the gate terminals of each of the second transistors to allow conduction between the respective drain terminals and source terminals. Furthermore, during turn off, the control circuitry controls the gate terminals of each of the second transistors to block conduction between the respective drain terminals and source terminals before controlling the gate terminals of each of the first transistors to block conduction between the respective drain terminals and source terminals. Accordingly, the first transistors and control scheme may ensure that the first and second transistors are collectively robust, whilst second transistors can be designed to suit other needs, such as a smaller footprint, smaller source-drain on resistance, lower cost and reduced complexity of the overall semiconductor chip.

The invention relates to a semiconductor die (1) with a semiconductor body (10), the semiconductor die (1) comprising: a vertical transistor device (20); an additional transistor device (40) comprising a channel region (43.1) configured for a vertical current flow; an isolation trench (60) extending into the semiconductor body (10); an isolation well (70) made of a second doping type; the isolation well (70) being arranged vertically below the additional transistor device (40), the isolation trench (60) being arranged laterally between the additional transistor device (40) and the vertical transistor device (20), wherein the isolation trench (60) extends to a depth (65) which lies vertically between an upper end (70.1) of the isolation well (70) and the second side (10.2) of the semiconductor body (10).

The disclosure relates to a semiconductor die (1) with a semiconductor body (10), the semiconductor die (1) comprising: a vertical transistor device (20) with a first load region (21) and a second load region (22) at opposite sides (10.1, 10.2) of the semiconductor body (10); an additional transistor device (40) with a source region (41) at a first side (10.1) of the semiconductor body (10), a gate trench (45), a body region (47) aside the gate trench (45) and a drain region (42) below the body region (47); an electrical isolation (60) in the semiconductor body (10); a vertical contact element (80) extending from the first side (10.1) into the semiconductor body (10); wherein the electrical isolation (60) is arranged laterally between the vertical transistor device (20) and the additional transistor device (40), and wherein the vertical contact element (80) makes electrical contact to the drain region (42) of the additional transistor device (40) and connects the drain region (42) to the first side (10.1) of the semiconductor body (10).

A method for operating a power converter and a power converter are disclosed. The method includes adjusting a common mode voltage (Vcm) at first and second output nodes (p, n) of a power converter. The power converter includes: a first input node (a) configured to receive a first input voltage (Va), and a second input node (b) configured to receive a second input voltage (Vb); a first intermediate capacitor (21) connected between a first intermediate node (x) and a midpoint (m), and a second intermediate capacitor (22) connected between the midpoint (m) and a second intermediate node (y); a first output capacitor (41) connected between a first output node (p) and the midpoint (m), and a second output capacitor (42) connected between the midpoint (m) and a second output node (q); an input converter (1) coupled to the first input node (a) and configured to provide an intermediate voltage (Vdc) between the first intermediate node (x) and the second intermediate node (y); a first output converter (31) coupled between the first intermediate capacitor (21) and the first output capacitor (41), and a second output converter (32) coupled between the second intermediate capacitor (22) and the second output capacitor (42); and a balancing circuit (5) coupled to the first intermediate capacitor (21) and the second intermediate capacitor (22), wherein the second input node (b) is coupled to the midpoint (m). Adjusting the common mode voltage includes: obtaining a duty cycle (D31, D32) of operation of at least one of the first and second output converters (31, 32); and adjusting a duty cycle (D5) of operation of the balancing circuit (5) dependent on the obtained duty cycle (D31, D32; D3) of the at least one of the first and second output converters (31, 32).

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A cryostat socket for holding an ion trap device mounted on a substrate in a cryostat includes a housing frame provided for pre-assembly in the cryostat. A spring pin insert is arranged in the housing frame. The spring pin insert comprises a base plate and contact pins resiliently received in the base plate. The contact pins are arranged in an array. A housing cover has a receptacle for the substrate, wherein the housing cover, when assembled with the housing frame, exerts a compressive force on the front side of the substrate by which the rear side of the substrate is pressed onto the contact pins.

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In an embodiment, a semiconductor device 100, 100' comprises a main bi-directional switch 10 formed on a semiconductor substrate 2) and comprising first and second gates, a first source electrically connected to a first voltage terminal VS1, a second source electrically connected to a second voltage terminal VS2, and a common drain D and a substrate control circuit 11. The substrate control circuit (11) comprises a first diode SD1 and a second diode SD2, a discharge circuit 12 comprising a first transistor QC1 and a second transistor QC2 connected in a common source configuration to the semiconductor substrate 20, and a gate potential control circuit 13 comprising a third diode QD1 and a fourth diode QD2. The first diode SD1 has a forward voltage Vf₁ and the third diode QD1 has a forward voltage Vf₃, wherein Vf₁ ≥ 1.1 Vf₄ or Vf₁ ≥ 1.2Vf₄ or Vf₁ ≥ 1.5Vf₄ or Vf₁ ≥ 2Vf₄.

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