Micron Technology

Systems, methods, and apparatus related to memory devices that store data. In one approach, a memory device includes at least one memory array having ternary memory cells. A controller stores data in pairs of the ternary cells. Each value in the data is stored by writing a respective pair of cells using a first level of coding. The controller defines a special value and identifies instances of the special value in the data. An additional bit is stored for each identified special value using a second level of coding.

A method, comprising:forming a stack of alternating layers on a substrate, the substrate defining a plane in a first direction and a second direction, and the substrate extending in a third direction orthogonal to the plane, wherein the stack of alternating layers comprises conductive materials and dielectric materials;etching the stack of alternating layers to form a plurality of cavities;depositing a chalcogenide material into a cavity of the plurality of cavities to form a self-selecting storage element that is in contact with a first conductive material of the conductive materials and two dielectric materials of the dielectric materials and that comprises a bulk region comprising the chalcogenide material having a first composition and a sidewall region comprising the chalcogenide material having a second composition that is different than the first composition; anddepositing a second conductive material that contacts the sidewall region of the chalcogenide material, at least a portion of the sidewall region extending between the first conductive material and the second conductive material in the first direction parallel to the plane defined by the substrate.

Memory devices, systems including memory devices, and methods of operating memory devices and systems in which a memory device can include a voltage regulator for adjusting a supply voltage to an output voltage and providing the output voltage to other devices external to the memory device (e.g., other memory devices in the same memory system, processors, graphics chipsets, other logic circuits, expansion cards, etc.). A memory device may comprise one or more external inputs configured to receive a supply voltage having a first voltage level; a voltage regulator configured to receive the supply voltage from the one or more external inputs and to output an output voltage having a second voltage level different from the first voltage level; one or more memories configured to receive the output voltage from the voltage regulator; and one or more external outputs configured to supply the output voltage to one or more connected devices.

A memory device, comprising: a self-selecting memory component comprising a top surface having a first top length and a bottom surface having a first bottom length less than the first top length in a first direction, the top surface having a second top length and the bottom surface having a second bottom length in a second direction, the second direction different than the first direction, wherein the second top length of the top surface is greater than the second top length of the bottom surface in the second direction; top electrode coupled with the top surface of the self-selecting memory component; and a bottom electrode coupled with the bottom surface of the self-selecting memory component and in electronic communication with the top electrode via the self-selecting memory component.

Systems, methods, and apparatuses related to cooperative learning neural networks are described. Cooperative learning neural networks may include neural networks which utilize sensor data received wirelessly from at least one other wireless communication device to train the neural network. For example, cooperative learning neural networks described herein may be used to develop weights which are associated with objects or conditions at one device and which may be transmitted to a second device, where they may be used to train the second device to react to such objects or conditions. The disclosed features may be used in various contexts, including machine-type communication, machine-to-machine communication, device-to-device communication, and the like. The disclosed techniques may be employed in a wireless (e.g., cellular) communication system, which may operate according to various standardized protocols.

An apparatus comprising a memory array including a plurality of memory cells arranged in a plurality of columns and a plurality of rows is provided. The apparatus further comprises circuitry configured to perform an error detection operation on the memory array to determine a raw count of detected errors, to compare the raw count of detected errors to a threshold value to determine an over-threshold amount, to scale the over-threshold amount according to a scaling algorithm to determine a scaled error count, and to store the scaled error count in a user-accessible storage location.

A method, comprising:forming a channel in a sidewall of a material stack, the channel being bounded by a first dielectric layer, a second dielectric layer, and a conductive layer of the material stack;depositing, into the channel over the conductive layer and via a trench by the sidewall of the material stack, a first material associated with a first electrode;depositing, into the channel over the first material and via the trench, a second material associated with a storage element, wherein a first side of the first material is covered by the second material and a first side of the second material is exposed to the trench based at least in part on depositing the second material;depositing, into the channel over the second material and via the trench, a third material associated with a second electrode, wherein the first side of the second material is covered and a first side of the third material is exposed to the trench based at least in part on depositing the third material;forming, through the first, second, and third materials, an opening that exposes a second side of the second material; andreplacing, via the opening, the second material with a chalcogenide material based at least in part on exposing the second side of the second material.

Methods, systems, and devices for memory architectures with ambipolar semiconductor channels are described. A memory device may include multiple conductors that are each associated with a respective activation line of a memory array, and a pillar that extends through the conductors. The pillar may include a semiconductor material extending along a length of the pillar and associated with an ambipolar channel along the length of the pillar. The memory device may also include multiple storage portions each including one or more storage materials (e.g., to store a charge, a dipole polarization, or a combination thereof). Each storage portion may be associated with a respective memory cell of the memory array and may be positioned between a respective one of the conductors and a respective portion of the semiconductor material along the length of the pillar.

Methods, systems, and devices for single etch and pier merge method for cell and comb features are described. One or more pillars and one or more piers for a memory array may be patterned, aligned, and formed in one processing step. For example, the one or more piers and the one or more pillars may be patterned and etched using a pillar shape to form a set of pillar cavities. A first subset of the pillar cavities may be etched such that pairs of adjacent pillar cavities merge to form a pier cavity that is filled with a first material and a liner to form the one or more piers. A second subset of the pillar cavities may be filled with the liner and the first material to form the one or more pillars. Comb edge structures may be formed based on a third subset of the pillar cavities.

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