imec Patente

A device (100; 200; 300; 400) for light detection comprises: an active layer (110; 210; 310; 410) configured to generate electrons in response to incident light; a silicon layer (120; 220; 320; 420) comprising a diode arrangement (122) configured for collection of the electrons generated by the active layer (110; 210; 310; 410); and an interface layer (140; 240; 340; 440) arranged between the active layer (110; 210; 310; 410) and the silicon layer (120; 220; 320; 420), wherein the interface layer (140; 240; 340; 440) is configured to provide an alignment of a conduction band of electrons between an energy level of the active layer (110; 210; 310; 410) and an energy level of the silicon layer (120; 220; 320; 420) for facilitating transport of the generated electrons from the active layer (110; 210; 310; 410) to the silicon layer (120; 220; 320; 420).

In a first aspect, the present invention relates to a method for depositing a layer of metal phosphate (20), comprising: a) providing a working electrode (10) in contact with a solution (30) comprising metal cations and phosphate anions; and b) electrochemically forming the layer of metal phosphate (20) onto the working electrode (10); wherein the layer of metal phosphate (20) comprises a plurality of dome-shaped substructures (21) and the solution (30) further comprises an agent which promotes said dome-shaped substructures (21) being formed such that an average size thereof is reduced.

The present disclosure relates to a method for fabricating a memory device, for example, a ferroelectric memory device. Further, the disclosure relates to a structure suitable for building the memory device. The method of this disclosure comprises a replacement metal gate (RMG) process, wherein sacrificial layers of a stack are replaced with metal layers. The RMG process is performed before a process of forming memory structures in memory holes, which extend through the stack. In this way, the memory structures can be formed with low thermal budget, for instance, at temperatures below 400°C, which is of benefit particularly for ferroelectric layers of memory structures of a ferroelectric memory device.

A memory access method (1600) and a computer implementing the method are disclosed. The method comprises: organizing data to be accessed (1601) in the computer memory as application object; providing a view (1602) on at least one of the application objects present in the computer memory, the view including a view definition expressive of a selection of data elements from one or multiple referenced application objects; compiling the view (1603) into a linked sequence of machine instructions; storing the compiled view (1604) in a view table and assigning a view tag to each row of the view table; in response to a compute core request (1605) for a selected data element expressed through the view, locating and executing the compiled view (1606, 1607) to determine the logical address for and the application object containing the requested data element; calculating the physical address (1610) corresponding to the logical address of the requested data element; accessing the computer memory (1611) at the physical address of the requested data element.

This disclosure relates generally to a ferroelectric field effect transistor (FeFET) device suitable for probabilistic computing. The FeFET devices is usable as tunable probabilistic element in a network. A computing device comprising the network is also proposed. The FeFET device comprising a channel layer comprising an oxide semiconductor material and/or a 2D semiconductor material. The FeFET device further comprises a gate structure on the channel layer, the gate structure comprising a ferroelectric or anti-ferroelectric layer and a gate layer arranged on the ferroelectric or anti-ferroelectric layer. The gate structure is arranged between a source contact and a drain contact, which are additionally arranged on the channel layer.

A device (100) for sensing thermal property and temperature of a test subject comprises: an array of sensors (110); each comprising an electrically conductive structure (112) and being configured for applying an electrical signal to the electrically conductive structure (112) and sensing a resistance and a temperature-induced change in resistance of the electrically conductive structure (112), indicative of temperature and thermal property of the test subject, respectively, wherein the electrically conductive structure (112) is electrically connected between at least one first contact point (114) and at least one second contact point (118); a common contact (130) configured to provide a common electrical connection to the at least one first contact point (114) of each of the sensors (110); and wherein each of the sensors (110) comprises an individual contact (140) configured to provide an individual electrical connection to the at least one second contact point (118) of the sensor (110).

According to an aspect of the present inventive concept there is provided a method for forming a source/drain contact, the method comprising: providing at least one fin (110) on top of a substrate (130), the at least one fin (110) comprising at least a first set of channel layers (111), the at least one fin (110) being arranged between a first and second shallow trench isolation, STI, region (151, 152) extending into the substrate (130); from a frontside (134) of the substrate (130): forming a cavity (136) in the substrate (130) proximate to the at least one fin (110), forming a sacrificial plug (160) in the cavity (136), and forming a source/drain region (170) on top of the sacrificial plug (160), and in contact with the first set of channel layers (111) of the at least one fin (110); and from a backside (135) of the substrate (130): removing a first region (138) of the substrate (130), the first region (138) of the substrate (130) being a region between the first and second STI region (151, 152) and around the sacrificial plug (160), forming a dielectric material (180) between the first and second STI region (151, 152) and around the sacrificial plug (160), and replacing the sacrificial plug (160) with a metal (190) such that the metal (190) is in electrical contact with the source/drain region (170), wherein a bottom level of the cavity (136) is substantially equal to a bottom level of the first and second STI region (151, 152).

Example embodiments relate to a computer-implemented method for determining endurance performance of a subject based on sensor measurements; the computer-implemented method comprising: obtaining (201) workload data measured by at least one workload sensor, comprising a time series (212) of the workload exerted by the subject during one or more physical activities; obtaining (202) heart rate data measured by at least one heart rate sensor, comprising a time series (211) of the heart rate of the subject during the one or more physical activities; selecting (203) time intervals (213 - 219) within the workload data and the heart rate data based on a set of selection criteria (204); for the respective time intervals (213 - 219), determining (205) an average workload (207) and, for a final portion of the respective time intervals (213 - 219), determining (205) an average heart rate (206); and determining (208) at least a portion of a workload-heart rate relationship (221), indicative for the endurance performance of the subject, by fitting a linear equation (224) to the average workloads and the average heart rates (230) of the respective time intervals (213 - 219).

A bit cell (100) is disclosed, comprising a non-non-volatile memory element (110) and a transistor arrangement (120) configured to provide a write signal switching a state of the memory element. A first terminal (111) of the memory element is connected to a bit line (BL), a second terminal (112) of the memory element is connected to a first common source/drain terminal (121) of the transistor arrangement, and a second common source/drain terminal (122) of the transistor arrangement is connected to a source line (SL). The transistor arrangement comprises a stacked complementary transistor pair, wherein a gate (213) of an upper transistor is connected to a first word line (WLN) and wherein a gate (223) of a lower transistor is connected to a second word line (WLP). A memory device comprising an array of such bit cells, as well as a method for controlling a bit cell, are also disclosed.

Example embodiments relate to a computer-implemented method for determining endurance performance of a subject based on sensor measurements; the computer-implemented method comprising: obtaining (201) a training dataset (214) comprising workload data (212) and heart rate data (211) measured, by respectively at least one workload sensor and at least one heart rate sensor, during respective physical activities performed by the subject within a historical window; training (202) a recurrent neural network, RNN (220), based on the training dataset (214); wherein the RNN (220) is configured to determine the heart rate (221) of the subject at an exerted workload (222) considering a historic time series of heart rate data (223) and workload data preceding the exerted workload; and determining (203) at least a portion of a workload-heart rate relationship (263), indicative for the endurance performance of the subject, by feeding one or more fixed workload time series (241, 242, 243) to the trained RNN (220).

The disclosure relates to a computer-implemented method for controlling on-demand service provisioning in a network, wherein the network comprises resources for providing a service. In the method, a service request is intercepted. At least one network function, indicated as a first network function, required for the service associated with the service request is determined. Then, the first network function is instantiated on a resource in the network for executing the service in the network.

The present invention provides a method for forming a semiconductor structure (100), the method comprising: forming a fin (103) comprising a layer stack (110) on a substrate (102), the layer stack (110) comprising: a first sub-stack (120) comprising: at least one channel layer (122) at least one sacrificial layer (124) a dielectric layer (132) on top of the first sub-stack (120) depositing a dummy gate oxide (142) straddling the fin (103), the dummy gate oxide (142) extending over the dielectric layer (132) of the fin (103), forming a dummy gate (150) on top of the dummy gate oxide (142), the dummy gate (150) straddling the fin (103).

The disclosure proposes a wireless acoustic power receiver comprising an acoustic transducer and a corresponding method of operation. The acoustic transducer is configured to: capture a first alternating current (AC) signal with respectively a first and a second electrode; capture a second AC signal with respectively the first electrode at a first phase and the second electrode at a second phase. The first and the second AC signal are respectively based on vibrations of a first and a second vibration mode of a diaphragm that are respectively induced by a first and a second acoustic frequency. The receiver is configured to provide an electrical power of the first AC signal or the second AC signal to a load, and receive a downlink data stream based on and/or provide an uplink data stream by selectively reflecting and modulating the second acoustic frequency or the first acoustic frequency.

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A method for monitoring a monitor material of a process, such as a manufacturing process, comprises: detecting (204) a suspicious particle (122) in a sample of the monitor material using an imaging system (114) configured to image the sample using illumination light from a light source (116) and to detect an interference pattern based on object light having interacted with the sample and reference light of the illumination light; selectively diverting (208) the suspicious particle (122) from a flow of the sample to an analysis flow; activating (210) a nucleic acid test (NAT) device (160), wherein said activating is triggered based on detecting of the suspicious particle (122) in the sample; receiving (214) by the NAT device (160) the analysis flow comprising the suspicious particle (122); and subjecting (220) the suspicious particle (122) to a NAT analysis.Also, an apparatus for monitoring a monitor material is provided.

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A light sensor (100) for spectrally resolved light detection, said light sensor (100) comprises: an upper reflective element (104); a lower reflective element (106); a photo-sensitive element (114) therebetween; a spacer element (108), configured to form the lower reflective element (106) or configured to be arranged between the upper (104) and the lower reflective element (106); wherein the elements form a stack of layers which define a resonance structure (102a, 102b, 102c) between the upper (104) and the lower reflective element (106) for providing a resonance of light; wherein the spacer element (108) comprises at least two different materials (110, 112), a distribution of which is different between different pixels in an array of pixels such that a resonance wavelength is different for different pixels; and wherein for a plurality of pixels, geometrical structures smaller than the resonance wavelength are defined by the at least two different materials (110, 112).

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According to the method of the invention, a trench (10) is formed in a semiconductor layer (1) of a device wafer for the fabrication of ICs, followed by the deposition of a liner (11) on the sidewalls of the trench. The liner is removed from the bottom of the trench, and the trench may be deepened anisotropically to form an extension (12) of the trench. This may be done along the full length of the trench, or locally by applying a mask. An etch process is then applied wherein the semiconductor material is removed outwardly from the extension, thereby creating a cavity (13) that is wider than the trench. The etch process is selective relative to the liner (11), so that the cavity is formed essentially below the liner (11). Then the combined space formed by the trench and the cavity is filled with an electrically conductive material, possibly after forming a second liner (14). This results in the formation of a buried interconnect rail (15) comprising a narrow portion (15a) in the area of the trench and a wider portion (15b) in the area of the cavity. The wider portion may be contacted from the back side of the semiconductor layer by a TSV connection (24), enabling a large contact area between said TSV connection and the buried rail. The selectivity of the etch process applied for forming the cavity (13) results in the formation of the cavity (13) and thereby of the wider rail portion (15b) at a location that is remote from the active devices formed on the front surface of the semiconductor layer (1).

A device (1) comprising an ovonic threshold switch (2) formed of a mixture consisting of at least 0.90 parts by mole of a composition of three or four chemical elements consisting of 0.20 to 0.70 parts by mole of Si, 0.05 to 0.60 parts by mole of Te, and 0.05 to 0.60 parts by mole of S and/or P, and at most 0.10 parts by mole of optional other chemical elements, wherein the parts by mole of the mixture add up to 1.00.

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The disclosure relates to a capacitive memory structure (10), comprising: a substrate (11); a first metallic layer (12) on the substrate; a ferroelectric material layer (13) on the first metallic layer (12); wherein the ferroelectric material layer (13) is electrically excitable to two polarization states, each polarization state representing a memory state of the capacitive memory structure (10). The capacitive memory structure (10) further comprises a second metallic layer (14) on the ferroelectric material layer (13); wherein the first metallic layer (12) and the second metallic layer (14) have different work functions.

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According to an aspect of the present inventive concept there is provided an imaging device for holographic imaging of a sample, the imaging device comprising a light source generating a light beam, a beam splitter splitting the light beam into an object beam along an object beam path and a reference beam along a reference beam path, and a detector.The imaging device defines a sample position.The object beam is propagated through the sample position, and the detector is arranged to prevent non-scattered object light, passing through the sample position without being scattered by the sample, from being incident onto the detector.The reference beam is propagated through the sample position, and the detector is arranged so that non-scattered reference light, passing through the sample position without being scattered by the sample, is incident onto the detector.The detector detects an interference pattern formed by scattered object light, scattered by the sample, and the non-scattered reference light.

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According to an aspect of the present inventive concept there is provided a sensor head for measurement of a biological material, the sensor head comprising: a substrate comprising: a plurality of sensors arranged in a sensor area at a surface of the substrate; electrical conductors connecting the plurality of sensors to contacts, wherein the electrical conductors are extending from the sensor area along the surface of the substrate to the contacts; a cap comprising a protective element for providing protection from the biological material, the protective element comprising: a first surface and a second surface opposite to the first surface; walls extending from the first surface to the second surface, defining an opening through the protective element; wherein the second surface of the protective element, around the walls of the protective element, is sealed to the surface of the substrate at a position between the sensor area and the contacts such that the opening of the protective element is arranged above the sensor area for allowing the plurality of sensors to be exposed to the biological material.