imec Patente

A method for forming a microfluidic device for culturing cells, the method comprising: providing a microfluidic device comprising a first chamber and a second chamber fluidically connected to the first chamber by a first porous structure comprising through holes for allowing fluid to pass through, said first porous structure physically separating the first chamber and the second chamber, wherein each of said chambers has photosensitive inner walls having a first property; and then irradiating the microfluidic device with light to which the photosensitive inner walls are sensitive, in such a way that the first porous structure acts as a mask during irradiation, thereby changing the surface property of the exposed surfaces and imparting a different surface property in the first chamber compared to the second chamber.

This disclosure proposes a reference voltage circuit, which may be used with a temperature sensor of a neural interface. The circuit comprises a first MOS transistor for providing a current to a set of transistors. In the set of transistors, a second MOS transistor generates a first PTAT voltage, a BJT generates a CTAT voltage, and a third MOS transistor generates a second PTAT voltage. The reference voltage is the sum of the first and second PTAT voltage and the CTAT voltage. The first and the third MOS transistor are of the same type of device, and a source-bulk voltage of the third MOS transistor is non-zero. The first PTAT voltage is independent of a threshold voltage of the second MOS transistor, and a dependence of the second PTAT voltage on the threshold voltage of the third MOS transistor is the opposite of a dependence of the CTAT voltage on a threshold voltage of the first MOS transistor.

The present invention relates in an aspect to an integrated circuit device. The integrated circuit device comprises an active device tier and a frontside interconnect structure arranged at a frontside of the active device tier and a backside interconnect structure arranged at a backside of the active device tier. The integrated circuit device comprises a plurality of circuit blocks, and a data communication circuit configured to transfer data between the plurality of circuit circuit blocks. The data communication circuit comprises a plurality of switching circuits. Each circuit circuit block is connected to the data communication circuit by a switching circuit. The data communication circuit further comprises a plurality of data communication channels interconnecting the plurality of switching circuits and comprising a plurality of backside interconnects arranged in one or more interconnect layers of the backside interconnect structure.

According to an aspect of the present inventive concept there is provided a method (1000) for fabricating a semiconductor structure (100), the method comprising: providing (1100) a substrate (110); providing (1200), on top of the substrate (110), a multi-layer stack (200) comprising, sacrificial layers (211, 212, 213, 214, 215) of a first type, sacrificial layers (221, 222, 223) of a second type, and first, second, and third channel layers (201, 202, 203); forming (1300) a first and second ridge (130, 140) from the multi-layer stack (200); and for the first ridge (130): removing (1400) the sacrificial layers (221, 222, 223) of the second type by selective etching, oxidizing (1500) the sacrificial layers (211, 212, 213, 214, 215) of the first type, and removing (1600) the second channel layer (202) by selective etching, wherein the oxidized sacrificial layers (131, 133, 135, 137, 139) protect the substrate (110) and the first and third channel layers (201, 203) from the selective etching step used to remove the second channel layer (202).

A method for producing a semiconductor structure (100) is provided. The method comprises: providing (12) a semiconductor fin (110) on a substrate (102), the semiconductor fin (110) comprising a first side surface (111), a second side surface (112) opposing the first side surface (111), and a top surface (113), wherein a mask (120) covers the top surface (113) of the semiconductor fin (110); exposing (14) a portion (114) of the top surface (113) of the semiconductor fin (110) by removing (15) a portion (124) of the mask (120), the exposed portion (114) of the top surface (113) and the first side surface (111) forming an exposed top corner (130) of the semiconductor fin (110); rounding (16) the exposed top corner (130) of the semiconductor fin (110) by oxidizing (17) the exposed portion (114) of the top surface (113) and the first side surface (111).

A 3D CCD based imager, comprising: a photosensitive layer, comprising a plurality of pixels to perform photoelectric conversion; a CCD gate stack, configured to store and transfer charge; and a readout layer, configured to read out a signal representative of the charge stored in the CCD gate stack. The CCD gate stack comprises: a plurality of gate layers and a plurality of spacer layers, which are alternatingly arranged one on the other along a first direction; a plurality of channels extending in the CCD gate stack along the first direction, for forming a plurality of strings of charge storage capacitors; and a plurality of dielectric layers extending in the CCD gate stack along the first direction, configured to isolate the plurality of channels from the plurality of gate layers.

A Code-Division Multiplexing radar system, comprises: a number NT transmitters, each configured to transmit a radar signal modulated by a unique code sequence, wherein one of the transmitters is configured to have a transmission power higher than the rest transmitters, a number NR receivers, each configured to receive a reflection signal caused by the transmitted radar signals, and reflected by a target, and a controller, configured to: - generate a number N virtual receive elements, for each virtual receive element VXp,q: - to detect the target, - based on the detected target, to generate a reconstructed interference signal ũp,q caused by the radar signals transmitted by the other transmitters except for the qth radar signal, and - to update a virtual receiving signal at said virtual receive element VXp,q based on the reconstructed interference signal x2.

According to an aspect of the present inventive concept there is provided a method for enabling tracking of an object in a flow channel comprising: receiving a first plurality of sequences of images; generating a first map, wherein said generating comprises: tracking the first plurality of training objects; determining movements of the first plurality of training objects; defining a first set of movement vectors; receiving a second plurality of sequences of images; generating a second map, wherein said generating comprises: tracking the second plurality of training objects; determining movements of the second plurality of training objects; defining a second set of movement vectors; generating a tracking map based on the second map; wherein a condition of the flow of liquid in the flow channel or of acquiring of sequences of images is changed between the first plurality of sequences of images and the second plurality of sequences of images.

A device (1) comprising: a first electrode (4) comprising a first electrode material of a type that, if oxidized by an oxidizing agent, is electrically insulating, a second electrode (2) comprising a second electrode material of a type that, if oxidized by said oxidizing agent, is electrically conducting, and a threshold switch layer (3) between the first electrode (4) and the second electrode (2), the threshold switch layer (3) comprising a material being switchable from an electrically insulating state to an electrically conducting state by a voltage between the first (4) and second electrode (2) crossing a threshold voltage, and a first electrode interface (40) between the threshold switch layer (3) and the first electrode (4), and a second electrode interface (20) between the threshold switch layer (3) and the second electrode (2), wherein the device (1) comprises the oxidizing agent suitable for being moveable between the first electrode (4) and the second electrode (2), the threshold switch layer (3) providing a passage for moving the oxidizing agent between the first electrode (4) and the second electrode (2).

In a one aspect, the present invention relates to a cell engineering module (4) for cell engineering target cells (51) in a mixture (5) comprising the target cells (51) and non-target cells (52), comprising: i) a cell monitoring zone (410) for allowing tracking and classifying individual cells (50) in the mixture (5), wherein classifying a cell (50) comprises determining whether the cell (50) is a target cell (51); and ii) an engineering component (42) in the cell monitoring zone (410) for selectively modifying individual cells (50) at one or more engineering sites (420), wherein the target cells (51) and the non-target cells (52) are randomly distributed in the engineering component (42); wherein the engineering component (42) is adapted for-in operation-being controlled so as to selectively modify only target cells tracked to be at one of the engineering sites (420).

A transistor structure for a vertical NAND flash memory device is provided. The transistor structure comprises a semiconductor channel layer, a first auxiliary layer and a second auxiliary layer arranged at two opposite sides of the semiconductor channel layer along a first axis, and each of the first auxiliary layer and the second auxiliary layer comprises a first material having a first relative permittivity, the first relative permittivity being larger than 1 and lower than 3.9. The transistor structure further comprises: a first dielectric layer arranged above the semiconductor channel layer, the first auxiliary layer and the first auxiliary layer along a second axis that is perpendicular to the first axis; a charge storage layer arranged on the first dielectric layer; a second dielectric layer arranged on the charge storage layer; and a gate layer arranged on the second dielectric layer.

A method for manufacturing a co-integrated semiconductor structure (1) from a first (100) and a second (200) layer stack, the first layer stack (100) comprising a channel layer (10) and at least one sub-stack (150) on the channel layer (10), wherein each of the at least one sub-stack (150) comprises a sacrificial layer of a first type (21), a first slender layer (31) on the sacrificial layer of the first type (21), a sacrificial layer of a second type (22) on the first slender layer (31), a second slender layer (32) on the sacrificial layer of the second type (22), a further sacrificial layer of the first type (21) on the second slender layer (32), and a further channel layer (10) on the further sacrificial layer of the first type (21), the second layer stack (200) comprising a channel layer (10) and at least one sub-stack (250) on the channel layer (10), wherein each of the at least one sub-stack (250) comprises a sacrificial layer of the first type (21) and a further channel layer (10, 11) on the sacrificial layer of the first type (21), wherein a separation (S1) between the neighboring channel layers (10) of the first layer stack (100) is larger than a separation (S2) between neighboring channel layers (10) of the second layer stack (200).

A microfluidic device for purification of nucleic acids comprising: at least one microfluidic channel, said channel having a first surface, a second surface opposite the first surface, and connecting surfaces joining the first and second surfaces; a plurality of fixed structures within said channel, said structures being attached to at least one of the first surface or second surface of the channel, collectively occupying at least 95% of the distance between the connecting surfaces, and each structure extending across at least 95% of the distance between the surface to which it is attached and the opposite surface; at least one inlet for introducing a fluid containing nucleic acids or molecular assemblies comprising nucleic acids into the channel; and at least one outlet for collecting purified nucleic acids; wherein said fixed structures comprise a surface capable of reversibly binding either nucleic acids or molecular assemblies comprising nucleic acids.

A method (100) for wafer-scale fabrication of a non-cytotoxic reference electrode for various types of sensors, including electrochemical sensors, biosensors, and other devices used for analyte sensing is provided. The method comprises the steps of forming (101) at least one electrode on a substrate, forming (102) one or more metal or metal oxide layers on top of the at least one electrode, functionalizing (103) the one or more metal or metal oxide layers, providing (104) a membrane on top of the one or more metal or metal oxide layers to confine ions diffused from the one or more metal or metal oxide layers, forming (105) a reservoir on top of the membrane, filling (106) the reservoir with a reference electrolyte, and providing (107) at least one sensor inside the reservoir being in contact with the reference electrolyte to measure a total ion concentration and/or a specific ion concentration and/or a temperature of the reference electrolyte, enabling correction for sensor drift.

A system (100) for synthesizing copolymerized molecules on a substrate (10) includes: a light source (20) emitting exposure light; a programmable light direction unit (30) for redirecting the light in specific patterns; a substrate holder (40); a reagent delivery system (50) for dispensing reagents; and a lateral movement mechanism (60) for generating relative movement between the light direction unit and the substrate holder. A controller (70) controls: i) reagent dispensing; ii) light exposure in a first pattern; iii) relative movement and adjustment of the light direction unit to a second pattern; and iv) subsequent exposure in the second pattern.

A quantum circuit and related manufacturing method are disclosed. The quantum circuit comprises a vertical Josephson junction (1001) formed by a bottom electrode (810) in a first superconducting material layer, a tunnel barrier (830), and a top electrode (820) in a second superconducting material layer. A contact portion (811) and a coupling portion (812) of the bottom electrode are located inside and outside the Josephson junction, respectively. A transmon qubit of the quantum circuit comprises the Josephson junction and a shunt capacitor formed by the top electrode and the contact portion of the bottom electrode as capacitor plates. A readout circuit is capacitively coupled to the bottom electrode through the coupling portion and includes a coupling head (861). The coupling portion is fitted into a recessed portion of the coupling head. The top electrode is configured as a floating electrode, not resistively coupled to the first superconducting material layer.

A method for determining a temperature map (70, 800) at a target resolution of an IC design (10), the method comprising: determining (200) a high-resolution power map (20) and a low-resolution power map (30); determining (400) a low-resolution temperature map (40) corresponding to the low-resolution power map; up-sampling (500) the low-resolution temperature map to the target resolution to obtain an intermediate temperature map (50); and for one or more ROIs: up-sampling (600) the low-resolution power map in the ROI (203) to the first, high resolution to obtain a local intermediate power map in the ROI (303); determining a difference between (601) the local intermediate power map and the high-resolution power map in the ROI (202), thereby obtaining a local differential power map (61) in the first, high resolution for the ROI; and determining (602) a local differential temperature map (62) in the target resolution corresponding to the local differential power map; and combining (700) the local differential temperature map with the intermediate temperature map in the ROI.

A thinned semiconductor substrate (1) is provided having a front end of line (FEOL) portion (2) on its front side. The FEOL portion includes conductive structures (3,40) at the front side of the thinned substrate, which need to be contacted by connections through the substrate. An opening (15) is etched from the back of the thinned substrate, to be filled with a conductive material. The bottom of said opening overlaps at least partially the end surface (14) of the conductive structure to be contacted, and further overlaps one or more portions of semiconductor material of the substrate. According to the invention, etching of the opening continues beyond the end surface into said semiconductor portion(s), to thereby create one or more cavities (27). A first dielectric layer (30) is formed on the sidewalls and bottom of the opening, so that the cavity or cavities are filled with the material of the first layer. This material is then removed everywhere except in the cavity or cavities (27). If necessary, a second dielectric layer (31) may be formed as a liner on the sidewalls and bottom of the opening (15), to be opened up at the bottom by an anisotropic etch to thereby expose said end surface (14), but wherein the dielectric of the first layer remains in the cavity or cavities (27). These dielectric-filled cavities thereby inhibit the formation of shorts between the eventual through-connection (18,43) obtained by filling the opening, and the semiconductor material of the substrate (1)..

This disclosure relates to a comparator circuit and an ADC circuit for a neural interface. The ADC circuit includes the comparator circuit. The comparator circuit comprises a comparator to receive a first and a second signal, and internally amplify the first and the second signal. A bump bias circuit of the comparator circuit receives the amplified first and second signal, and causes the comparator to operate at a higher power level when a difference between the amplified first and second signal is smaller, and at a lower power level when the difference between the amplified first and second signal is larger. The ADC circuit comprises two comparator circuits connected to a first and second switching circuit. A control circuit of the ADC circuit can set a capacitor state of first capacitor pairs of the first switching circuit, and a capacitor state of second capacitors pairs of the second switching circuit, based on outputs of the respective comparator circuit.

A system (100) for performing electromyography (EMG) measurements, the system comprising an EMG unit (110) for collecting electromyography data of a user, the EMG unit (110) comprising a plurality of EMG electrodes (120), one or more other sensors (130) for capturing sensor data related to a motion and/or activity of the user, a sensor data processing unit (140) being programmed for processing the captured sensor data using a muscle activity expectation model (142) for identifying specific muscles used during the motion and/or activity of the user, and the system being adapted for selecting a subset of EMG electrodes from the plurality of EMG electrodes (120), said selecting being based on the identified specific muscles.

The present invention provides a method for forming a gate stack (100) on a semiconductor substrate (102), the method comprising:forming a dielectric interlayer (103) on the semiconductor substrate (102),forming a dipole-forming layer (104) comprising a work function shifting metal and oxygen on top of the dielectric interlayer (103);etching the dipole-forming layer (104) such that a residue (106) of the dipole-forming layer (104) remains on the dielectric interlayer (103), the residue (106) being less than one monolayer of the dipole-forming layer (104), wherein a temperature is kept below 430 °C between said acts of forming the dipole-forming layer (104) and etching the dipole-forming layer (104);depositing a gate dielectric (108); anddepositing a metal gate (110) on the gate dielectric (108).

According to an aspect of the present inventive concept there is provided a device for characterizing objects comprising: a flow channel configured to pass a flow of liquid, wherein: the flow of liquid carries the objects, the flow channel comprises a zone associated with a category, wherein a surface is coated with molecules having an affinity and specificity to the category, whereby the surface forms an object movement modifying (OMM) surface configured to modify the movement of the object by binding and releasing the object; wherein the device is configured to modulate a force exerted on the object; wherein the device is configured to exert a first condition and a second condition on the object, the first condition being adapted to promote the binding of an object belonging to the category to the OMM surface and the second condition being adapted to promote the releasing of an object bound to the OMM surface.

A three-dimensional integrated circuit, comprising a first tier, a second tier, vertically stacked above the first tier, and a memory circuit. The memory circuit comprises a bitcell array disposed in the first tier. The memory circuit also comprises a column peripheral circuit having at least an elongate first portion disposed in the second tier. The memory circuit also includes a row decoder being elongate and disposed in the second tier and extending in a direction parallel to the first portion of the column peripheral circuit.

According to an aspect there is provided a field-effect transistor device (100) comprising: a semiconductor layer (101) of a wide-bandgap semiconductor, the semiconductor layer comprising a source region (102), a drain region (104) and a floating body region (106) between the source region (102) and the drain region (104); a first gate (108) and a second gate (110) arranged along the floating body region (106) of the semiconductor layer (101), wherein the first gate (108) is arranged at a first side (101a) of the semiconductor layer and the second gate is arranged at a second side (102b) of the semiconductor layer (101), opposite the first side (101a); and a charge storage island (114) arranged along the floating body region (106) in contact with the second side (101b) of the semiconductor layer (101) such that the charge storage island (114) is arranged between the floating body region (106) and the second gate (110), wherein the charge storage island (114) is configured to define a potential well for charge carriers attracted from a channel induced in the floating body region (106) during an on-state of the transistor device (100).

A device (100; 200; 300; 400) for light detection comprises: an active layer (110; 210; 310; 410) configured to generate electrons in response to incident light; a silicon layer (120; 220; 320; 420) comprising a diode arrangement (122) configured for collection of the electrons generated by the active layer (110; 210; 310; 410); and an interface layer (140; 240; 340; 440) arranged between the active layer (110; 210; 310; 410) and the silicon layer (120; 220; 320; 420), wherein the interface layer (140; 240; 340; 440) is configured to provide an alignment of a conduction band of electrons between an energy level of the active layer (110; 210; 310; 410) and an energy level of the silicon layer (120; 220; 320; 420) for facilitating transport of the generated electrons from the active layer (110; 210; 310; 410) to the silicon layer (120; 220; 320; 420).

In a first aspect, the present invention relates to a method for depositing a layer of metal phosphate (20), comprising: a) providing a working electrode (10) in contact with a solution (30) comprising metal cations and phosphate anions; and b) electrochemically forming the layer of metal phosphate (20) onto the working electrode (10); wherein the layer of metal phosphate (20) comprises a plurality of dome-shaped substructures (21) and the solution (30) further comprises an agent which promotes said dome-shaped substructures (21) being formed such that an average size thereof is reduced.

The present disclosure relates to a method for fabricating a memory device, for example, a ferroelectric memory device. Further, the disclosure relates to a structure suitable for building the memory device. The method of this disclosure comprises a replacement metal gate (RMG) process, wherein sacrificial layers of a stack are replaced with metal layers. The RMG process is performed before a process of forming memory structures in memory holes, which extend through the stack. In this way, the memory structures can be formed with low thermal budget, for instance, at temperatures below 400°C, which is of benefit particularly for ferroelectric layers of memory structures of a ferroelectric memory device.

This disclosure relates generally to a ferroelectric field effect transistor (FeFET) device suitable for probabilistic computing. The FeFET devices is usable as tunable probabilistic element in a network. A computing device comprising the network is also proposed. The FeFET device comprising a channel layer comprising an oxide semiconductor material and/or a 2D semiconductor material. The FeFET device further comprises a gate structure on the channel layer, the gate structure comprising a ferroelectric or anti-ferroelectric layer and a gate layer arranged on the ferroelectric or anti-ferroelectric layer. The gate structure is arranged between a source contact and a drain contact, which are additionally arranged on the channel layer.

A memory access method (1600) and a computer implementing the method are disclosed. The method comprises: organizing data to be accessed (1601) in the computer memory as application object; providing a view (1602) on at least one of the application objects present in the computer memory, the view including a view definition expressive of a selection of data elements from one or multiple referenced application objects; compiling the view (1603) into a linked sequence of machine instructions; storing the compiled view (1604) in a view table and assigning a view tag to each row of the view table; in response to a compute core request (1605) for a selected data element expressed through the view, locating and executing the compiled view (1606, 1607) to determine the logical address for and the application object containing the requested data element; calculating the physical address (1610) corresponding to the logical address of the requested data element; accessing the computer memory (1611) at the physical address of the requested data element.

A bit cell (100) is disclosed, comprising a non-non-volatile memory element (110) and a transistor arrangement (120) configured to provide a write signal switching a state of the memory element. A first terminal (111) of the memory element is connected to a bit line (BL), a second terminal (112) of the memory element is connected to a first common source/drain terminal (121) of the transistor arrangement, and a second common source/drain terminal (122) of the transistor arrangement is connected to a source line (SL). The transistor arrangement comprises a stacked complementary transistor pair, wherein a gate (213) of an upper transistor is connected to a first word line (WLN) and wherein a gate (223) of a lower transistor is connected to a second word line (WLP). A memory device comprising an array of such bit cells, as well as a method for controlling a bit cell, are also disclosed.

Example embodiments relate to a computer-implemented method for determining endurance performance of a subject based on sensor measurements; the computer-implemented method comprising: obtaining (201) a training dataset (214) comprising workload data (212) and heart rate data (211) measured, by respectively at least one workload sensor and at least one heart rate sensor, during respective physical activities performed by the subject within a historical window; training (202) a recurrent neural network, RNN (220), based on the training dataset (214); wherein the RNN (220) is configured to determine the heart rate (221) of the subject at an exerted workload (222) considering a historic time series of heart rate data (223) and workload data preceding the exerted workload; and determining (203) at least a portion of a workload-heart rate relationship (263), indicative for the endurance performance of the subject, by feeding one or more fixed workload time series (241, 242, 243) to the trained RNN (220).

The disclosure relates to a computer-implemented method for controlling on-demand service provisioning in a network, wherein the network comprises resources for providing a service. In the method, a service request is intercepted. At least one network function, indicated as a first network function, required for the service associated with the service request is determined. Then, the first network function is instantiated on a resource in the network for executing the service in the network.

A device (100) for sensing thermal property and temperature of a test subject comprises: an array of sensors (110); each comprising an electrically conductive structure (112) and being configured for applying an electrical signal to the electrically conductive structure (112) and sensing a resistance and a temperature-induced change in resistance of the electrically conductive structure (112), indicative of temperature and thermal property of the test subject, respectively, wherein the electrically conductive structure (112) is electrically connected between at least one first contact point (114) and at least one second contact point (118); a common contact (130) configured to provide a common electrical connection to the at least one first contact point (114) of each of the sensors (110); and wherein each of the sensors (110) comprises an individual contact (140) configured to provide an individual electrical connection to the at least one second contact point (118) of the sensor (110).

According to an aspect of the present inventive concept there is provided a method for forming a source/drain contact, the method comprising: providing at least one fin (110) on top of a substrate (130), the at least one fin (110) comprising at least a first set of channel layers (111), the at least one fin (110) being arranged between a first and second shallow trench isolation, STI, region (151, 152) extending into the substrate (130); from a frontside (134) of the substrate (130): forming a cavity (136) in the substrate (130) proximate to the at least one fin (110), forming a sacrificial plug (160) in the cavity (136), and forming a source/drain region (170) on top of the sacrificial plug (160), and in contact with the first set of channel layers (111) of the at least one fin (110); and from a backside (135) of the substrate (130): removing a first region (138) of the substrate (130), the first region (138) of the substrate (130) being a region between the first and second STI region (151, 152) and around the sacrificial plug (160), forming a dielectric material (180) between the first and second STI region (151, 152) and around the sacrificial plug (160), and replacing the sacrificial plug (160) with a metal (190) such that the metal (190) is in electrical contact with the source/drain region (170), wherein a bottom level of the cavity (136) is substantially equal to a bottom level of the first and second STI region (151, 152).

Example embodiments relate to a computer-implemented method for determining endurance performance of a subject based on sensor measurements; the computer-implemented method comprising: obtaining (201) workload data measured by at least one workload sensor, comprising a time series (212) of the workload exerted by the subject during one or more physical activities; obtaining (202) heart rate data measured by at least one heart rate sensor, comprising a time series (211) of the heart rate of the subject during the one or more physical activities; selecting (203) time intervals (213 - 219) within the workload data and the heart rate data based on a set of selection criteria (204); for the respective time intervals (213 - 219), determining (205) an average workload (207) and, for a final portion of the respective time intervals (213 - 219), determining (205) an average heart rate (206); and determining (208) at least a portion of a workload-heart rate relationship (221), indicative for the endurance performance of the subject, by fitting a linear equation (224) to the average workloads and the average heart rates (230) of the respective time intervals (213 - 219).

The present invention provides a method for forming a semiconductor structure (100), the method comprising: forming a fin (103) comprising a layer stack (110) on a substrate (102), the layer stack (110) comprising: a first sub-stack (120) comprising: at least one channel layer (122) at least one sacrificial layer (124) a dielectric layer (132) on top of the first sub-stack (120) depositing a dummy gate oxide (142) straddling the fin (103), the dummy gate oxide (142) extending over the dielectric layer (132) of the fin (103), forming a dummy gate (150) on top of the dummy gate oxide (142), the dummy gate (150) straddling the fin (103).

The disclosure proposes a wireless acoustic power receiver comprising an acoustic transducer and a corresponding method of operation. The acoustic transducer is configured to: capture a first alternating current (AC) signal with respectively a first and a second electrode; capture a second AC signal with respectively the first electrode at a first phase and the second electrode at a second phase. The first and the second AC signal are respectively based on vibrations of a first and a second vibration mode of a diaphragm that are respectively induced by a first and a second acoustic frequency. The receiver is configured to provide an electrical power of the first AC signal or the second AC signal to a load, and receive a downlink data stream based on and/or provide an uplink data stream by selectively reflecting and modulating the second acoustic frequency or the first acoustic frequency.

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A method for monitoring a monitor material of a process, such as a manufacturing process, comprises: detecting (204) a suspicious particle (122) in a sample of the monitor material using an imaging system (114) configured to image the sample using illumination light from a light source (116) and to detect an interference pattern based on object light having interacted with the sample and reference light of the illumination light; selectively diverting (208) the suspicious particle (122) from a flow of the sample to an analysis flow; activating (210) a nucleic acid test (NAT) device (160), wherein said activating is triggered based on detecting of the suspicious particle (122) in the sample; receiving (214) by the NAT device (160) the analysis flow comprising the suspicious particle (122); and subjecting (220) the suspicious particle (122) to a NAT analysis.Also, an apparatus for monitoring a monitor material is provided.