imec Patente

A semiconductor device (100) for controlling a current flowing between a source terminal (102) and a drain terminal (104), as well as a method for forming such a device, is disclosed. The semiconductor device is formed from a layer stack of GaN layers, in which a vertical junction field-effect transistor, JFET, structure (120) and a lateral high electron mobility transistor, HEMT, structure (130) is provided to control the current.

In an aspect there is provided a 3D IC, comprising:a stack of device tiers comprising a first and a second device tier;a data processing circuit comprising a set of launch and capture circuits, and a set of processing stages,wherein each processing circuit is connected between a launch circuit and a capture circuit,wherein the data processing circuit is partitioned between the first and second device tiers such that the set of launch and capture circuits is arranged in the first device tier and the set of processing stages is arranged in the second device tier.

According to an aspect, there is provided a 3D IC device comprising: a first semiconductor device tier comprising a first set of active devices; a second semiconductor device tier comprising a second set of active devices; a clock distribution network comprising a plurality of clock signal routing interconnects arranged in an interconnect structure arranged at a side of the first semiconductor device tier facing the second semiconductor device tier; and a logic circuit comprising a plurality of registers, each register comprising first active devices arranged along a data path of the register and second active devices arranged along a clock path of the register, wherein the first active devices are comprised in the first set of active devices of the first semiconductor device tier, and wherein the second active devices are comprised in the second set of active devices of the second semiconductor device tier and connected to the clock distribution network to receive a clock signal.

According to an aspect, there is provided a 3D IC device comprising:a first semiconductor device tier comprising a first set of active devices;a second semiconductor device tier comprising a second set of active devices;a clocked circuit comprising first active devices comprised in the first set of active devices of the first semiconductor device tier; anda clock distribution network comprising a plurality of clock signal routing interconnects arranged in an interconnect structure arranged at a side of the first semiconductor device tier facing the second semiconductor device tier, and a set of active clock devices formed by second active devices comprised in the second set of active devices of the second semiconductor device tier;wherein the clocked circuit is connected to the clock distribution network to receive a clock signal

Example embodiments relate to a computer-implemented method for reducing self-interference (130) from a transmitter array (220, 250) at a receiver array (230, 260), the computer-implemented method comprising: generating (201) a set of beamforming antenna pairs (210) by selecting at least two non-identical antenna pairs (214, 215) from transmitter antennas (221 - 223) within the transmitter array (220) or from receiver antennas (261, 262, 263) within the receiver array (260); determining (202) a null space of the self-interference (217) at the receiver array (230, 260) comprising null space vectors (216) of the respective beamforming antenna pairs (211 - 213); and determining (203) beamforming coefficients (218) for the respective antennas within the set of beamforming antenna pairs (210) that reduce self-interference at the receiver array based on a linear combination (219) of the null space vectors (216) of the respective beamforming antenna pairs (211 - 213).

The present invention provides a complementary metal-oxide-semiconductor (CMOS) field effect device comprising a substrate; a first n-doped S/D region and a second n-doped S/D region; a first p-doped S/D region and a second p-doped S/D region; a first channel layer arranged above the substrate, the first channel layer comprising: a first sub-layer and a second sub-layer; wherein the first and second n-doped S/D regions are arranged at a first lateral side of the first channel layer, and the first and second p-doped S/D regions are arranged at a second lateral side of the first channel layer, the second lateral side being opposite to the first lateral side; wherein a conduction band edge of the first sub-layer has an energy below a conduction band edge of the second sub-layer; and wherein a valence band edge of the first sub-layer has an energy below a valence band edge of the second sub-layer; and a gate structure abutting the first and second sublayers of the first channel layer.

A Gallium-Nitride inverter is disclosed using only n-type enhancement mode transistors, thereby achieving Direct-Coupled-FET (DCFL) logic.

The present invention provides a method for forming a semiconductor device (100), comprising: providing a substrate (102) having a frontside (102a) and a backside (102b); forming a fin (104) on the frontside (102a), the fin (104) comprising a fin base (105), the fin (104) extending across a gate zone (150) and across a source/drain zone (160); forming gate spacers (125) in the gate zone (150), the gate spacers (125) comprising a second dielectric material (108b); forming an interlayer dielectric layer (166) in the source/drain zone (160), the interlayer dielectric layer (166) comprising a third dielectric material (108c); depositing a bottom dielectric layer (156), the bottom dielectric layer (156) comprising a fourth dielectric material (108d); wherein the second dielectric material (108b), the third dielectric material (108c), and the fourth dielectric material (108d) comprise different materials; removing the substrate (102), wherein a backside surface exposes the second dielectric material (108b), the third dielectric material (108c), and the fourth dielectric material (108d).

A magnetic memory cell (100) includes a magnetic memory element (110) with at least one magnetic layer (111), configured to store information in distinct magnetization states. The magnetic layer (111) generates a stray magnetic field corresponding to its magnetization state. A magnetic field detection device (120) is positioned in proximity to the magnetic memory element (110) to detect variations in the stray magnetic field. The detection device (120) comprises a magnetostrictive (121) and piezoelectric (122) or a piezomagnetic (121) and piezoelectric (122) layer assembly. The magnetostrictive (121) or piezomagnetic (121) layer undergoes mechanical deformation in response to stray field changes, while the piezoelectric layer (122) generates an electrical signal representing the stored information. A writing mechanism (130) is configured to alter the magnetization state of the magnetic layer (111), enabling reliable data storage and retrieval.

A reservoir computing method and related system. The method comprises providing a pulse wave representation of a reservoir input and a MOSFET-based compute node of a reservoir computing system. A body terminal of the MOSFET is configured to apply a bias signal to the body region. The MOSFET is operable in floating mode in the absence of the bias signal. The MOSFET displays a history-dependent threshold voltage when driven by input pulses in floating mode. The method further includes removing the bias signal from the body terminal; applying input pulses to a gate terminal of the MOSFET, thus causing history-dependent variations in the threshold voltage; and acquiring an output sequence related to the compute node while the MOSFET threshold voltage is varying, by repeatedly applying readout pulses to the gate terminal of the MOSFET and simultaneously detecting a current through a channel region of the MOSFET.

The invention relates to a system (100) for generating multiple probability streams with varying probabilities for stream processing applications. The system comprises at least one probabilistic bit (110) configured to produce a fixed probability output and a digital logic circuit (120) designed to process the outputs from the probabilistic bit. The digital logic circuit performs logic operations to transform the fixed probability outputs into multiple streams with different probabilities. This approach reduces the complexity associated with analog control of probabilistic bits by shifting the probability adjustment to the digital domain. The system enables efficient and scalable probability stream generation suitable for applications such as stochastic computing, bit stream computing, and neural networks. Its versatility and reduced hardware requirements make it an ideal solution for error-tolerant stream processing tasks, providing a balance between accuracy, speed, and implementation simplicity.

A device (100; 200; 300) for Fourier Transform spectroscopy comprises: a first light propagating unit (120; 220; 320) receiving a first portion of a light signal and being configured to couple out fractions of the first portion by a sequence of first out-coupling elements (124; 224; 324) with a remaining fraction of the first portion continuing propagation along the first waveguide (122; 222; 322); a second light propagating unit (130; 230; 330) receiving a second portion of the light signal and being configured to couple out fractions of the second portion by a sequence of second out-coupling elements (132; 232; 332) with a remaining fraction of the second portion of the light signal continuing propagation along the second waveguide (132; 232; 332); wherein optical path lengths between sequential out-coupling elements are different in the second waveguide (132; 232; 332) and the first waveguide (122; 232; 332).

The invention is related to a micro-electronic component comprising superconducting digital logic circuitry, including at least one capacitor that comprises a bottom and top electrode (6',8') formed of superconducting NbTiN, and a dielectric interlayer (7') formed of orthorhombic HZO. A method for producing the capacitor includes method steps for producing of NbTiN electrodes defined by atomic concentrations of its constituent elements which enable superconductivity as well as the formation of HZO in the orthorhombic phase that remains stable throughout the sequence of method steps for producing the capacitor. The invention thereby enables producing capacitors for integration in an SDL circuit, for example to be used for the power supply in the circuit, which exhibit superior electrical performance combined with advanced scalability to nanosized dimensions.

In an aspect there is provided a semiconductor device comprising:a first and second power rail structure extending in parallel, each comprising a bottom power rail and a top power rail arranged above the bottom power rail;a row of local interconnects arranged between and extending in parallel to the first and second rows of CFET devices;a first and second row of complementary field-effect transistor, CFET, devices extending in parallel to the first and second power rail structures, wherein the first row of CFET devices is arranged between the first power rail structure and the row of local interconnects, and the second row of CFET devices is arranged between the second power rail structure and the row of local interconnects;a logic cell comprisingat least one CFET device of the first row of CFET devices configured to implement a first logic gate, and a first local interconnect of the row of local interconnects configured to interconnect a top and bottom source/drain, S/D, of a first CFET device of the at least one CFET device of the first row of CFET devices; andat least one CFET device of the second row of CFET devices configured to implement a second logic gate, and a second local interconnect of the row of local interconnects configured to interconnect a top and bottom S/D of a second CFET device of the at least one CFET device of the second row of CFET devices,wherein the first logic gate is connected to first input and output pins of the logic cell and the second logic gate is connected to second input and output pins of the logic cell, andwherein the first power rail structure is configured to power the first logic gate and the second power rail structure is configured to power the second logic gate.

A method for producing a semiconductor structure (100) is provided. The method comprises: providing (12) a semiconductor fin (110) on a substrate (102), the semiconductor fin (110) comprising a first side surface (111), a second side surface (112) opposing the first side surface (111), and a top surface (113), wherein a mask (120) covers the top surface (113) of the semiconductor fin (110); exposing (14) a portion (114) of the top surface (113) of the semiconductor fin (110) by removing (15) a portion (124) of the mask (120), the exposed portion (114) of the top surface (113) and the first side surface (111) forming an exposed top corner (130) of the semiconductor fin (110); rounding (16) the exposed top corner (130) of the semiconductor fin (110) by oxidizing (17) the exposed portion (114) of the top surface (113) and the first side surface (111).

According to an aspect of the present inventive concept there is provided a method (1000) for fabricating a semiconductor structure (100), the method comprising: providing (1100) a substrate (110); providing (1200), on top of the substrate (110), a multi-layer stack (200) comprising, sacrificial layers (211, 212, 213, 214, 215) of a first type, sacrificial layers (221, 222, 223) of a second type, and first, second, and third channel layers (201, 202, 203); forming (1300) a first and second ridge (130, 140) from the multi-layer stack (200); and for the first ridge (130): removing (1400) the sacrificial layers (221, 222, 223) of the second type by selective etching, oxidizing (1500) the sacrificial layers (211, 212, 213, 214, 215) of the first type, and removing (1600) the second channel layer (202) by selective etching, wherein the oxidized sacrificial layers (131, 133, 135, 137, 139) protect the substrate (110) and the first and third channel layers (201, 203) from the selective etching step used to remove the second channel layer (202).

The present invention relates in an aspect to an integrated circuit device. The integrated circuit device comprises an active device tier and a frontside interconnect structure arranged at a frontside of the active device tier and a backside interconnect structure arranged at a backside of the active device tier. The integrated circuit device comprises a plurality of circuit blocks, and a data communication circuit configured to transfer data between the plurality of circuit circuit blocks. The data communication circuit comprises a plurality of switching circuits. Each circuit circuit block is connected to the data communication circuit by a switching circuit. The data communication circuit further comprises a plurality of data communication channels interconnecting the plurality of switching circuits and comprising a plurality of backside interconnects arranged in one or more interconnect layers of the backside interconnect structure.

A 3D CCD based imager, comprising: a photosensitive layer, comprising a plurality of pixels to perform photoelectric conversion; a CCD gate stack, configured to store and transfer charge; and a readout layer, configured to read out a signal representative of the charge stored in the CCD gate stack. The CCD gate stack comprises: a plurality of gate layers and a plurality of spacer layers, which are alternatingly arranged one on the other along a first direction; a plurality of channels extending in the CCD gate stack along the first direction, for forming a plurality of strings of charge storage capacitors; and a plurality of dielectric layers extending in the CCD gate stack along the first direction, configured to isolate the plurality of channels from the plurality of gate layers.

This disclosure proposes a reference voltage circuit, which may be used with a temperature sensor of a neural interface. The circuit comprises a first MOS transistor for providing a current to a set of transistors. In the set of transistors, a second MOS transistor generates a first PTAT voltage, a BJT generates a CTAT voltage, and a third MOS transistor generates a second PTAT voltage. The reference voltage is the sum of the first and second PTAT voltage and the CTAT voltage. The first and the third MOS transistor are of the same type of device, and a source-bulk voltage of the third MOS transistor is non-zero. The first PTAT voltage is independent of a threshold voltage of the second MOS transistor, and a dependence of the second PTAT voltage on the threshold voltage of the third MOS transistor is the opposite of a dependence of the CTAT voltage on a threshold voltage of the first MOS transistor.

A method for forming a microfluidic device for culturing cells, the method comprising: providing a microfluidic device comprising a first chamber and a second chamber fluidically connected to the first chamber by a first porous structure comprising through holes for allowing fluid to pass through, said first porous structure physically separating the first chamber and the second chamber, wherein each of said chambers has photosensitive inner walls having a first property; and then irradiating the microfluidic device with light to which the photosensitive inner walls are sensitive, in such a way that the first porous structure acts as a mask during irradiation, thereby changing the surface property of the exposed surfaces and imparting a different surface property in the first chamber compared to the second chamber.

A device (100; 200) for interferometry detection comprises: a receiving unit (114; 214) configured to receive a reference beam and a response beam, based on a sample interacting with the sample beam to form the response beam carrying information of the sample; at least a first waveguide system (120; 220) configured to receive the reference beam and configured to transport the reference beam along different path lengths to a plurality of first outputs (126; 226); a plurality of light sensors (130; 230) configured to receive a combination of the reference beam and the response beam forming an interference of the reference beam and the response beam, wherein the plurality of light sensors (130; 230) are configured to simultaneously detect interference of the reference beam and the response beam corresponding to different path length relations between the reference beam and the response beam.

A system (100) for localization of an anatomical part in a subject comprises: an array of ultrasound transducers (110); a control unit (120) configured to activate a selected subset of at least one ultrasound transducer (110) for controlling the subset to assume a localization mode, wherein the at least one ultrasound transducer (110) is configured to transmit pulse(s) of ultrasound signals and detect the reflected pulse(s) for forming pulse echo data representing an ultrasound response for each pulse as a function of a time delay, wherein the control unit (120) is further configured to sequentially activate different selected subsets; a processing unit (130) configured to analyze the pulse echo data in relation to a characteristic pattern, and to identify one or more ultrasound transducers (110) being located to acquire pulse echo data representing the anatomical part for determining a location of the anatomical part in the subject.

A Code-Division Multiplexing radar system, comprises: a number NT transmitters, each configured to transmit a radar signal modulated by a unique code sequence, wherein one of the transmitters is configured to have a transmission power higher than the rest transmitters, a number NR receivers, each configured to receive a reflection signal caused by the transmitted radar signals, and reflected by a target, and a controller, configured to: - generate a number N virtual receive elements, for each virtual receive element VXp,q: - to detect the target, - based on the detected target, to generate a reconstructed interference signal ũp,q caused by the radar signals transmitted by the other transmitters except for the qth radar signal, and - to update a virtual receiving signal at said virtual receive element VXp,q based on the reconstructed interference signal x2.

According to an aspect of the present inventive concept there is provided a method for enabling tracking of an object in a flow channel comprising: receiving a first plurality of sequences of images; generating a first map, wherein said generating comprises: tracking the first plurality of training objects; determining movements of the first plurality of training objects; defining a first set of movement vectors; receiving a second plurality of sequences of images; generating a second map, wherein said generating comprises: tracking the second plurality of training objects; determining movements of the second plurality of training objects; defining a second set of movement vectors; generating a tracking map based on the second map; wherein a condition of the flow of liquid in the flow channel or of acquiring of sequences of images is changed between the first plurality of sequences of images and the second plurality of sequences of images.

A device (1) comprising: a first electrode (4) comprising a first electrode material of a type that, if oxidized by an oxidizing agent, is electrically insulating, a second electrode (2) comprising a second electrode material of a type that, if oxidized by said oxidizing agent, is electrically conducting, and a threshold switch layer (3) between the first electrode (4) and the second electrode (2), the threshold switch layer (3) comprising a material being switchable from an electrically insulating state to an electrically conducting state by a voltage between the first (4) and second electrode (2) crossing a threshold voltage, and a first electrode interface (40) between the threshold switch layer (3) and the first electrode (4), and a second electrode interface (20) between the threshold switch layer (3) and the second electrode (2), wherein the device (1) comprises the oxidizing agent suitable for being moveable between the first electrode (4) and the second electrode (2), the threshold switch layer (3) providing a passage for moving the oxidizing agent between the first electrode (4) and the second electrode (2).

In a one aspect, the present invention relates to a cell engineering module (4) for cell engineering target cells (51) in a mixture (5) comprising the target cells (51) and non-target cells (52), comprising: i) a cell monitoring zone (410) for allowing tracking and classifying individual cells (50) in the mixture (5), wherein classifying a cell (50) comprises determining whether the cell (50) is a target cell (51); and ii) an engineering component (42) in the cell monitoring zone (410) for selectively modifying individual cells (50) at one or more engineering sites (420), wherein the target cells (51) and the non-target cells (52) are randomly distributed in the engineering component (42); wherein the engineering component (42) is adapted for-in operation-being controlled so as to selectively modify only target cells tracked to be at one of the engineering sites (420).

A transistor structure for a vertical NAND flash memory device is provided. The transistor structure comprises a semiconductor channel layer, a first auxiliary layer and a second auxiliary layer arranged at two opposite sides of the semiconductor channel layer along a first axis, and each of the first auxiliary layer and the second auxiliary layer comprises a first material having a first relative permittivity, the first relative permittivity being larger than 1 and lower than 3.9. The transistor structure further comprises: a first dielectric layer arranged above the semiconductor channel layer, the first auxiliary layer and the first auxiliary layer along a second axis that is perpendicular to the first axis; a charge storage layer arranged on the first dielectric layer; a second dielectric layer arranged on the charge storage layer; and a gate layer arranged on the second dielectric layer.

A microfluidic device for purification of nucleic acids comprising: at least one microfluidic channel, said channel having a first surface, a second surface opposite the first surface, and connecting surfaces joining the first and second surfaces; a plurality of fixed structures within said channel, said structures being attached to at least one of the first surface or second surface of the channel, collectively occupying at least 95% of the distance between the connecting surfaces, and each structure extending across at least 95% of the distance between the surface to which it is attached and the opposite surface; at least one inlet for introducing a fluid containing nucleic acids or molecular assemblies comprising nucleic acids into the channel; and at least one outlet for collecting purified nucleic acids; wherein said fixed structures comprise a surface capable of reversibly binding either nucleic acids or molecular assemblies comprising nucleic acids.

A method for manufacturing a co-integrated semiconductor structure (1) from a first (100) and a second (200) layer stack, the first layer stack (100) comprising a channel layer (10) and at least one sub-stack (150) on the channel layer (10), wherein each of the at least one sub-stack (150) comprises a sacrificial layer of a first type (21), a first slender layer (31) on the sacrificial layer of the first type (21), a sacrificial layer of a second type (22) on the first slender layer (31), a second slender layer (32) on the sacrificial layer of the second type (22), a further sacrificial layer of the first type (21) on the second slender layer (32), and a further channel layer (10) on the further sacrificial layer of the first type (21), the second layer stack (200) comprising a channel layer (10) and at least one sub-stack (250) on the channel layer (10), wherein each of the at least one sub-stack (250) comprises a sacrificial layer of the first type (21) and a further channel layer (10, 11) on the sacrificial layer of the first type (21), wherein a separation (S1) between the neighboring channel layers (10) of the first layer stack (100) is larger than a separation (S2) between neighboring channel layers (10) of the second layer stack (200).

A method (100) for wafer-scale fabrication of a non-cytotoxic reference electrode for various types of sensors, including electrochemical sensors, biosensors, and other devices used for analyte sensing is provided. The method comprises the steps of forming (101) at least one electrode on a substrate, forming (102) one or more metal or metal oxide layers on top of the at least one electrode, functionalizing (103) the one or more metal or metal oxide layers, providing (104) a membrane on top of the one or more metal or metal oxide layers to confine ions diffused from the one or more metal or metal oxide layers, forming (105) a reservoir on top of the membrane, filling (106) the reservoir with a reference electrolyte, and providing (107) at least one sensor inside the reservoir being in contact with the reference electrolyte to measure a total ion concentration and/or a specific ion concentration and/or a temperature of the reference electrolyte, enabling correction for sensor drift.

This disclosure relates to a comparator circuit and an ADC circuit for a neural interface. The ADC circuit includes the comparator circuit. The comparator circuit comprises a comparator to receive a first and a second signal, and internally amplify the first and the second signal. A bump bias circuit of the comparator circuit receives the amplified first and second signal, and causes the comparator to operate at a higher power level when a difference between the amplified first and second signal is smaller, and at a lower power level when the difference between the amplified first and second signal is larger. The ADC circuit comprises two comparator circuits connected to a first and second switching circuit. A control circuit of the ADC circuit can set a capacitor state of first capacitor pairs of the first switching circuit, and a capacitor state of second capacitors pairs of the second switching circuit, based on outputs of the respective comparator circuit.

A system (100) for synthesizing copolymerized molecules on a substrate (10) includes: a light source (20) emitting exposure light; a programmable light direction unit (30) for redirecting the light in specific patterns; a substrate holder (40); a reagent delivery system (50) for dispensing reagents; and a lateral movement mechanism (60) for generating relative movement between the light direction unit and the substrate holder. A controller (70) controls: i) reagent dispensing; ii) light exposure in a first pattern; iii) relative movement and adjustment of the light direction unit to a second pattern; and iv) subsequent exposure in the second pattern.

A quantum circuit and related manufacturing method are disclosed. The quantum circuit comprises a vertical Josephson junction (1001) formed by a bottom electrode (810) in a first superconducting material layer, a tunnel barrier (830), and a top electrode (820) in a second superconducting material layer. A contact portion (811) and a coupling portion (812) of the bottom electrode are located inside and outside the Josephson junction, respectively. A transmon qubit of the quantum circuit comprises the Josephson junction and a shunt capacitor formed by the top electrode and the contact portion of the bottom electrode as capacitor plates. A readout circuit is capacitively coupled to the bottom electrode through the coupling portion and includes a coupling head (861). The coupling portion is fitted into a recessed portion of the coupling head. The top electrode is configured as a floating electrode, not resistively coupled to the first superconducting material layer.

A thinned semiconductor substrate (1) is provided having a front end of line (FEOL) portion (2) on its front side. The FEOL portion includes conductive structures (3,40) at the front side of the thinned substrate, which need to be contacted by connections through the substrate. An opening (15) is etched from the back of the thinned substrate, to be filled with a conductive material. The bottom of said opening overlaps at least partially the end surface (14) of the conductive structure to be contacted, and further overlaps one or more portions of semiconductor material of the substrate. According to the invention, etching of the opening continues beyond the end surface into said semiconductor portion(s), to thereby create one or more cavities (27). A first dielectric layer (30) is formed on the sidewalls and bottom of the opening, so that the cavity or cavities are filled with the material of the first layer. This material is then removed everywhere except in the cavity or cavities (27). If necessary, a second dielectric layer (31) may be formed as a liner on the sidewalls and bottom of the opening (15), to be opened up at the bottom by an anisotropic etch to thereby expose said end surface (14), but wherein the dielectric of the first layer remains in the cavity or cavities (27). These dielectric-filled cavities thereby inhibit the formation of shorts between the eventual through-connection (18,43) obtained by filling the opening, and the semiconductor material of the substrate (1)..

A method for determining a temperature map (70, 800) at a target resolution of an IC design (10), the method comprising: determining (200) a high-resolution power map (20) and a low-resolution power map (30); determining (400) a low-resolution temperature map (40) corresponding to the low-resolution power map; up-sampling (500) the low-resolution temperature map to the target resolution to obtain an intermediate temperature map (50); and for one or more ROIs: up-sampling (600) the low-resolution power map in the ROI (203) to the first, high resolution to obtain a local intermediate power map in the ROI (303); determining a difference between (601) the local intermediate power map and the high-resolution power map in the ROI (202), thereby obtaining a local differential power map (61) in the first, high resolution for the ROI; and determining (602) a local differential temperature map (62) in the target resolution corresponding to the local differential power map; and combining (700) the local differential temperature map with the intermediate temperature map in the ROI.

According to an aspect of the present inventive concept there is provided a device for characterizing objects comprising: a flow channel configured to pass a flow of liquid, wherein: the flow of liquid carries the objects, the flow channel comprises a zone associated with a category, wherein a surface is coated with molecules having an affinity and specificity to the category, whereby the surface forms an object movement modifying (OMM) surface configured to modify the movement of the object by binding and releasing the object; wherein the device is configured to modulate a force exerted on the object; wherein the device is configured to exert a first condition and a second condition on the object, the first condition being adapted to promote the binding of an object belonging to the category to the OMM surface and the second condition being adapted to promote the releasing of an object bound to the OMM surface.

A system (100) for performing electromyography (EMG) measurements, the system comprising an EMG unit (110) for collecting electromyography data of a user, the EMG unit (110) comprising a plurality of EMG electrodes (120), one or more other sensors (130) for capturing sensor data related to a motion and/or activity of the user, a sensor data processing unit (140) being programmed for processing the captured sensor data using a muscle activity expectation model (142) for identifying specific muscles used during the motion and/or activity of the user, and the system being adapted for selecting a subset of EMG electrodes from the plurality of EMG electrodes (120), said selecting being based on the identified specific muscles.

The present invention provides a method for forming a gate stack (100) on a semiconductor substrate (102), the method comprising:forming a dielectric interlayer (103) on the semiconductor substrate (102),forming a dipole-forming layer (104) comprising a work function shifting metal and oxygen on top of the dielectric interlayer (103);etching the dipole-forming layer (104) such that a residue (106) of the dipole-forming layer (104) remains on the dielectric interlayer (103), the residue (106) being less than one monolayer of the dipole-forming layer (104), wherein a temperature is kept below 430 °C between said acts of forming the dipole-forming layer (104) and etching the dipole-forming layer (104);depositing a gate dielectric (108); anddepositing a metal gate (110) on the gate dielectric (108).

A device (100; 200; 300; 400) for light detection comprises: an active layer (110; 210; 310; 410) configured to generate electrons in response to incident light; a silicon layer (120; 220; 320; 420) comprising a diode arrangement (122) configured for collection of the electrons generated by the active layer (110; 210; 310; 410); and an interface layer (140; 240; 340; 440) arranged between the active layer (110; 210; 310; 410) and the silicon layer (120; 220; 320; 420), wherein the interface layer (140; 240; 340; 440) is configured to provide an alignment of a conduction band of electrons between an energy level of the active layer (110; 210; 310; 410) and an energy level of the silicon layer (120; 220; 320; 420) for facilitating transport of the generated electrons from the active layer (110; 210; 310; 410) to the silicon layer (120; 220; 320; 420).

A three-dimensional integrated circuit, comprising a first tier, a second tier, vertically stacked above the first tier, and a memory circuit. The memory circuit comprises a bitcell array disposed in the first tier. The memory circuit also comprises a column peripheral circuit having at least an elongate first portion disposed in the second tier. The memory circuit also includes a row decoder being elongate and disposed in the second tier and extending in a direction parallel to the first portion of the column peripheral circuit.