imec Patente

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The invention is related to a semiconductor component, for example an integrated circuit chip, comprising a semiconductor substrate (1) having active devices (7) at the front side thereof and I/O terminals (19) at the back side of the component. The terminals are connected to the active devices through TSV connections (16b) and buried rails (15b) in an area (5) of the substrate that is separate from the area (4) in which the active devices are located. According to the invention, the I/O TSV connections (16b) are located in a floating well (25) of the substrate that is separated from the rest of the substrate by a second well (26) formed of material of the opposite conductivity type compared to the material of the floating well. The second well (26) comprises at least one contact (28) configured to be coupled to a voltage that is suitable for reverse-biasing the junction (27) between the floating well (25) and the second well (26). In this way, a small capacitance is placed in series with the large parasitic capacitance generated by a thin dielectric liner that isolates the I/O TSVs and I/O rails from the substrate, thereby mitigating the negative effect of the large parasitic capacitance. According to preferred embodiments, additional contacts and conductors are provided which are configured to create an ESD protection circuit for protecting the I/O TSVs (16b) and the I/O rails (15b) from electrostatic discharges.

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A method (100) for forming a semiconductor device (1), the method comprising:forming a stack of field effect transistors (60), FETs, on top of a substrate (4), the stack of FETs comprising a bottom FET (61) and a top FET (62), the bottom FET (61) comprising at least a first source/drain region (51);forming a first insulating layer (11) laterally surrounding the stack of FETs (60);etching a hole (20) into the first insulating layer (11), the hole (20) extending between a top endpoint (26) and a bottom endpoint (25);filling the hole (20) with electrically conductive material such that the electrically conductive material of the filled hole (20) forms a via (21);etching, from a bottom side (4b) of the substrate (4) towards the first insulating layer (11), a trench (30), such that a top part (30p) of the trench (30) comprises both a bottom side (51b) of the first source/drain region (51) and the bottom endpoint (25);filling the top part (30p) of the trench (30) with electrically conductive material, such that the electrically conductive material of the filled top part (30p) of the trench (30) electrically connects the bottom side (51b) of the first source/drain region (51) to the bottom endpoint (25) of the via (21).

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A substrate (1) is provided comprising on its surface a patterned area (8) defined by a given topography. The substrate is to be processed for obtaining a TEM sample (4) in the form of a slice of the substrate . According to the method of the invention, a conformal layer (7) of contrasting material is deposited on the topography, by depositing a layer (5) of the contrasting material on a local target area (6) of the substrate, spaced apart from the patterned area (8). The material is deposited by Electron Beam Induced Deposition (EBID). The deposition parameters, the thickness of the layer (5) deposited in the target area (6), and the distance of said target area to the patterned area, are such that a conformal layer (7) of the contrasting material is formed on the topography of the patterned area (8). This is followed by the deposition of the protective layer (10), which does not damage the topography in the patterned area (8), as it is protected by the conformal layer (7). The TEM sample (4) is prepared in a manner known in the prior art, for example by FIB. The conformal contrasting layer (7) provides a good contrast with the protective layer, thereby allowing a high quality TEM analysis.

A force sensing device (100) comprises: a flexible substrate (102); a sensor unit (112) arranged thereon comprising: at least one first electrode (114a-d) in a first layer (116); at least one second electrode (120) in a second layer (122); wherein a plurality of first electrodes (114a-d) and/or second electrodes is provided; an intermediate structure (130) between the first and second electrodes for changing characteristics upon a force being received; trench(es) (140) in the second layer (122) partially surrounding the second electrode(s) (120), wherein bridging structure(s) (142) provides an anchoring position defining a fixed relation between the first and second layers (116; 122); a rigid projecting structure (150) projecting from the second layer (122) and connected to the second electrode(s) (120), wherein the rigid projecting structure (150) is embedded in an elastic material (152) for allowing the rigid projecting structure (150) to be tilted in relation to the first layer (116).

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A sensor device (100) comprises: a plurality of sensors (102a-f), wherein each sensor (102a-f) comprises an optical resonance element (106a-f) configured to be affected by a measurand and has a mutually unique optical resonance frequency; the sensors (102a-f) being configured to receive at least one of a first and a second sensor interrogation signals forming a plurality of signal component pairs, wherein a difference in frequency between the frequencies in the signal component pair is different for different signal component pairs; wherein each sensor (102a-f) is configured to modulate an optical intensity of at least one frequency of a mutually unique signal component pair; and a detector (110), being configured to receive the first sensor interrogation signal and the second sensor interrogation signal, wherein the detector (110) is configured to detect a plurality of mutually unique beat frequencies for detecting a plurality of measurements by the plurality of sensors (102a-f).

An integrated photonics arrayed waveguide multiplexing/demultiplexing device (1) comprising:- an array (30) of waveguides (300) comprising:o an incident light waveguide section (301) comprising a phase correcting region (31);o a transmitted light waveguide section (302);o a tunable reflector (32);wherein each pair of consecutive waveguides (300) in the array (30) comprises a coupler (33) configured to:- combine light from the transmitted light waveguide sections (302);- determine therefrom an optical phase difference between the two consecutive waveguides (300); andwherein the couplers (33) are further configured to determine therefrom a change (3) in optical path length required for each of two consecutive waveguides (300) to reach a predetermined optical phase difference;and wherein each phase correcting region (31) is configured to apply the change (3) to correct the optical path length of the respective waveguide (300).

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An optical system (10) is provided. Said optical system (10) comprises an optical waveguide (11), and at least two coupling means (12, 13) forming at least one confocal point being located within the optical waveguide (11). In this context, a first coupling means (12) of the at least two coupling means (12, 13) has a first focal length, and a second coupling means (13) of the at least two coupling means (12, 13) has a second focal length. In addition to this, the first coupling means (12) is configured to couple and/or focus incident light (16a) to the optical waveguide (11), wherein the second coupling means (13) is configured to emit and/or collimate light (16b) conveyed by the optical waveguide (11).

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The disclosure relates to a method for manufacturing a shape-retaining non-flat device (100), comprising: providing (S10) a flat device laminate (200) comprising: a first layer of thermoformable material (210); a carrier layer (230); conductive traces (240) arranged at least on a second portion (232) of the carrier layer (230); a circuit element (250) arranged on the second portion (232) and electrically connected to the conductive traces (240); deforming (S20) the device region (260) of the flat device laminate (200) into the shape-retaining non-flat device (100) by thermoforming (S22) the flat device laminate (200), wherein the carrier layer (230) is non-stretchable such that the respective shortest distance (d), along the second portion (232) of the carrier layer (230), between the circuit element (250) and a first portion (231), prior to and after the step of deforming (S20) the flat device laminate (200), are equal.

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According to an aspect there is provided a memory cell (10, 50). The memory cell (10, 50) comprises: a first (21, 61) and a second (22, 62) electrode; a spin-orbit-torque, SOT, layer (30, 70) comprising a first (31, 71) and a second (32, 72) electrode contact portion arranged in contact with the first (21, 61) and the second (22, 62) electrode, respectively, and an intermediate portion (33, 73) between the first and second electrode contact portions (31, 32, 71, 72); a first magnetic tunnel junction, MTJ, layer stack (41, 81) arranged in contact with the intermediate portion (33, 73); and a second MTJ layer stack (42, 82) arranged in contact with the first or second electrode contact portion (32, 72). A memory device (90) comprising such a memory cell (10, 50) and a method (100) for writing to such a memory cell (10, 50) are also provided.

A self-biased amplifier circuit (100; 200), comprises: an input, wherein the input comprises input transistors (110, 112, 114, 116; 210, 212, 214, 216) forming inverters; bias transistors (118, 120, 122, 124; 218, 222), wherein a source of each input transistor (110, 112, 114, 116; 210, 212, 214, 216) is connected to a drain of a bias transistor (118, 120, 122, 124; 218, 222) for providing a bias current to the inverters; an output connected to a first output node (106; 206) and/or a second output node (108; 208); and pairs of transistor switches (126, 128; 226, 228) connected between the first (106; 206) or the second output node (108; 208) and a respective gate of the bias transistors (118, 120, 122, 124; 218, 222), wherein the pairs of transistor switches (126, 128; 226, 228) are configured to control the self-biased amplifier circuit (100; 200) to assume an active mode or a standby mode.

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