GlobalFoundries U.S. Patente

A system for developing a design in an advanced semiconductor-on-insulator processing technology includes a process design kit (PDK). A cell library in the PDK includes compact ancillary component cells placeable adjacent a functional block in a design layout. Some cells contain pairs of ancillary components including: a first ancillary component (e.g., a substrate diode) in a first hybrid area; a second ancillary component (e.g., a zero bias tap, a bias tap, or a signal antenna) in a second hybrid area; a first semiconductor-on-insulator area between the first and second hybrid areas and including less than five gate structures; and a second semiconductor-on-insulator area between the second hybrid area and functional block. Another cell contains a stand-alone signal antenna component and is placeable in the design layout between sections of a stacked memory-type functional block without requiring supporting cells. An IC structure can be manufactured according to such a design layout.

Structures for an optical switch and methods of forming such structures. The structure comprises a Mach-Zehnder interferometer including a first arm, a second arm, a first waveguide core section coupled to the first arm, and a second waveguide core section coupled to the second arm. The structure further comprises a first ring resonator and a second ring resonator. The first ring resonator is positioned between the first waveguide core section and the second ring resonator, and the second ring resonator is positioned between the second waveguide core section and the first ring resonator.

The present disclosure relates to semiconductor structures and, more particularly, to a contact strap extending to a common source/drain region of adjacent gate structures and methods of manufacture. The structure includes: a first gate structure; a second gate structure adjacent to the first gate structure; a common diffusion region to the first gate structure and the second gate structure; a trench lined with insulator material; and a contact strap extending within the trench and connecting to the common diffusion region.

The present disclosure relates to semiconductor structures and, more particularly, to a lateral heterojunction bipolar transistor (HBT) and methods of manufacture. The structure includes: a buried extrinsic base (20) within a semiconductor material (18); an intrinsic base (24) over and in electrical contact with the extrinsic base (20); an emitter (12) having a semiconductor material with a single crystalline orientation, the emitter being (12) above the intrinsic base (24) and comprising a faceted sidewall (12a); a collector (16) having the semiconductor material with the single crystalline orientation, the collector (16) being above the intrinsic base (24) and comprising a faceted sidewall (16a); and a spacer (14) between the emitter and the collector.

The present disclosure relates to an optical fiber positioning device and, more particularly, to an optical fiber positioning device and a method for attaching a fiber optic array to a photonic integrated circuit (PIC). The structure includes: a body having a first end and a second end; a dome shaped indicator provided on the body; a first positioning mark associated with the dome shaped indicator; and a second positioning mark under the first positioning mark and associated with the dome shaped indicator.

Structures for a Mach-Zehnder interferometer and methods of forming a structure for a Mach-Zehnder interferometer. The structure comprises a Mach-Zehnder interferometer including a first directional coupler, a second directional coupler, a first delay arm between the first and second directional couplers, and a second delay arm between the first and second directional couplers. The first delay arm includes a portion with a U-shape that surrounds a pocket, and the second delay arm includes a portion with a U-shape that extends into the pocket.

Disclosed are embodiments of structure including: a chip with an embedded magnetic random access memory (eMRAM) or other on-chip component susceptible to magnetic field-induced performance degradation; and magnetic shield(s) for protecting the chip. In some embodiments, a magnetic shield includes abutting magnetic layers having different magnetic properties. In other embodiments, a magnetic shield includes abutting magnetic layers (of the same or different magnetic materials) having offset patterns of openings (e.g., through-holes or mesh). In any case, the chip can be mounted on a board and contained in a package. Such magnetic shields can be located on the package (opposite the board) and/or on the board (opposite the chip) depending upon the expected location of a potentially adverse magnetic field.

The present disclosure relates to semiconductor structures and, more particularly, to high-electron-mobility transistors with field plates and methods of manufacture. The structure includes: a gate structure on a semiconductor substrate; a passivation layer adjacent to the gate structure and above the semiconductor substrate; an insulator material over the passivation layer; and a field plate comprising a first portion contacting the passivation layer and a second portion being separated from the passivation layer by the insulator material.

The disclosure provides a vertical bipolar transistor with an emitter contact (146) wider than an emitter terminal (114, 148), and related methods. A structure of the disclosure includes an emitter contact (146) within an inter-level dielectric (140) layer and on an emitter terminal (114, 148) of a bipolar transistor (100), wherein a horizontal width of the emitter contact (146) is greater than a horizontal width of the emitter terminal (114, 148) thereunder.

Structures for a photonic component and methods of forming a structure for a photonic component. The photonic structure comprises a semiconductor substrate, a first waveguide core including a first plurality of segments, and a second waveguide core including a second plurality of segments. The second plurality of segments are positioned between the first plurality of segments and the substrate.

A bit cell (BC) includes: a variable resistor and a first transistor connected in series between two end nodes; and a second transistor also connected between the two end nodes. Gates of the first and second transistors are connected to first and second word lines (WLs), respectively, for a row. A circuit includes an array of BCs. In each column, BCs are connected in a stack between a sense amplifier (SA) and footer device (FD). During a read operation, FDs connect the stacks to ground. Additionally, first and second WL voltages on first and second WLs for each row are such that, for any selected row, first transistors of BCs are on and second transistors are off and, for any unselected row, first transistors of BCs are off and second transistors are on. SAs compare sense currents from the stacks to a mid-level reference current to concurrently compute majority functions.

Structures for a phase shifter and methods of forming such structures. The structure comprises a first layer comprising a first electro-optic material, a second layer comprising a second electro-optic material, and a third layer between the first layer and the second layer. The third layer comprises a dielectric material that is an electrical insulator. A waveguide core is positioned on a portion of the first layer.

Embodiments of the disclosure provide a circuit structure and method with a resistor for reducing a discharged pad voltage. A structure of the disclosure includes a resistor having a first end connected to a pad and a second end opposite the first end. A trigger circuit is connected between the pad and ground. A discharge circuit is connected between the second end of the resistor and ground. The discharge circuit is connected to an output node of the trigger circuit.

Structures for a high-electron-mobility transistor and methods of forming such structures. The structure comprises a layer stack including an active region, and a dielectric layer on the active region of the layer stack. The active region has a perimeter. The dielectric layer includes an opening and portions between the opening and the perimeter of the active region. The structure further comprises a source/drain region inside the opening in the dielectric layer.

A gain cell memory device includes a semiconductor device layer of a silicon on insulator (SOI) substrate comprising an active region, a storage transistor over the active region of the semiconductor device layer, an isolation structure between a gate electrode of the storage transistor and a source/drain region adjacent to the storage transistor, the isolation structure extending through the active region such that a first portion of the active region is isolated from a second portion of the active region, and a capacitor coupled to the storage transistor. A bottom plate of the capacitor comprises the first portion of the active region, a gate dielectric layer of the storage transistor is an insulator of the capacitor, and a top plate of the capacitor comprises the gate electrode of the storage transistor and a metal structure over the gate electrode.

The present disclosure relates to heterojunction bipolar transistors with a common extrinsic base, and methods of manufacture. The structure includes: a first transistor (100) having an intrinsic base (14a), an extrinsic base (12a) and an emitter (32a); and a second transistor (200) having an intrinsic base (14b), an extrinsic base (12b) and an emitter (32b). The extrinsic base (12a) of the first transistor and the extrinsic base (12b) of the second transistor have a common extrinsic base region (12a, b, c) with a first dopant type for the first transistor and a second opposite dopant type for the second transistor.

Semiconductor structures that include a conductor layer and multiple dielectric layers, as well as methods of forming such semiconductor structures. The structure comprises a first dielectric layer, a second dielectric layer, and a conductor layer including a first section and a second section between the first dielectric layer and the second dielectric layer. The structure further comprises a semiconductor layer including a first section that overlaps with the first section of the conductor layer and a second section that overlaps with the second section of the conductor layer, and a trench isolation region including a first portion laterally between the first section of the conductor layer and the second section of the conductor layer.

An electronic fuse includes an inactive gate structure over a substrate, and a fuse link along at least one sidewall of the inactive gate structure. A first terminal is at a first end of the fuse link, and a second terminal is at a second of the fuse link. The fuse link takes the form of a conductive metal spacer along at least one sidewall of the inactive gate structure and can be formed without a silicide process. Although the e-fuse can be used with any semiconductor device, it is advantageous for use with, for example, III-IV semiconductor devices. The method of making the e-fuse does not require any additional masks and provides a fuse link having a sub-photolithographic width dimension.

Embodiments of the present disclosure provide a memory circuit, including: a non-volatile memory; a one-time-programmable memory; a sense amplifier coupled to the non-volatile memory and the one-time-programmable memory; a digital register coupled to an output of the sense amplifier for storing reference resistance bits; control logic coupled to an output of the digital register; a decoder coupled to an output of the control logic; and a controller for outputting a control signal to the control logic to select a first reference resistance for the sense amplifier from the decoder for a reading of bits from the one-time-programmable memory, and to select a second reference resistance for the sense amplifier from the decoder for a reading of bits from the non-volatile memory.

The present disclosure relates to layout recommendations and, more particularly, to dynamic layout optimization systems, processes and methods of use. The method includes: determining mismatches between design notes and layout data of an integrated circuit; generating suggestions to correct the mismatches between the design notes and the layout data of the integrated circuit; providing an output of the mismatches between the design notes and the layout data of the integrated circuit including the suggestions; and saving the mismatches and suggestions to a log file.

The present disclosure relates to semiconductor structures and, more particularly, to body contacted transistors and methods of manufacture. The structure includes: an active gate structure on a semiconductor substrate; at least one body contact extending through the active gate structure and connecting to a body region that contains a channel of the active gate which is under the active gate structure; and insulator material isolating the at least one body contact from the active gate structure.

The present disclosure relates to vertical heterojunction bipolar transistors (10) and methods of manufacturing. The structure includes: a sub-collector region (14); a collector region (12, 26) over the sub-collector region, the collector region having a first semiconductor material (12) comprising polysilicon material (12a) and single crystalline semiconductor material (12b) which is over the sub-collector region, and a second semiconductor material (26) on the single crystalline semiconductor material (12b); STI regions (16) under the polysilicon first semiconductor material (12a); diffusion regions (22) in the polysilicon first semiconductor material (12a); a base region (30) over the collector region (12, 26); and an emitter region (32) over the base region (30).

A laterally diffused field effect transistor (LDFET) and a related method are disclosed. The LDFET includes a substrate having a fin region and a planar region adjacent to the fin region. The LDFET also includes a source region in the fin region, a drain region in the planar region, a channel gate over the fin region and the planar region, and a drain extension region in the planar region between the source region and the drain region. The use of a substrate with a fin region for the source region and the channel of the channel gate and a planar region for the drain region and the drain extension region provides many of the benefits of both types of substrates for the LDFET.

A resistor including a first current transport level, a second current transport level, and a vertical interconnect resistor that couples the first and second current transport levels. The vertical interconnect resistor includes a doped conductive layer including one of indium gallium nitride (InGaN) and a doped polysilicon. The first and second current levels may include a number of current level islands that can be coupled in a lateral serpentine fashion and a vertical serpentine fashion to control a length and resistance value of the resistor. The resistor can be employed with III-V semiconductor devices and takes up less areal space than current resistors.

The disclosure provides a structure base portions having different germanium concentrations, and related methods. A structure of the disclosure includes a base region including a first portion on a first emitter/collector (E/C) terminal and including germanium (Ge). A Ge concentration in the first portion varies with respect to distance from the first E/C terminal. A second portion is on the first portion and includes Ge. A third portion is between the second portion and a second E/C terminal and includes Ge. A Ge concentration in the third portion varies with respect to distance between the second portion and the second E/C terminal.

Disclosed are embodiments of a structure for polarization-independent coarse wavelength division demultiplexing. The structure includes a polarization splitter-rotator (PSR), which receives a dual polarization mode multi-wavelength optical signal and outputs a single polarization mode multi-wavelength optical signal. The structure includes a wavelength division demultiplexer (WDD) and a thermo-optic phase-shifter (TOPS), which is coupled to the PSR and either coupled to the input section of the WDD or integrated into the input section of the WDD. The structure includes at least one photodetector and a thermal control system (TCS). The photodetector is coupled to an unused end of a waveguide in either the TOPS or WDD (depending on the embodiment). The TCS monitors output current from the photodetector, and based thereon, sets heating voltage(s) applied to heating element(s) in the TOPS, ensuring that single wavelength optical signals output from output sections of the WDD are at desired wavelengths and power levels.

Disclosed is a dual-antifuse (DAF) device with two electrically isolated antifuses. The DAF device includes a gate structure including a dielectric layer lining a recess in a semiconductor layer between first and second conductive regions and a conductor layer on the dielectric layer. A gate cut isolation structure extends through the conductor layer, dividing the conductor layer into first and second conductor sections. As a result, the device includes a first antifuse (i.e., the first conductor section, the first conductive region, and the dielectric layer therebetween) and a second antifuse (i.e., a second conductor section, the second conductive region, and the dielectric layer therebetween), which is isolated from the first antifuse. Thus, the two antifuses are independently programable. Also disclosed herein are memory structure embodiments, which include DAF devices (either with or without electrically isolated antifuses) integrated into the cells of an array and which are configured for improved reliability.

The disclosure provides bipolar transistor structures with a semiconductor film, and related methods. A structure of the disclosure includes an intrinsic base on a collector. The collector has a first doping type. A semiconductor film is on the intrinsic base and horizontally surrounds the intrinsic base. The semiconductor film horizontally encapsulates the intrinsic base. An emitter having the first doping type is on a first portion of the semiconductor film. An extrinsic base having a second doping type is on a second portion of the semiconductor film.

Disclosed are predecoders and structures including the predecoders. Each predecoder includes, among other components, first and second latches controlled by write and read clock signals, respectively, and a multiplexer-enabled write logic bypass path. During a write, an address signal is latched by the first latch and propagated through logic downstream of the first latch (including through a write logic block) to the second latch (which is transparent). During a read, the write logic bypass path is activated so the address signal bypasses the first latch and the write logic block and is instead propagated only through logic downstream of the write logic block to the second latch (which periodically latches the received signal). In both operations, a predecoded address signal is output but, due to activation of the write logic bypass path during the read, the time between receiving the address signal and outputting the predecoded address signal is reduced.

A disclosed D flip-flop includes first and second stages. The first stage includes a first intermediate node. The second stage includes second and third intermediate nodes and a pair of transistors connected in series to the second intermediate node. The first and third intermediate nodes are connected to the gates of different ones of the transistors in the pair in order to provide feedforward and feedback paths for maintaining the voltage level of a signal on the second intermediate node when a clock signal is static and the second intermediate node is floating. Optionally, the second stage can also include a feedback loop (including an inverter and a multiphase clock-controlled tri-state logic device connected in series from and back to the third intermediate node) for maintaining the voltage level of a signal on the third intermediate node when the clock signal is static and the third intermediate node is floating.

Structures for a memory device and methods of forming a structure for a memory device. The structure (10) comprises a first transistor (48) including a first gate structure (18) and a first source/drain region (31, 32), a second transistor (50) including a second gate structure (20) and a second source/drain region (31, 32), and a capacitor including a first capacitor plate (43) directly coupled to the first source/drain region, a second capacitor plate (40), and a capacitor dielectric layer (38) between the first capacitor plate and the second capacitor plate.

The present disclosure relates to semiconductor structures and, more particularly, to diode triggered silicon controlled rectifiers and methods of manufacture. The structure includes: a vertical silicon controlled rectifier (SCR) having a doped semiconductor material region over a semiconductor substrate; and at least one vertical triggering diode electrically connected to the SCR in series, and having a doped semiconductor material region over a doped region in the semiconductor substrate.

A bipolar transistor structure comprising a semiconductor fin on a substrate, the semiconductor fin having a first doping type, a length in a first direction, and a width in a second direction perpendicular to the first direction; a first emitter/collector material adjacent a first sidewall of the semiconductor fin along the width of the semiconductor fin, the first emitter/collector material having a second doping type opposite the first doping type; and a second emitter/collector material adjacent a second sidewall of the semiconductor fin along the width of the semiconductor fin, the second emitter/collector material having the second doping type, wherein a width of the first emitter/collector material is different from a width of the second emitter/collector material.

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