NXP USA Patente

The present disclosure relates to a package assembly including an integrated circuit die having standoff structures and associated methods of die attach and fabrication. The package may include an integrated circuit die having standoff structures disposed on a bottom surface of the integrated circuit die, a die pad structure on which the integrated circuit die is disposed, and die attach material disposed between the integrated circuit die and the die pad structure. The standoff structures can include metallic ink. The standoff structures may contact an upper surface of the die pad structure. The die attach material may attach the integrated circuit die to the die pad structure.

A Doherty power amplifier circuit includes a first impedance circuit (230), a second impedance circuit (260), and a third impedance circuit (276). The first impedance circuit is coupled between a carrier amplifier and a combining node (246) that is connected to an output terminal (206). The second impedance circuit (260) includes an input coupled to an output of a peaking amplifier and includes an output. The third impedance circuit (276) is coupled between the output of the second impedance circuit (260)and the combining node (246). The first impedance circuit (230) provides a first impedance and the second and third impedance circuits (260, 276) provide a second impedance to the combining node (246) to produce an output impedance configured to match a load impedance. The first impedance circuit (230) provides a ninety-degree phase offset and the second and third impedance circuits (260, 276) provide a zero-degree phase offset.

Aspects of this disclosure are directed to a duty cycle, monitoring circuit for receiving at an input, and monitoring a duty cycle of, a clock signal, and comprising: an averaging circuit, connected to the input and configured to average the received clock signal; a first and second comparators, configured to compare the averaged clock signal with upper and lower thresholds, and to output a firs and secondt error signal in response to the average clock signal exceeding the upper threshold, or being less that the second threshold; a divider circuit connected between a first node and a second node, and configured to generate the upper threshold and the lower threshold at respective first and second intermediate nodes; and a first detector circuit operably coupled between the first node and the input for providing, at the first node, a voltage dependent on a maximum of the received clock signal.

According to the present disclosure, there is provided an air-filled waveguide, AWG, assembly for use with a launcher-in-package semiconductor device, and comprising a stack of; a first laminate structure configured to be coupled to a semiconductor die, and having a first aperture therethrough; a second laminate structure affixed to the first laminate structure, having a second aperture, aligned with the first aperture, therethrough, and having a main AWG there-along; and a third laminate structure affixed to the second laminate structure, and having at least one bridging AWG there-along; wherein the AWG assembly is arranged to guide a microwave or millimetre-wave signal between the semiconductor die and the AWG in the second laminate, through the first and second aperture and along the bridging AWG.

A semiconductor device comprising: a substrate; an epitaxial layer arranged on the surface of the substrate, the epitaxial layer comprising: a first p-doped region, a second p-doped region and a third p-doped region arranged laterally with the second p-doped region positioned between; a first n-doped region positioned between the first p-doped region and the second p-doped region; a second n-doped region positioned between the second p-doped region and the third p-doped region; a metal contact layer arranged above the epitaxial layer, the metal contact layer comprising: a signal connection comprising a first metal contact and a second metal contact; and a ground metal contact, wherein the first metal contact is connected to the first p-doped region, the ground metal contact is connected to the second p-doped region and the second metal contact is connected to the third p-doped region.

The present disclosure relates to a sensor device comprising a sensor substrate, a sensor capacitor, a first sensor contact element, and a second sensor contact element, wherein the sensor capacitor is arranged on a surface, referred to as the first top surface, of the sensor substrate, wherein the sensor capacitor comprises a first sensor electrode and a second sensor electrode, wherein the second sensor electrode is arranged between the first sensor electrode and the first top surface of the sensor substrate such that a sensor cavity is provided between the two sensor electrodes, wherein both sensor contact elements are arranged on another surface, referred to as the first bottom surface, of the sensor substrate, wherein a first electrical interconnection extends through the sensor substrate from the first sensor electrode to the first sensor contact element, and wherein a second electrical interconnection extends through the sensor substrate from the second sensor electrode to the second sensor contact element.

The present disclosure relates to a circuit for a transmitter, the circuit comprising: a first supply terminal, a second supply terminal, a first output terminal, a second output terminal, wherein a first circuit string extends from the first supply terminal to a first node of the circuit, wherein a first transistor is integrated in the first circuit string, wherein a second circuit string extends from the second supply terminal to a second node of the circuit, wherein a second transistor is integrated in the second circuit string, wherein a third circuit string extends from the second supply terminal to the first node of the circuit, wherein a third transistor is integrated in the third circuit string, wherein a fourth circuit string extends from the first supply terminal to the second node of the circuit, wherein a second transistor is integrated in the second circuit string, wherein a first connection string extends from the first node to the first output terminal, wherein a first resistor is integrated into the first connection string, and wherein a second connection string extends from the second node to the second output terminal, wherein a second resistor is integrated into the second connection string.

A data processing system (100) includes a requestor (104), a split transaction interconnect (102), and address mapping circuitry (110). The requestor (104) issues block access requests (1) to a target peripheral (112). The target peripheral (112) includes a set of first-in first-out structures (FIFOs) (130) which buffer incoming or outgoing data. The split transaction interconnect (102) has a requestor port (122) coupled to the requestor (104) and a target port (124) coupled to the target peripheral (112). The target port (124) breaks a single block access request from the requestor into multiple smaller access requests (2) for the target peripheral (112), each including a corresponding access address, in which the corresponding access addresses of the multiple smaller access requests access consecutive address locations of the target peripheral (112). The address mapping circuitry (110) maps (3) each of the corresponding access addresses of the multiple smaller access requests generated from the single block access request access to a same register of a first FIFO (130) of the target peripheral (112).

One example discloses a power regulator, including: a power output node configured to be coupled to a high-side of a load; a load ground node configured to be coupled to a low-side of the load; a negative feedback node (Fbm) configured to form a negative feedback path when coupled to the low-side of the load; a controller configured to regulate voltages at the power output node and the load ground node in response to a voltage on the negative feedback path; a current source configured to inject a current at the negative feedback node (Fbm); and a detector circuit configured to monitor a voltage (VFbm) at the negative feedback node (Fbm); wherein the detector circuit is configured to switch the negative feedback node (Fbm) from the load ground node to an internal ground node, if the voltage (VFbm) exceeds a predetermined threshold voltage.

A packaged device includes a substrate, a die, a die flag, and a plurality of leads. The substrate has a lower surface and an upper surface opposite the lower surface. The die is arranged on the upper surface of the substrate. The die has a lower surface facing the upper surface of the substrate, and an upper surface opposite the lower surface. The die flag includes a cover portion which is arranged over the upper surface of the die. The cover portion has a lower surface and an upper surface opposite the lower surface. The lower surface of the cover portion faces the upper surface of the die. The plurality of leads is arranged around a periphery of the substrate. The plurality of leads includes a first lead connected to the die flag, and a second lead separated from the die flag. Each of the plurality of leads includes an outer portion which has a lower surface and an upper surface opposite the lower surface. The lower surfaces of the plurality of leads are coplanar with and separated from the lower surface of the substrate.

An interposer structure and fabrication method are disclosed by providing a wafer substrate in which is formed FEOL transistors with gate oxides having a minimum specified thickness, forming a BEOL ILD stack with interconnect structures on the wafer substrate, selectively etching openings extending at least part way down through the BEOL ILD stack, filling the etch openings with at least deposited aluminum to form a plurality of aluminum via structures and aluminum crack stop structures extending from a top surface of the BEOL ILD stack at least part way down through the BEOL ILD stack, and partially recessing a bottom surface of the wafer substrate layer to expose at least the aluminum crack stop structures.

A distributed radar system includes a reference clock source, a first radar front end, and a second radar front end. The reference clock source is configured to generate a reference clock signal. The first radar front end is configured to generate a first radar chirp signal based on the reference clock signal received from the reference clock source. The second radar front end is configured to generate a second radar chirp signal by modulating a time period between consecutive chirps in the second radar chirp signal based on a second frequency signal that is generated by upconverting the reference clock signal received from the reference clock source.

A frame structure is described for aggregated data over a half-duplex serial data channel. In an example a serial link modem includes a transmit modem coupled to a serial channel and configured to send serial data through the serial channel, and an aggregator coupled to the transmit modem and configured to form a first frame type of serial data configured for data other than Universal Serial Bus (USB) data having an upstream packet and a downstream packet and a total length of less than a latency of two USB hubs, and a second frame type of serial data configured for USB data, wherein the aggregator forms the second frame type upon receiving USB data and wherein the transmit modem is configured to transmit the first frame type through the serial channel, and to transmit the second frame type through the serial channel upon completion of transmitting the first frame.

Embodiments of a repeater, an embedded Universal Serial Bus (eUSB) repeater, and a method of operating a repeater are disclosed. In an embodiment, a repeater includes a buffer configured to store data that is received during a time distance between an input start and a frame slot start, a counter configured to calculate a waiting time before starting frame transmission, and a transmitter configured to transmit predefined data at the frame slot start over a repeater channel and to transmit the data that is stored in the buffer over the repeater channel after the waiting time from the frame slot start.

Embodiments of a repeater (402), an embedded Universal Serial Bus (eUSB) repeater (402), and a method of operating a repeater (402) are disclosed. In an embodiment, a repeater (402) includes a timer (436) configured to generate a counter value that represents a time distance between a frame slot and a packet start and a modem (418) configured to transmit output data containing the counter value over a repeater channel (420).

An apparatus and method for mitigating received interference. Baseband signals received during a time interval by a first MIMO receiver and a second MIMO receiver are provided as in-phase and quadrature input streams of a complex valued input of a Discrete Fourier Transform (DFT) circuit that calculates a complex valued DFT dataset of the complex valued input. A complex valued interference mitigated frequency domain dataset is produced by determining an interference mask from a spectrogram of the complex valued DFT dataset and applying the interference mask to the spectrogram. An inverse DFT of the complex valued interference mitigated frequency domain dataset determines an interference mitigated complex valued time domain data stream that contains a first interference mitigated time series as its real valued data and a second interference mitigated time series as its imaginary valued data.

An integrated circuit assembly includes first and second circuit portions, an interposer vertically disposed between the first and second circuit portions, the interposer having a plated through hole with a metallic sidewall, and a metallic pillar that extends through the plated through hole without touching the metallic sidewall. The metallic pillar and the plated through hole together form a vertical coaxial structure constructed and arranged to convey RF (radio frequency) signals between the first and second circuit portions. Embodiments are directed to both the integrated circuit assembly and to a method of manufacturing the integrated circuit assembly.

A receiver for a multi-antenna system and a method of generating channel estimations for the multi-antenna system are disclosed. In an embodiment, a receiver for a multi-antenna system comprises a detector configured to detect packets using signals received on a plurality of antennas, and a channel estimator configured to produce channel estimations based on the signals received on the plurality of antennas. The channel estimator is configured to estimate a relative channel with respect to first and second antenna using signals from first and second antennas to derive a relative channel estimation, estimate an antenna power for at least one of the first and second antennas using the signals from at least one of the first and second antennas, and compute channel estimations for the first and second antennas using the relative channel estimation and the antenna power for the at least one of the first and second antennas.

A dual-personal area network (PAN) router receives one or more fields of a frame of a PAN on a channel; determines that the dual-PAN router is not to route the frame to a PAN based on the one or more received fields and before the entire frame is received; and switches to receive on another channel for a transmission duration of the frame by an end device in response to the determination.

A PLL method and apparatus are provided with a phase-frequency detector, charge pump, loop filter, voltage controlled ring oscillator, and feedback clock divider that is configured with a multiplication feedback integer (MFI) value for generating a PLL clock output signal, where the charge pump includes a current bias circuit which dynamically scales an input reference current under control of the MFI value to generate the charge pump control current so that a PLL bandwidth of the PLL adaptively tracks a frequency of the input reference signal and a frequency of the PLL clock output signal.

Systems and methods of controlling buck-boost converters are provided herein that include controllers having two delay line based compensators in series. The two delay line based compensators may include a voltage loop delay line compensator and a current loop delay line compensator. The voltage loop delay line compensator may be the first compensator and the current loop delay line compensator may be the second compensator. Each delay line based compensator may include a pre-condition stage, a pre-condition output-to-pulse conversion stage, a time difference comparison stage, a pulse to current conversion stage, and a current to voltage conversion stage.

Techniques for removing phase noise from baseband signals in a radar system are disclosed. In one example, a received baseband signal is derotated using parameters of a spill-over signal to generate a derotated signal. The derotated signal is decomposed into a real component and an imaginary component. A transform is applied on the real component to produce a transformed signal. A phase noise signal estimate is generated by subtracting the transformed signal from the imaginary component. The phase noise signal estimate is applied to the received baseband signal to generate a phase noise mitigated signal.

An electronic circuit includes a fast-settling threshold estimator for determining a fast-settling threshold voltage which includes a maximum peak detector that receives an analog signal containing digital data and produces an estimate of a maximum value of the analog signal; a differentiator that produces an output voltage responsive to a change in the estimate of a maximum value of the analog signal; a preselected voltage coupled to a comparator that outputs a pulse when the output voltage is greater than the preselected voltage; a minimum peak detector that produces an estimate of a minimum value of the analog signal; and an averaging circuit that produces a weighted average of the estimate of a maximum value of the analog signal and the estimate of a minimum value of the analog signal. In one embodiment, the fast-settling threshold estimator is coupled to a bit slicer and to a RF receiver.

A continuous-time delta-sigma modulator (CTDSM) system includes a quantizer, an update block, a switching block, a summation block, and a feedback path. The quantizer is configured to quantize an analog input signal into one or more thermometer-coded digital signals. The update block is configured to generate control signals based on the thermometer-coded digital signals. The switching block is configured to route the thermometer-coded digital signals to a plurality of digital-to-analog converter (DAC) elements based on the control signals. The plurality of DAC elements is configured to convert the thermometer-coded digital signals into analog outputs. The summation block is configured to combine the analog outputs from the plurality of DAC elements to produce a final analog output. The feedback path is configured to use the final analog output as a feedback signal for the CTDSM system.

A transmitter reduces the Crest Factor of an input signal by identifying potentially hidden peaks and by efficiently identifying the delay between an observed peak at a specified sampling rate and a corresponding true peak generated after upsampling. The transmitter rescales, based on a programmable rescaling parameter, a threshold for peak detection, and employs the rescaled threshold to identify one or more candidate peaks of the input signal. After the transmitter has rescaled the one or more candidate peaks based on the estimated fractional delay between the candidate peaks and the corresponding true peaks, the peaks are reevaluated based on the original threshold.

A system and method is presented for determining a plurality of MIMO virtual antenna arrays. Each virtual antenna array of the plurality of MIMO virtual antenna arrays is associated with a subset of a plurality of transmit antennas (102) and a subset of a plurality of receive antennas (104). Signals received by the plurality of receive antennas are used to determine signal spectrums (208) for each MIMO virtual antenna array of the plurality of MIMO virtual antenna arrays. Each signal spectrum includes signal magnitude values and has associated angle values, wherein main lobe (210) positions of the signal spectrums of the plurality of MIMO virtual antenna arrays are at a same angle across all signal spectrums and sidelobe (212) positions of the signal spectrums are not at the same angle across all signal spectrums. A first combined MIMO virtual antenna array signal spectrum (409) is determined by combining minimum values of the signal spectrums at each angle value. The first combined MIMO virtual antenna array signal spectrum is used to detect an object.

One or more integrated capacitors can be formed within the molding material(s) of a molded electronic device package. An electronic device such as a semiconductor die is surrounded by a first volume of molding material and a first capacitor plate is formed on a top surface of the first volume of molding material above the electronic device. A second volume of molding material is formed above the first capacitor plate and a second capacitor plate is formed on a top surface of the second volume of molding material which separates the second capacitor plate from the first capacitor plate.

Systems and methods for an implicit frequency multiplier are described. In some embodiments, an implicit frequency multiplier may include a cross-coupled oscillator having a transistor pair, a primary coil coupled to source terminals of the transistor pair, and a secondary coil magnetically coupled to the primary coil. In another embodiment, a method may include operating a cross-coupled oscillator having a transistor pair and extracting a harmonic component of a current flowing through the cross-coupled oscillator using a transformer coupled to source terminals of the transistor pair.

A method for implementing software defined vehicle, SDV, application programming interfaces, APIs, using an automotive open system architecture, AUTOSAR, classic platform, CP, is described. The method includes distributing SDV APIs on at least one client-server, C-S, interface located between: a SDV sensor software component, SWC, a SDV central compute unit, CCU, SWC, and a SDV actuator SWC. The method also includes developing an API-Data Distribution Service, DDS, transformer and mapping, by the API-DDS, the at least one C-S interface to DDS topics.

Embodiments of a wireless device, a wireless access point (AP), and a method for wireless communications are disclosed. In an embodiment, a wireless device includes a controller configured to map, based on station (STA) priority and latency consideration, downlink (DL) traffic of STAs to different transmit queues and to adjust Enhanced Distributed Channel Access (EDCA) parameters for the different transmit queues and a wireless transceiver configured to implement wireless channel access based on the adjusted EDCA parameters to communicate with the STAs.

The present specification relates to package semiconductor devices and methods of manufacture thereof. According to a first aspect of the present disclosure, there is provided a packaged semiconductor device comprising a semiconductor die, a first molding compound encapsulating the semiconductor die, a first set of interconnecting solder balls, at least one redistribution layer, such redistribution layer connecting the semiconductor die to the interconnecting solder balls. The packaged semiconductor device further comprises at least one channel extending from the at least one redistribution layer to an exterior of the packaged semiconductor device wherein the at least one redistribution layer comprises pipes coupled to the at least one channel, such pipes transporting steam or moisture or thermal fluids from the at least one channel to the at least one redistribution layer or from the at least one redistribution layer to the at least one channel.

An integrated circuit and associated method of operation are provided for a target component coupled over a bus having multiple data path lines and a clock path line to an initiator component which generates a plurality of data bit signals and a first clock timing signal for transmission in parallel over the bus, where the initiator component includes transmit circuitry to launch a first plurality of even data bit signals over a first subset of the plurality of data path lines in response to a rising clock edge of the first clock signal and to launch a second plurality of odd data bit signals over a second subset of the plurality of data path lines in response to a falling clock edge of the first clock signal.

An electronic module includes an electronic circuit and a controller circuit. The electronic circuit includes first and second reconfigurable devices, each with an electronic component that is capable of being configured into a plurality of states. The controller circuit includes an external control signal interface that receives encoded state information, and an enable signal input that receives an enable signal indicating whether the electronic circuit is in an active or inactive operational mode. After the controller circuit has received the encoded state information, and the enable signal indicates that the electronic circuit has transitioned from the active operational mode into the inactive operational mode, the controller circuit sends the encoded state information through an internal control signal interface to the reconfigurable devices. The encoded state information causes the reconfigurable devices to configure their electronic components into component states that correspond to the selected circuit state.

Power amplifier assemblies and multiple-stage amplifier systems include first and second semiconductor dies, each of which includes an integrated transistor. The second semiconductor die is physically and electrically coupled to a die-mounting interface at a mounting surface of the first semiconductor die in a "flip-chip" orientation. This arrangement provides a multiple-stage amplifier that includes the integrated transistor of the first semiconductor die coupled in a cascade arrangement with the integrated transistor of the second semiconductor die. The first and second semiconductor dies may be formed from different semiconductor materials.

A semiconductor die includes a transistor including a source region, a drain region, a channel between the source region and the drain region, and a gate structure overlying the channel. The gate structure is configured to control a conductivity of the channel vis an electrical voltage applied thereto. The semiconductor die includes a first gate terminal electrically connected to the gate structure and a first harmonic filter inductor formed in a body of the semiconductor die. The first harmonic filter inductor is electrically connected to the first gate terminal. The semiconductor die includes a first harmonic filter capacitor formed in the body of the semiconductor die. The first harmonic filter capacitor includes a first capacitor plate electrically connected to the first harmonic filter inductor and a second capacitor plate connected to a ground reference node.

Modified fabrication processes for transistors with field plates such as gallium nitride heterostructure transistors reduce exposure of surfaces near the transistor channel to mitigate the risk of damage and performance degradation arising from exposure to sensitive surfaces and interfaces to high temperatures and etch-induced damage. Such processes include sequencing of dielectric formation and patterning that allows formation of gate and field plate electrodes after high-temperature processing steps. Passivation layers which can also function as etch stop layers for other dielectric materials enable protection of the channel region during dry etching processes followed by selective wet etching to remove the passivation layer immediately prior to gate electrode formation and other steps. Such methods can also enable surface modification processes to be performed to selectively enhance channel conductivity followed by passivation of modified surfaces to preserve enhanced conductivity during subsequent processing steps.

There is disclosed a method for transferring an embedded subscriber identity module, eSIM, subscriber profile from a first mobile device to a second mobile device, which are within near field communication, NFC, range to each other using a profile server. The method comprises performing a transfer authentication of the first mobile device and the second mobile device using NFC technology. In response to the successful transfer authentication, profile identification information is transmitted from the first mobile device to the second mobile device using optical technology. Then the first mobile device generates an authentication key based on the subscriber profile and transmits it to the second mobile device. The second mobile device then downloads the subscriber profile from the profile server and the subscriber profile is deleted on the first mobile device. Further mobile devices and a computer program product are disclosed.

Modified fabrication processes for transistors with field plates such as gallium nitride heterostructure transistors reduce exposure of surfaces near the transistor channel to mitigate the risk of damage and performance degradation arising from exposure to sensitive surfaces and interfaces to high temperatures and etch-induced damage. Such processes include sequencing of dielectric formation and patterning that allows formation of gate and field plate electrodes after high-temperature processing steps. Passivation layers which can also function as etch stop layers for other dielectric materials enable protection of the channel region during dry etching processes followed by selective wet etching to remove the passivation layer immediately prior to gate electrode formation and other steps. Such methods can also enable surface modification processes to be performed to selectively enhance channel conductivity followed by passivation of modified surfaces to preserve enhanced conductivity during subsequent processing steps.

Modified fabrication processes for transistors with field plates such as gallium nitride heterostructure transistors reduce exposure of surfaces near the transistor channel to mitigate the risk of damage and performance degradation arising from exposure to sensitive surfaces and interfaces to high temperatures and etch-induced damage. Such processes include sequencing of dielectric formation and patterning that allows formation of gate and field plate electrodes after high-temperature processing steps. Passivation layers which can also function as etch stop layers for other dielectric materials enable protection of the channel region during dry etching processes followed by selective wet etching to remove the passivation layer immediately prior to gate electrode formation and other steps. Such methods can also enable surface modification processes to be performed to selectively enhance channel conductivity followed by passivation of modified surfaces to preserve enhanced conductivity during subsequent processing steps.

The present disclosure relates to an oscillator, such as a series resonance oscillator, which includes an inverter , non-inverting buffer circuitry including, a first transistor having a first gate terminal and a first source terminal, and a second transistor having a second gate terminal and a second source terminal, a first inductor-capacitor (LC) tank coupled between the inverter and an output of the non-inverting buffer circuitry, and a second LC tank coupled between the inverter and an input of the non-inverting buffer circuitry, where the first gate and second gate terminals are coupled to the input of the non-inverting buffer circuitry, the first and second source terminals are coupled to the output of the non-inverting buffer circuitry, the first and second source terminals are separately direct-current (DC)-biased, and the first and second gate terminals are separately DC-biased.