NXP USA Patente

A transmitter reduces the Crest Factor of an input signal by identifying potentially hidden peaks and by efficiently identifying the delay between an observed peak at a specified sampling rate and a corresponding true peak generated after upsampling. The transmitter rescales, based on a programmable rescaling parameter, a threshold for peak detection, and employs the rescaled threshold to identify one or more candidate peaks of the input signal. After the transmitter has rescaled the one or more candidate peaks based on the estimated fractional delay between the candidate peaks and the corresponding true peaks, the peaks are reevaluated based on the original threshold.

A continuous-time delta-sigma modulator (CTDSM) system includes a quantizer, an update block, a switching block, a summation block, and a feedback path. The quantizer is configured to quantize an analog input signal into one or more thermometer-coded digital signals. The update block is configured to generate control signals based on the thermometer-coded digital signals. The switching block is configured to route the thermometer-coded digital signals to a plurality of digital-to-analog converter (DAC) elements based on the control signals. The plurality of DAC elements is configured to convert the thermometer-coded digital signals into analog outputs. The summation block is configured to combine the analog outputs from the plurality of DAC elements to produce a final analog output. The feedback path is configured to use the final analog output as a feedback signal for the CTDSM system.

An electronic circuit includes a fast-settling threshold estimator for determining a fast-settling threshold voltage which includes a maximum peak detector that receives an analog signal containing digital data and produces an estimate of a maximum value of the analog signal; a differentiator that produces an output voltage responsive to a change in the estimate of a maximum value of the analog signal; a preselected voltage coupled to a comparator that outputs a pulse when the output voltage is greater than the preselected voltage; a minimum peak detector that produces an estimate of a minimum value of the analog signal; and an averaging circuit that produces a weighted average of the estimate of a maximum value of the analog signal and the estimate of a minimum value of the analog signal. In one embodiment, the fast-settling threshold estimator is coupled to a bit slicer and to a RF receiver.

The present specification relates to package semiconductor devices and methods of manufacture thereof. According to a first aspect of the present disclosure, there is provided a packaged semiconductor device comprising a semiconductor die, a first molding compound encapsulating the semiconductor die, a first set of interconnecting solder balls, at least one redistribution layer, such redistribution layer connecting the semiconductor die to the interconnecting solder balls. The packaged semiconductor device further comprises at least one channel extending from the at least one redistribution layer to an exterior of the packaged semiconductor device wherein the at least one redistribution layer comprises pipes coupled to the at least one channel, such pipes transporting steam or moisture or thermal fluids from the at least one channel to the at least one redistribution layer or from the at least one redistribution layer to the at least one channel.

Embodiments of a wireless device, a wireless access point (AP), and a method for wireless communications are disclosed. In an embodiment, a wireless device includes a controller configured to map, based on station (STA) priority and latency consideration, downlink (DL) traffic of STAs to different transmit queues and to adjust Enhanced Distributed Channel Access (EDCA) parameters for the different transmit queues and a wireless transceiver configured to implement wireless channel access based on the adjusted EDCA parameters to communicate with the STAs.

A method for implementing software defined vehicle, SDV, application programming interfaces, APIs, using an automotive open system architecture, AUTOSAR, classic platform, CP, is described. The method includes distributing SDV APIs on at least one client-server, C-S, interface located between: a SDV sensor software component, SWC, a SDV central compute unit, CCU, SWC, and a SDV actuator SWC. The method also includes developing an API-Data Distribution Service, DDS, transformer and mapping, by the API-DDS, the at least one C-S interface to DDS topics.

Systems and methods for an implicit frequency multiplier are described. In some embodiments, an implicit frequency multiplier may include a cross-coupled oscillator having a transistor pair, a primary coil coupled to source terminals of the transistor pair, and a secondary coil magnetically coupled to the primary coil. In another embodiment, a method may include operating a cross-coupled oscillator having a transistor pair and extracting a harmonic component of a current flowing through the cross-coupled oscillator using a transformer coupled to source terminals of the transistor pair.

A system and method is presented for determining a plurality of MIMO virtual antenna arrays. Each virtual antenna array of the plurality of MIMO virtual antenna arrays is associated with a subset of a plurality of transmit antennas (102) and a subset of a plurality of receive antennas (104). Signals received by the plurality of receive antennas are used to determine signal spectrums (208) for each MIMO virtual antenna array of the plurality of MIMO virtual antenna arrays. Each signal spectrum includes signal magnitude values and has associated angle values, wherein main lobe (210) positions of the signal spectrums of the plurality of MIMO virtual antenna arrays are at a same angle across all signal spectrums and sidelobe (212) positions of the signal spectrums are not at the same angle across all signal spectrums. A first combined MIMO virtual antenna array signal spectrum (409) is determined by combining minimum values of the signal spectrums at each angle value. The first combined MIMO virtual antenna array signal spectrum is used to detect an object.

One or more integrated capacitors can be formed within the molding material(s) of a molded electronic device package. An electronic device such as a semiconductor die is surrounded by a first volume of molding material and a first capacitor plate is formed on a top surface of the first volume of molding material above the electronic device. A second volume of molding material is formed above the first capacitor plate and a second capacitor plate is formed on a top surface of the second volume of molding material which separates the second capacitor plate from the first capacitor plate.

An integrated circuit and associated method of operation are provided for a target component coupled over a bus having multiple data path lines and a clock path line to an initiator component which generates a plurality of data bit signals and a first clock timing signal for transmission in parallel over the bus, where the initiator component includes transmit circuitry to launch a first plurality of even data bit signals over a first subset of the plurality of data path lines in response to a rising clock edge of the first clock signal and to launch a second plurality of odd data bit signals over a second subset of the plurality of data path lines in response to a falling clock edge of the first clock signal.

An electronic module includes an electronic circuit and a controller circuit. The electronic circuit includes first and second reconfigurable devices, each with an electronic component that is capable of being configured into a plurality of states. The controller circuit includes an external control signal interface that receives encoded state information, and an enable signal input that receives an enable signal indicating whether the electronic circuit is in an active or inactive operational mode. After the controller circuit has received the encoded state information, and the enable signal indicates that the electronic circuit has transitioned from the active operational mode into the inactive operational mode, the controller circuit sends the encoded state information through an internal control signal interface to the reconfigurable devices. The encoded state information causes the reconfigurable devices to configure their electronic components into component states that correspond to the selected circuit state.

Power amplifier assemblies and multiple-stage amplifier systems include first and second semiconductor dies, each of which includes an integrated transistor. The second semiconductor die is physically and electrically coupled to a die-mounting interface at a mounting surface of the first semiconductor die in a "flip-chip" orientation. This arrangement provides a multiple-stage amplifier that includes the integrated transistor of the first semiconductor die coupled in a cascade arrangement with the integrated transistor of the second semiconductor die. The first and second semiconductor dies may be formed from different semiconductor materials.

A USB-capable device includes an eUSB device repeater includes D+ and D- lines for communicating via a USB bus, and eD+ and eD- lines for communicating via an eUSB bus. The repeater includes a squelch detector for detecting a differential voltage between the D+ and D- lines and comparing it to a squelch threshold voltage based on a selectively variable squelch threshold voltage level at the squelch detector. During USB bus reset the squelch detector compares the differential voltage to a chirp-specific squelch threshold voltage level and the squelch signal indicates no K chirp or J chirp activity on the USB bus. The repeater thereby avoids false detections of invalid chirps and more reliably detects end of USB bus resets. A USB2 bus reset sequence windowing scheme is also provided.

A semiconductor device configured to reduce the size of passive components monolithically integrated with active components includes a semiconductor substrate that includes an active region, a first current-carrying electrode formed in the active region, a second current-carrying electrode formed in the active region, a control electrode configured to control current flow between the first current-carrying electrode and the second current-carrying electrode. A capacitor structure is formed over the semiconductor substrate adjacent the active region. The capacitor structure includes a first capacitor region that includes a portion of a first conductive layer formed over the semiconductor substrate. A first insulating layer is formed over the first capacitor region. A second capacitor region that includes a portion of a second conductive layer is formed over the first insulating layer. In an embodiment, a contact area is coupled to the capacitor structure.

Modified fabrication processes for transistors with field plates such as gallium nitride heterostructure transistors reduce exposure of surfaces near the transistor channel to mitigate the risk of damage and performance degradation arising from exposure to sensitive surfaces and interfaces to high temperatures and etch-induced damage. Such processes include sequencing of dielectric formation and patterning that allows formation of gate and field plate electrodes after high-temperature processing steps. Passivation layers which can also function as etch stop layers for other dielectric materials enable protection of the channel region during dry etching processes followed by selective wet etching to remove the passivation layer immediately prior to gate electrode formation and other steps. Such methods can also enable surface modification processes to be performed to selectively enhance channel conductivity followed by passivation of modified surfaces to preserve enhanced conductivity during subsequent processing steps.

The present disclosure relates to an oscillator, such as a series resonance oscillator, which includes an inverter , non-inverting buffer circuitry including, a first transistor having a first gate terminal and a first source terminal, and a second transistor having a second gate terminal and a second source terminal, a first inductor-capacitor (LC) tank coupled between the inverter and an output of the non-inverting buffer circuitry, and a second LC tank coupled between the inverter and an input of the non-inverting buffer circuitry, where the first gate and second gate terminals are coupled to the input of the non-inverting buffer circuitry, the first and second source terminals are coupled to the output of the non-inverting buffer circuitry, the first and second source terminals are separately direct-current (DC)-biased, and the first and second gate terminals are separately DC-biased.

A system and method provides a substrate having a first surface and a second surface. A first plurality of contact pads are formed on the first surface of the substrate. A first redistribution layer is formed over the first surface of the substrate by mounting a plurality of metal balls to contact pads of the first plurality of contact pads on the first surface of the substrate, wherein the plurality of metal balls include copper, forming a layer of encapsulant surrounding at least a portion of the plurality of metal balls, depositing a dielectric layer over the plurality of metal balls and the encapsulant, and forming a second plurality of contact pads over the dielectric layer, wherein each contact pad of the second plurality of contact pads is connected through openings in the dielectric layer to metal balls of the plurality of metal balls.

Systems and methods for Power Factor Correction (PFC) circuits are described. In various implementations, these systems and methods may be used to power the operation of any component of any electronic device. In an illustrative, non-limiting embodiment, a power supply may include: a power converter having a high-side switch, a low-side switch coupled to the high-side switch, and a bootstrap capacitor coupled between the high-side switch and the low-side switch; and a control circuit coupled to the low-side switch, the control circuit configured to activate the low-side switch and charge the bootstrap capacitor without changing an output voltage of the power converter.

An integrated circuit device is disclosed which has a substrate layer with input and output terminals and an array of FET elements formed over a top surface of the substrate layer, where each FET element includes an elongated source contact with opposed sides extending longitudinally between a first source end that is proximate to the output terminal layer and a second source end that is proximate to the input terminal; a U-shaped drain contact positioned to enclose the first source end and located to define a U-shaped channel region between the elongated source contact and the U-shaped drain contact; and a U-shaped gate contact positioned over the U-shaped channel region and between the U-shaped drain contact and the elongated source contact, where the U-shaped gate contact and U-shaped drain contact each have a closed end located in the peripheral ancillary region between the first source end and the output terminal.

A semiconductor die includes a transistor including a source region, a drain region, a channel between the source region and the drain region, and a gate structure overlying the channel. The gate structure is configured to control a conductivity of the channel vis an electrical voltage applied thereto. The semiconductor die includes a first gate terminal electrically connected to the gate structure and a first harmonic filter inductor formed in a body of the semiconductor die. The first harmonic filter inductor is electrically connected to the first gate terminal. The semiconductor die includes a first harmonic filter capacitor formed in the body of the semiconductor die. The first harmonic filter capacitor includes a first capacitor plate electrically connected to the first harmonic filter inductor and a second capacitor plate connected to a ground reference node.

Modified fabrication processes for transistors with field plates such as gallium nitride heterostructure transistors reduce exposure of surfaces near the transistor channel to mitigate the risk of damage and performance degradation arising from exposure to sensitive surfaces and interfaces to high temperatures and etch-induced damage. Such processes include sequencing of dielectric formation and patterning that allows formation of gate and field plate electrodes after high-temperature processing steps. Passivation layers which can also function as etch stop layers for other dielectric materials enable protection of the channel region during dry etching processes followed by selective wet etching to remove the passivation layer immediately prior to gate electrode formation and other steps. Such methods can also enable surface modification processes to be performed to selectively enhance channel conductivity followed by passivation of modified surfaces to preserve enhanced conductivity during subsequent processing steps.

There is disclosed a method for transferring an embedded subscriber identity module, eSIM, subscriber profile from a first mobile device to a second mobile device, which are within near field communication, NFC, range to each other using a profile server. The method comprises performing a transfer authentication of the first mobile device and the second mobile device using NFC technology. In response to the successful transfer authentication, profile identification information is transmitted from the first mobile device to the second mobile device using optical technology. Then the first mobile device generates an authentication key based on the subscriber profile and transmits it to the second mobile device. The second mobile device then downloads the subscriber profile from the profile server and the subscriber profile is deleted on the first mobile device. Further mobile devices and a computer program product are disclosed.

Modified fabrication processes for transistors with field plates such as gallium nitride heterostructure transistors reduce exposure of surfaces near the transistor channel to mitigate the risk of damage and performance degradation arising from exposure to sensitive surfaces and interfaces to high temperatures and etch-induced damage. Such processes include sequencing of dielectric formation and patterning that allows formation of gate and field plate electrodes after high-temperature processing steps. Passivation layers which can also function as etch stop layers for other dielectric materials enable protection of the channel region during dry etching processes followed by selective wet etching to remove the passivation layer immediately prior to gate electrode formation and other steps. Such methods can also enable surface modification processes to be performed to selectively enhance channel conductivity followed by passivation of modified surfaces to preserve enhanced conductivity during subsequent processing steps.

An integrated circuit is provided with a signal node/IO pad in an output buffer that is protected by a current injection protection circuit which includes first and second comparators connected between a first voltage supply and a second voltage supply to generate first and second control signals in response to, respectively, a positive or negative injected current at the signal node, and which also includes a pre-driver stack of transistors which generate, respectively, a positive gate control signal and negative gate control signal, and which also includes a multiplex selection circuit connected to output the positive gate control signal and negative gate control signal to the output buffer to clamp signal node to a first clamped voltage if a voltage on the signal node exceeds the first supply voltage or to a second clamped voltage if a voltage on the signal node falls below the second supply voltage.

A unity gain buffer including a differential amplifier, detector and feedback circuitry, and an output stage. The differential amplifier receives a difference voltage between a buffer input and output, is coupled to a control node for modulating a current of the differential amplifier, and drives an output node. The detector and feedback circuitry has an input coupled to the buffer input and output and has an output coupled to the control node. The output stage has an input coupled to the output drive node and has an output coupled to the buffer output node. The differential amplifier draws minimal current when the difference voltage is substantially zero and increases current when the difference voltage increases causing the output stage to drive a voltage of the buffer output node back to a voltage of the buffer input node. At least one current booster or a preset load may be added.

Embodiments of a control circuit for a flyback converter and a method for controlling a flyback converter are disclosed. In an embodiment, a control circuit includes an integrator circuit configured to output a ramp signal in response to an AC feedback signal from a primary side of a flyback converter, a threshold generator circuit configured to output a threshold voltage in response to the ramp signal, wherein the threshold voltage is generated as a function of a peak voltage of the ramp signal, a comparator circuit configured to compare the ramp signal to the threshold voltage and to output a sampling signal when the ramp signal drops below the threshold voltage, and a sample and hold circuit configured to sample the AC feedback signal in response to the sampling signal and to output a sample of the AC feedback signal that is used to control the flyback converter.

This disclosure generally relates to an apparatus and a method for amplitude and duration comparison of an analog signal, in particular for analog signals with noise.

A data processing system includes a shared memory, a plurality of execution environments (EEs) which access the shared memory, and a cache which caches information stored in the shared memory. A first encryption engine is coupled between the plurality of EEs and the cache, and a second encryption engine is coupled between the cache and the shared memory. An encryption control circuit is configured to store a unique key corresponding to each EE of the plurality of EEs and provide a current EE key uniquely corresponding to a currently executing EE of the plurality of EEs to the first and second encryption engines. Any data loaded into the cache during execution of the currently executing EE is encrypted using the current EE key and stored as encrypted data in the cache, and any data returned from the cache to the currently executing EE is decrypted using the current EE key.

A radio frequency (RF) power amplifier (100, 200) and a packaged power amplifier device include a transistor (130, 230, 530) and an input impedance matching circuit (110, 210, 310) coupled between an amplifier input and an input terminal of the transistor. The input impedance matching circuit includes first, second, third, and fourth inductive elements (111, 112, 113, 114, 211, 212, 213, 214, 411, 412, 413, 414) coupled in series, with first, second, third intermediate nodes (118, 119, 120, 218, 219, 220, 418, 419, 420) between adjacent inductive elements. First, second, and third capacitors (115, 116, 117, 215, 216, 217, 415, 416, 417) are coupled between the first, second, and third intermediate nodes, respectively, and a ground reference node.

Radiofrequency systems for use in advanced driver assistance systems (ADAS) can include a mixture of high frequency (e.g., above 1 GHz) analog and components and lower-frequency digital devices mounted on one main circuit board. Cost savings can be achieved by providing high-frequency signal paths on an interposer circuit board that is mounted to the main circuit board and couples devices requiring high-frequency signalling (e.g., distributing a local oscillator signal to several devices forming part of a cascaded radar system). The interposer is fabricated from special purpose materials suitable for routing high frequency signals with low loss, while the main circuit board can be fabricated from commodity materials suitable for lower frequency applications.

A power factor correction (PFC) circuit is described which includes an inductor configured to generate an output voltage to an output load, an output voltage sensor, an output current measurement circuit, a first filter capacitor coupled between the output voltage and a first input node, a second filter capacitor between the first input node and a low voltage, and a first input node voltage sensor. Capacitor compensation logic is configured to receive the output current and the first input node voltage, to compensate the output current for the first filter capacitor and the second filter capacitor using the first input node voltage, and to generate a corrected output current. A control system is coupled to receive the output voltage and the corrected output current and configured to generate control signals to control the output voltage.

An apparatus, such as a subsampling phase locked loop (PLL), includes a digitally controlled oscillator (DCO), a digital phase detector, and a digital filter. The DCO generates a first signal having a phase based on a second signal provided to the DCO. The digital phase detector generates a third signal that represents a phase offset between a reference clock signal and the first signal. The digital filter generates the second signal by filtering out high-frequency fluctuations in the third signal.

An integrated circuit is disclosed which includes a stacked P+ substrate, n-type epitaxial layer, and one or more p-type epitaxial layers, with a buried layer located in the one or more p-type epitaxial layers to be adjacent to the n-type epitaxial layer, a central isolated region located in the one or more p-type epitaxial layers to be positioned over the buried layer, one or more concentric shallow isolation ring structures positioned to surround the central isolated region and to extend down through the buried layer and into the n-type epitaxial layer, and a concentric deep poly isolation structure positioned to surround the central isolated region and the one or more concentric shallow isolation ring structures and to extend down through the n-type epitaxial layer and into the P+ substrate, wherein the concentric deep poly isolation structure include one or more polysilicon layers that are shorted to the P+ substrate.

A current mirror circuit (200) comprises: a first current source (206) for providing a first reference current (IB1); a first transistor (M1, 222) having a control terminal (226), a first current terminal (228) coupled to receive the first reference current (IB1), and a second current terminal (230) coupled to a reference potential (VEE); a second transistor (M2, 224) having a control terminal (232) coupled to the control terminal (226) of the first transistor (M1, 222), a first current terminal (234) coupled to an output node (GL, 208) of the current mirror circuit (200), and a second current terminal (236) coupled to the reference potential (VEE); and matching circuitry (300) having an input (302) coupled to the output node (GL, 208) of the current mirror circuit (200), and an output (304) coupled to the first current terminal (228) of the first transistor (M1, 222), the matching circuitry (300) being configured to provide, at the first current terminal (228) of the first transistor (M1, 222), a replica voltage corresponding to a voltage at the output node (GL, 208) of the current mirror circuit (200).

Aspects of the subject disclosure may include, for example, a packaged integrated circuit device that includes two galvanically isolated integrated circuit die. The integrated circuit die include conductive coils that can be inductively coupled for wireless communications between the two galvanically isolated integrated circuit die. A first integrated circuit die is mounted to a lead frame and a second integrated circuit die is surrounded by a molding compound structure and an insulating layer. The second integrated circuit is adhered to the first integrated circuit in a manner that aligns the conductive coils and provides galvanic isolation between the two integrated circuit die. Other embodiments are disclosed.

This disclosure relates to a power module, a power converter, a method, and a computer program for supplying a target amount of power across different power ranges using a hybrid circuit architecture.

The present disclosure relates to a communication module comprising: a first communication interface, a second communication interface, and a processing unit, wherein the first communication interface is configured to receive an instruction message according to a first communication protocol, wherein the instruction message represents a predefined reference instruction, wherein the communication module is configured to detect an uninterrupted idle time during which the communication module does not receive a message via the first communication interface, and wherein the processing unit is configured, in response to the idle time exceeding a predefined dead time, to control the second communication interface such that the second communication interface transmits a command message according to a second communication protocol, wherein the command message represents the reference instruction. The present disclosure also relates to a communication system, which includes the communication module, and a method for the communication module.

A packaged device includes molding compound, a first semiconductor die disposed within the molding compound and a second semiconductor die disposed within the molding compound. The molding compound galvanically isolates the first and second semiconductor dies. The packaged device further includes communication coils constructed and arranged to provide communication between the first and second semiconductor dies through inductive coupling, at least one of the communication coils being fabricated within the molding compound.

Aspects of the subject disclosure may include, for example, a packaged integrated circuit device that includes two galvanically isolated integrated circuit die. The integrated circuit die include conductive coils that can be inductively coupled for wireless communications between the two galvanically isolated integrated circuit die. One of the integrated circuit die is flip chip mounted to the other integrated circuit die with the coils facing each other across an insulating layer that includes routing to provide power to the flip chip mounted integrated circuit die. Other embodiments are disclosed.

Systems and methods for pin lift detection compensation in Low Dropout (LDO) regulators. In an illustrative, non-limiting embodiment, a System-On-Chip (SoC) may include: a circuit; and an LDO regulator coupled to the circuit, where the LDO includes a transistor having a first terminal coupled to a first voltage rail and a second terminal coupled to the circuit, where the second terminal is configured to receive a probe current produced from a second voltage rail, and where the first voltage rail is coupled to a compensating current source configured to draw a compensating charge equal to or greater than a charge imparted upon the second terminal by the probe current.