NXP USA Patente

The present disclosure relates to a driver system, the driver system comprising: a driver circuit, a compensation circuit, a first driver terminal, a second driver terminal, and a third driver terminal, wherein the driver circuit comprises a first switching transistor and a first current mirror, wherein the first current mirror comprises a first reference transistor and a first mirror transistor, wherein the first reference transistor is integrated into a first circuit branch of the driver circuit, wherein the first switching transistor and the first mirror transistor are integrated into a second circuit branch of the driver circuit, such that the first switching transistor and the first mirror transistor are connected in series, wherein the compensation circuit is coupled to the gate terminal of the first mirror transistor, and wherein a second switching transistor and a compensation capacitor are integrated in the compensation branch.

An apparatus and method for synchronizing a reference oscillator. A frequency of an adjustable frequency reference oscillator is adjusted based on an indication that radio signal processing is inactive and based on a phase error between a synchronized frequency reference signal and a frequency based on a synchronization reference signal. The adjustable frequency reference oscillator provides the synchronized frequency reference signal for a radio frequency circuit and a timing signal indicates whether radio signal processing by a radio frequency circuit is active or inactive. Adjustment of the frequency of the adjustable frequency reference oscillator is inhibited based on the timing signal indicating that radio signal processing is active.

A dual-path phase-locked loop (PLL) is disclosed. The dual-path PLL converts, based on a masking value, a pulse signal to a masked pulse signal such that the masked pulse signal comprises one or more unmasked pulses and one or more masked pulses of the pulse signal. An integral current is generated, based on the masked pulse signal in a manner such that that an average current value of the integral current reaches a desired value over a predefined number of cycles of the pulse signal and an optimal peaking in the dual-path PLL is achieved.

An apparatus and method for aggregating multiple data streams over a single aggregate link. Two or more serial communication signals are received. A minimum effective transfer rate (M) for a single aggregate link for a given frame structure is determined. A minimum frame length (FLEN) based on a combination of sync bits (S), propagation delay (PD), turnaround (TA), and payload (P) is set. A transfer rate per bit (R) based on the payload (P) and minimum frame length (FLEN) is evaluated. In response to the transfer rate per bit (R) being less than or equal to the minimum effective transfer rate (M), increment the payload (P) of the given frame structure and repeat the steps above. Otherwise, the serial communication signals are encoded to generate an encoded serial communication signal, wherein the encoded serial communication signal enables the reconstruction of the serial communication signals independent of a clock signal.

A method, system, and apparatus for bandsteering a client station to an access point. A non-6 GHz AP receives a plurality of probe requests from the client station and determines that the client station is operable to communicate with the 6 GHz AP based on an indication in the probe requests. A threshold estimated number of probe requests transmitted by the client station is ignored to bandsteeer the client station to connect to the 6 GHz AP based on the determination where the threshold is based on a number of probe requests transmitted by the client station in a scan cycle. A probe response is then transmitted after the threshold estimated number of the probe requests are transmitted by the client station, wherein the client station is allowed to connect to the non-6 GHz AP.

A memory includes a data array divided into a plurality of input/output (IO) groups and a redundant IO group, each group including a set of columns. A column decoder selects one column from each IO group to provide selected data lines, and one column from the redundant group to provide a redundant data line. Repair circuitry, during normal operation, performs column repair using the selected one column from the redundant group to repair a defective column within one of the plurality of IO groups. Read/write circuitry, in response to a read access during a test mode, outputs read data sensed from the redundant data line in parallel with read data sensed from all the selected data lines. Control circuitry, in response to the read access during the test mode, provides the output read data sensed from the redundant data line external to the memory via a memory output pin.

A time to digital converter including multiple programmable buffers coupled in series for receiving a pulse signal, latches configured to provide binary values indicative of the state of the buffers at the end of a timing pulse asserted on the pulse signal, and a phase converter configured to convert the binary values into a digital output value indicative of a measured delay of the timing pulse. Each of the buffers is configured with an adjustable delay based on a delay select input. The adjustable delay is used to select from among multiple different transition delays of each buffer. The buffers may be configured to be compatible with a standard cell layout. The buffers may be configured as standard cell logic gate with modified connections. The buffers may be calibrated by selecting a fastest delay value that does not cause overflow in response to a calibration pulse.

A radio frequency amplifier device includes four power amplifiers. The first power amplifier output is coupled through a first inductive element to a first signal output terminal and through a second inductive element to a first shunt circuit access terminal. The second power amplifier output is coupled through a third inductive element to the first shunt circuit access terminal. The third power amplifier output is coupled through a fourth inductive element to a second signal output terminal and through a fifth inductive element to a second shunt circuit access terminal. The fourth power amplifier output is coupled through a sixth inductive element to the second shunt circuit access terminal. A first output combiner circuit includes the second and third inductive elements, and a second output combiner circuit includes the fifth and sixth inductive elements. External shunt capacitors are coupled to the first and second shunt circuit access terminals.

A temperature correction circuit for a voltage reference circuit includes two amplifiers, each having an output that controls a respective transistor that produces correction current for adjusting the reference voltage. Both amplifiers include one input coupled in a path to a reference voltage source and another input coupled in a path to a temperature sensing diode circuit. One amplifier's output controls the conductivity of its respective transistor to adjust the reference voltage when the temperature exceeds a high temperature set point. The other amplifier's output controls the conductivity of its respective transistor to adjust the reference voltage when the temperature falls below a low temperature set point.

Aspects of this disclosure are directed to systems and methods, for controlling access to a vehicle. The system comprises: a transceiver device, configured to transmit signals to, and receive signals from, an access device of a user, thereby to provide an indication that the user is within a first range of the system; a sensing system, comprising a video camera, and configured to, in response to the indication, record movements of the user; and a processor, coupled to the sensing system, and configured to: analyse the movements, determine, from the movements, whether the user is one of a group of known users, and in response to determining that the user is a one of the group of known users, authenticate the user.

There is provided a substrate package and method of manufacturing thereof. The substrate package comprises a carrier; a substrate having a first major surface and a second major surface, wherein the second major surface faces the carrier; a non-conductive first barrier wall extending from the second major surface towards the carrier, the first barrier wall defining first and second regions of the substrate package; and a ball grid array comprising a plurality of solder balls located between the substrate and the carrier, wherein a first subset of the solder balls is located within the first region and a second subset of the solder balls is located within the second region.

Improved half-duplex communication systems and methods are disclosed herein. In an example embodiment, an improved half-duplex communication system includes a first communication portion configured to operate at a first time as a first transmitter portion, and to receive a plurality of first data stream signals provided by a plurality of first ports, and also a second communication portion configured to operate at the first time as a first receiver portion, and configured to send a plurality of second data stream signals to be received by a plurality of second ports. The first communication portion includes each of a first data aggregation block, a first framing block, and a first modem device, and the second communications portion includes each of a first data deaggregation block, a first deframing block, and a second modem device.

A method of producing a circuit die where the method includes applying a pre-patterned backing tape to a first surface of a semiconductor substrate that includes the first surface and a second surface, the second surface including one or more circuits; coating the second surface with an encapsulant; removing a patterned portion of the pre-patterned backing tape to expose one or more contact pads on the first surface; applying one of an electrically conductive adhesive (ECA) or solder to the one or more contact pads on the first surface; and coupling an electrical component to the contact pads using the ECA or solder.

A power device system (100) comprising: a power device (101) and a controller (102), the power device (101) comprising: a power switch (103); and a control terminal driver (104), and wherein the power device (101) is configured to operate in both a ramp-up and ramp-down diagnostic mode in which the control terminal driver (104) is respectively configured to: apply a test current at the first node of the conduction channel (105) of the power switch (103); apply a first driver voltage that is less than or greater than the threshold voltage at control terminal (106) of the power switch (103); increase or decrease, respectively, the first driver voltage until a voltage drop or voltage increase, respectively is detected; and measure the first driver voltage at which the voltage drop is detected as a ramp-up threshold voltage or ramp-down threshold voltage, respectively, wherein the controller (102) is configured to determine a state of health of the power switch (101) based on the ramp-up threshold voltage and the ramp-down threshold voltage.

Techniques for processing a wafer involve patterning the wafer to define via locations within dies of the wafer and simultaneously define saw street indentation locations within saw street regions of the wafer. The saw street regions are disposed between the dies of the wafer. Such techniques further involve creating a set of indentations within the wafer. The set of indentations includes via indentations at the via locations within the dies configured to support electrically conductive interconnects and saw street indentations at the saw street indentation locations within the saw street regions configured to facilitate dicing.

A multi-level interconnect structure is formed on a semiconductor wafer to include conductive power-distribution rail bonding structures which are positioned for mounting on a package substate by forming a patterned insulator layer on the multi-level interconnect structure which includes a defined array of patterned openings, and then forming an array of conductive power-distribution rail bonding structures in the defined array of patterned openings to extend substantially over the top surface of the interconnect structure, where the array of conductive power-distribution rail bonding structures includes a plurality of parallel conductive rails which are aligned in parallel and distributed uniformly to directly electrically connect power over the plurality of conductive interconnect structures to the IC device.

A voltage gate driver (400) comprising:an OpAmp (401);a current source (402);a pull switch (403) configured to switchably operate in one of: a disconnected mode; and a pull mode,wherein one or both of:a) the operational amplifier (401) is configured to switchably operate in one of:a regulation mode;a pull mode, wherein the operational amplifier operates in the pull mode when the pull switch operates in the pull mode; anda disconnected mode in which the output node is disconnected from the operational amplifier and the reference voltage node; andb) the current source (402) is configured to switchably operate in one of:a controlled shutdown mode;a pull mode, wherein the current source operates in the pull mode when the pull switch operates in the pull mode; anda disconnected mode in which the output node is disconnected from the current source and the reference voltage node.

The disclosure relates to a power amplifier apparatus. A power amplifier apparatus (300) comprises: a power amplifier circuit (310) configured to receive an RF input signal at an RF input (RF_in) and to generate an RF output signal at an RF output (RF_out); an adaptive bias circuit (320) comprising a biasing transistor (M3), the biasing transistor (M3) having a common terminal coupled to the RF input (RF_in) and to a tail current source (I_bias), and the biasing transistor (M3) further having an input terminal coupled to a DC bias voltage source (dc_bias); and a rectification booster (330) comprising a current mirror device, wherein a first side of the current mirror device is coupled to an output terminal of the biasing transistor (M3) and wherein a second side of the current mirror device is coupled to the RF input (RF_in).

The disclosure relates to methods and systems for gauging a state of charge of a battery (200) in a chargeable device. An example method of gauging a state of charge of a battery (200) in a chargeable device comprises: measuring a current (I_DSG, I_CHG, I_SPM) at a charge control transistor (102); measuring a voltage (V_{bat_sense}) of a battery (200); providing the measured current (I_DSG, I_CHG, I_SPM) at the charge control transistor (102) and the voltage (V_{bat_sense}) of the battery (200) to a processor (300); determining, using the processor (300), the state of charge of the battery (200).

Methods and apparatus for generating a codebook for a reconfigurable intelligent surface (RIS) having a plurality of reflective elements (RIS elements). In an example, a method includes determining relative location information regarding a transmitter and the RIS and a receiver and the RIS. Based on the relative location information, angle of arrival information is calculated for signals from the transmitter to the RIS elements, and angle of departure information is calculated for signals from the RIS elements to the receiver. Phase shift information for the RIS elements is calculated based on the angle of arrival and angle of departure information, and is used to select reflection coefficients for the RIS elements such that a transmitted signal is reflected from the RIS to the receiver as a coherent reflected beam. The reflection coefficients are stored as a codeword in a RIS codebook used to configure the RIS elements.

A time to digital converter including multiple delay lines and an output adder. Each delay line includes multiple series-coupled buffers receiving a start signal, multiple latches each having an input coupled to an output of a buffer and an output providing one of multiple binary values in response to a stop signal, and an adder. Each adder adds the binary values from corresponding latches in response to the stop signal and provides a corresponding one of multiple digital output values. The output adder adds the digital output values from the delay lines and provides a digital output value indicative of a measured delay. The start and stop signals may be buffered to provide multiple start and stop signals each provided one of the delay lines. Each start signal may be delayed by one of multiple different delays. Select logic may combine multiple delay lines into a longer delay line group.

Methods and systems are described for monitoring and diagnosing the health of a processing unit within an embedded system using a power management integrated circuit (PMIC). The PMIC measures the current power consumption and temperature of the processing unit and compares these measurements against expected ranges derived from mission profiles, operational modes, and/or historical data. An alert is generated to prompt corrective action if the measurements are determined to be outside an expected range.

A fully differential CMOS demodulator includes a CMOS bias control circuit, a CMOS squarer rectifier, a CMOS summing circuit, at least one CMOS gain stage, and a CMOS mismatch control circuit. CMOS bias control circuit produces a bias signal that biases the other components. The CMOS squarer rectifier receives the reference voltage, a first modulated analog information signal, and a second modulated analog information signal and demodulates the first and second modulated analog information signals to produce differential demodulated information signals and average voltage levels of the differential demodulated information signals. The CMOS summing circuit sums the differential demodulated information signals and average voltage levels of the differential demodulated information signals to produce a differential demodulated information signal pair. The at least one CMOS gain stage amplifies the differential demodulated information signal pair, and the CMOS mismatch control circuit alters the differential demodulated information signal pair for offset compensation.

To help reduce the amount of time before a safety power management integrated circuit (PMIC) releases a processing system from a safety state, the safety PMIC includes a first digital circuitry that first configures a voltage threshold comparator and then enables a voltage regulator to provide power to the rest of the PMIC. Additionally, concurrently with the rest of the PMIC powering on, the safety PMIC includes a second digital circuitry that is distinct from the first digital circuitry and that performs a logic built-in self-test (LBIST) for a safety logic circuitry configured to monitor the voltage threshold comparator.

A method for Channel Sounding (CS) localization with multiple vehicle anchors includes performing a CS procedure to generate a first remote data at a digital key and a first local data at a first one of a plurality of anchors. A first distance between the digital key and the first anchor is determined from the first remote data received from the digital key and the first local data. A connection handover from the first anchor to a second one of a plurality of anchors is performed. The CS procedure is performed to generate a second remote data at the digital key and a second local data at the second anchor. A second distance between the digital key and the second anchor is determined from the second remote data received from the digital key and the second local data. A location of the digital key is trilaterated using at least the first distance and the second distance.

One example discloses a module, including: a set of e-switches configured to be coupled to a power supply line and a set of loads; a communications circuit coupled to the e-switches and configured to be coupled to a communications bus; a controller coupled to the e-switches and the communications circuit; wherein the communications circuit and the controller are powered by the e-switches; wherein the communications circuit and the controller are configured to be in a low-power state until receiving a wake-up signal from the e-switches; and wherein the e-switches are configured to receive the wake-up signal over the power supply line.

The regulation and clamping functions are separated at a controller integrated circuit (IC) for a DC-DC converter. The controller IC includes a clamp circuit configured to clamp the voltage at a pin of the controller IC that is connected to external compensation circuitry. The controller IC further includes a different regulation circuit configured to regulate a clamp loop of the controller IC.

A power amplifier device (130, 230, 330, 430, 430', 530, 530') includes a power transistor die (154, 174, 454, 474), an input side signal lead (140, 141, 240, 241, 440, 441) electrically coupled to an input terminal of the power transistor die and extending beyond an input side (131, 231, 331, 431, 1031) of the device, an output side signal lead (144, 145, 244, 245, 444, 445) electrically coupled to an output terminal of the power transistor die and extending beyond an output side (132, 232, 332, 432, 1032) of the device, and an input-to-output bias-conducting structure (133, 135, 433, 435, 533, 535, 1000, 1100, 1200, 1300) that is not physically directly connected to the input side signal lead or to the output side signal lead. The input-to-output bias-conducting structure includes an input side bias lead (142, 143, 242, 243, 342, 343, 442, 443, 542, 543, 1042, 1242, 1342) coupled to an input portion of the device, an output side bias lead (146, 147, 246, 247, 346, 247, 446, 447, 546, 547, 1046, 1246, 1346) coupled to an output portion of the device, and an interior conductive structure (134, 136, 434, 436, 1034, 1134, 1234, 1334) with a first end connected to the input side bias lead, and a second end connected to the output side bias lead.

A device includes a radiofrequency integrated circuit (RFIC) having a radiofrequency (RF) input terminal and an RF output terminal and also includes a field plate electrode having a first end that is electrically-coupled to the RF output terminal and a second end that is suspended above the RFIC. The second end of the field plate electrode is configured to float at an electric potential that is determined by an electric potential of the RF output terminal.

Built-in self-test circuitry is configured to calculate a sensed temperature using an MRAM and a stored set of margin read reference and temperature correlations for a target bit error rate. A current margin read reference is selected, and a sweep through a sequence of addresses of the MRAM is performed using the current margin read reference. At each address of the sequence, a normal read is performed to obtain normal read data and a margin read is performed to obtain margin read data. A bit error count is obtained for the sweep based on comparisons between the normal and margin read data obtained at each address, and the current margin read reference is selectively modified based on whether or not the bit error count achieves the target bit error rate. The selectively modified current margin read reference and the stored set of correlations are used to calculate the sensed temperature.

A pipelined SAR ADC that is connected to receive an analog input voltage includes a first ADC stage, a residue amplifier, a second ADC stage, and calibration circuitry coupled and configured to add first and second ADC conversion results to form an uncalibrated digital value, and to apply calibration values to the uncalibrated digital value to obtain a calibrated digital value corresponding to a calibrated digital representation of the analog input voltage, where the calibration values include a first ADC stage DAC element mismatch calibration value corresponding to the first ADC conversion result, an offset calibration value, and a gain adjustment factor.

A processing system including processing cores, a shared memory, a shift table that stores a maximum number of reservations to locations in the memory, and an exclusive monitor that uses the shift table and an eviction policy to enforce core synchronization. The eviction policy is based on priority, age of valid reservations, shift table fullness state, and reservation memory conflict. The shift table may include a memory address and a size value indicative of a flexible amount of reserved memory at the memory address. The exclusive monitor evicts an oldest reservation in the shift table having a same or lower priority level as the new reservation. The exclusive monitor rejects the new reservation when the shift table is full of higher priority reservations. Reservations are shifted to maintain age status. Stale reservations may be invalidated or have their priority lowered. Conflicting reservations may be made with the same priority level.

A method, system, apparatus, and architecture are provided for reacting to resource faults by deploying safety management unit (SMU) instances at a plurality of functional components, where each SMU instance is program code configured to monitor a first set of one or more resources assigned to run a first application; detect a fault at the first set of one or more resources; identify a second set of one or more resources for reallocation to the first application using a ranked listing of candidate resource sets, where each candidate resource set is capable of running the first application; and assign the second set of one or more resources to run the first application, where the ranked listing of candidate resource sets is dynamically updated based on runtime performance and health measures of resources in the candidate resource set.

A system and method include receiving, by a security controller of a system-on-chip and from a controller of the system-on-chip, an indication that a debugger computing device is connected to a debug port of the system-on-chip. A user debug authorization key and a user debug profile are received and verified by the security controller. The user debug profile identifies a set of requested resources. A configuration of the system-on-chip is modified to allow the debugger computing device to access resources of the set of requested resources.

A Doherty power amplifier includes a combining node that combines amplified output signals from first and second amplifiers. A reconfigurable impedance inverter circuit is coupled between the first amplifier and the combining node. The impedance inverter circuit includes an inductive element coupled between a first node and a second node, and a switching circuit coupled between the first node and the second node. A fundamental frequency tuning circuit and a harmonic frequency resonance circuit are coupled between the switching circuit and a ground reference node. When the switching circuit is configured in a first state, the fundamental frequency tuning circuit and the harmonic frequency resonance circuit are electrically coupled through the switching circuit to the first and second nodes. When the switching circuit is configured in a second state, the fundamental frequency tuning circuit and the harmonic frequency resonance circuit are electrically disconnected from the first and second nodes.

A circuit arrangement comprises an output combiner circuit including a first output network having a first amplifier output node for connection to a first output of the main amplifier, a second output network having a second amplifier output node for connection to a second output of the peaking amplifier, and a final summing node. The first output network comprises a first inductive element connected between the first amplifier output node and a first intermediate node, a second inductive element connected between the first intermediate node and the final summing node, and a third inductive element connected between the first intermediate node and ground. The second output network comprises a fourth inductive element connected between the second amplifier output node and a second intermediate node, a fifth inductive element connected between the second intermediate node and ground, and a capacitive element connected between the second intermediate node and the final summing node.

A non-volatile memory (NVM) controller is configured to control reads from and writes to an NVM array, and includes a write buffer and a buffer control circuit. The write buffer includes a plurality of entries, each configured to store a write access having a corresponding page address of the NVM array and corresponding write data. The buffer control circuit is configured to store a write access having a corresponding page address of the NVM array and corresponding write data, and generate burst writes from the write buffer to the NVM array. The buffer control circuit generates a burst write by sequentially selecting write accesses from the write buffer which have consecutive page addresses, in which the length of the burst write is undefined when the burst write to the NVM array is initiated.

A method of manufacturing a semiconductor device interconnect structure is provided. The method includes forming a copper pillar on a semiconductor die by way of a plating process. A proximal portion of the copper pillar has a first width dimension, and a distal portion of the copper pillar has a second width dimension. The second width dimension of the distal portion of the copper pillar is configured to be smaller than the first width dimension of the proximal portion of the copper pillar. Sidewalls of the distal portion of the copper pillar are selectively roughened. The roughened sidewalls of the distal portion of the copper pillar are configured to promote solder wetting.

A method for delivering data frames from a source device (702) to a Zigbee end device, ZED, (550) via a Zigbee router, ZR, (510), comprises, at the ZR, receiving individual data blocks with a fragmentation window of '1' data block between the ZR and the source, individually transmitting an APS acknowledgement for received data blocks identified by APS transmission parameters. Data blocks are re-transmitted until an acknowledgement of a successful receipt is transmitted to the source. The data block is transmitted to the ZED until an acknowledgement is received. Following a penultimate data block (720) having been transmitted from the ZR and acknowledged by the ZED, the method further comprises at the ZED: transmitting a second data request (762, 772) to the ZR for a final data block; and transmitting an APS acknowledgement of successfully receiving the final data block to the ZR; and to the source.

An electronic device has a molded package (e.g., a quad flat no leads package) with attached connectors. The molded package includes one or more semiconductor dies and is pretested prior to attachment of the connectors. Along these lines, such molded packages may be pretested in parallel at high volume due to their relatively small form factor (e.g., at numbers several times greater than those for testing leaded socket assemblies). Following such pretesting, the connectors are attached to the pretested molded package (e.g., by directly fusing the connectors to metallic pads on surfaces of the packaged integrated circuit via laser welding or soldering). Such electronic devices may be further tested if desired (e.g., opens/shorts tested) and encased within housings to form larger modules (e.g., accelerometers, pressure sensors, etc.).