NXP USA Patente

A unity gain buffer including a differential amplifier, detector and feedback circuitry, and an output stage. The differential amplifier receives a difference voltage between a buffer input and output, is coupled to a control node for modulating a current of the differential amplifier, and drives an output node. The detector and feedback circuitry has an input coupled to the buffer input and output and has an output coupled to the control node. The output stage has an input coupled to the output drive node and has an output coupled to the buffer output node. The differential amplifier draws minimal current when the difference voltage is substantially zero and increases current when the difference voltage increases causing the output stage to drive a voltage of the buffer output node back to a voltage of the buffer input node. At least one current booster or a preset load may be added.

An integrated circuit is provided with a signal node/IO pad in an output buffer that is protected by a current injection protection circuit which includes first and second comparators connected between a first voltage supply and a second voltage supply to generate first and second control signals in response to, respectively, a positive or negative injected current at the signal node, and which also includes a pre-driver stack of transistors which generate, respectively, a positive gate control signal and negative gate control signal, and which also includes a multiplex selection circuit connected to output the positive gate control signal and negative gate control signal to the output buffer to clamp signal node to a first clamped voltage if a voltage on the signal node exceeds the first supply voltage or to a second clamped voltage if a voltage on the signal node falls below the second supply voltage.

A radio frequency (RF) power amplifier (100, 200) and a packaged power amplifier device include a transistor (130, 230, 530) and an input impedance matching circuit (110, 210, 310) coupled between an amplifier input and an input terminal of the transistor. The input impedance matching circuit includes first, second, third, and fourth inductive elements (111, 112, 113, 114, 211, 212, 213, 214, 411, 412, 413, 414) coupled in series, with first, second, third intermediate nodes (118, 119, 120, 218, 219, 220, 418, 419, 420) between adjacent inductive elements. First, second, and third capacitors (115, 116, 117, 215, 216, 217, 415, 416, 417) are coupled between the first, second, and third intermediate nodes, respectively, and a ground reference node.

A power factor correction (PFC) circuit is described which includes an inductor configured to generate an output voltage to an output load, an output voltage sensor, an output current measurement circuit, a first filter capacitor coupled between the output voltage and a first input node, a second filter capacitor between the first input node and a low voltage, and a first input node voltage sensor. Capacitor compensation logic is configured to receive the output current and the first input node voltage, to compensate the output current for the first filter capacitor and the second filter capacitor using the first input node voltage, and to generate a corrected output current. A control system is coupled to receive the output voltage and the corrected output current and configured to generate control signals to control the output voltage.

Radiofrequency systems for use in advanced driver assistance systems (ADAS) can include a mixture of high frequency (e.g., above 1 GHz) analog and components and lower-frequency digital devices mounted on one main circuit board. Cost savings can be achieved by providing high-frequency signal paths on an interposer circuit board that is mounted to the main circuit board and couples devices requiring high-frequency signalling (e.g., distributing a local oscillator signal to several devices forming part of a cascaded radar system). The interposer is fabricated from special purpose materials suitable for routing high frequency signals with low loss, while the main circuit board can be fabricated from commodity materials suitable for lower frequency applications.

An apparatus, such as a subsampling phase locked loop (PLL), includes a digitally controlled oscillator (DCO), a digital phase detector, and a digital filter. The DCO generates a first signal having a phase based on a second signal provided to the DCO. The digital phase detector generates a third signal that represents a phase offset between a reference clock signal and the first signal. The digital filter generates the second signal by filtering out high-frequency fluctuations in the third signal.

An integrated circuit is disclosed which includes a stacked P+ substrate, n-type epitaxial layer, and one or more p-type epitaxial layers, with a buried layer located in the one or more p-type epitaxial layers to be adjacent to the n-type epitaxial layer, a central isolated region located in the one or more p-type epitaxial layers to be positioned over the buried layer, one or more concentric shallow isolation ring structures positioned to surround the central isolated region and to extend down through the buried layer and into the n-type epitaxial layer, and a concentric deep poly isolation structure positioned to surround the central isolated region and the one or more concentric shallow isolation ring structures and to extend down through the n-type epitaxial layer and into the P+ substrate, wherein the concentric deep poly isolation structure include one or more polysilicon layers that are shorted to the P+ substrate.

A packaged device includes molding compound, a first semiconductor die disposed within the molding compound and a second semiconductor die disposed within the molding compound. The molding compound galvanically isolates the first and second semiconductor dies. The packaged device further includes communication coils constructed and arranged to provide communication between the first and second semiconductor dies through inductive coupling, at least one of the communication coils being fabricated within the molding compound.

The present disclosure relates to a communication module comprising: a first communication interface, a second communication interface, and a processing unit, wherein the first communication interface is configured to receive an instruction message according to a first communication protocol, wherein the instruction message represents a predefined reference instruction, wherein the communication module is configured to detect an uninterrupted idle time during which the communication module does not receive a message via the first communication interface, and wherein the processing unit is configured, in response to the idle time exceeding a predefined dead time, to control the second communication interface such that the second communication interface transmits a command message according to a second communication protocol, wherein the command message represents the reference instruction. The present disclosure also relates to a communication system, which includes the communication module, and a method for the communication module.

Aspects of the subject disclosure may include, for example, a packaged integrated circuit device that includes two galvanically isolated integrated circuit die. The integrated circuit die include conductive coils that can be inductively coupled for wireless communications between the two galvanically isolated integrated circuit die. A first integrated circuit die is mounted to a lead frame and a second integrated circuit die is surrounded by a molding compound structure and an insulating layer. The second integrated circuit is adhered to the first integrated circuit in a manner that aligns the conductive coils and provides galvanic isolation between the two integrated circuit die. Other embodiments are disclosed.

This disclosure relates to a power module, a power converter, a method, and a computer program for supplying a target amount of power across different power ranges using a hybrid circuit architecture.

Aspects of the subject disclosure may include, for example, a packaged integrated circuit device that includes two galvanically isolated integrated circuit die. The integrated circuit die include conductive coils that can be inductively coupled for wireless communications between the two galvanically isolated integrated circuit die. One of the integrated circuit die is flip chip mounted to the other integrated circuit die with the coils facing each other across an insulating layer that includes routing to provide power to the flip chip mounted integrated circuit die. Other embodiments are disclosed.

A current mirror circuit (200) comprises: a first current source (206) for providing a first reference current (IB1); a first transistor (M1, 222) having a control terminal (226), a first current terminal (228) coupled to receive the first reference current (IB1), and a second current terminal (230) coupled to a reference potential (VEE); a second transistor (M2, 224) having a control terminal (232) coupled to the control terminal (226) of the first transistor (M1, 222), a first current terminal (234) coupled to an output node (GL, 208) of the current mirror circuit (200), and a second current terminal (236) coupled to the reference potential (VEE); and matching circuitry (300) having an input (302) coupled to the output node (GL, 208) of the current mirror circuit (200), and an output (304) coupled to the first current terminal (228) of the first transistor (M1, 222), the matching circuitry (300) being configured to provide, at the first current terminal (228) of the first transistor (M1, 222), a replica voltage corresponding to a voltage at the output node (GL, 208) of the current mirror circuit (200).

A dual-path phase-locked loop (PLL) is disclosed. The dual-path PLL converts, based on a masking value, a pulse signal to a masked pulse signal such that the masked pulse signal comprises one or more unmasked pulses and one or more masked pulses of the pulse signal. An integral current is generated, based on the masked pulse signal in a manner such that that an average current value of the integral current reaches a desired value over a predefined number of cycles of the pulse signal and an optimal peaking in the dual-path PLL is achieved.

An apparatus and method for synchronizing a reference oscillator. A frequency of an adjustable frequency reference oscillator is adjusted based on an indication that radio signal processing is inactive and based on a phase error between a synchronized frequency reference signal and a frequency based on a synchronization reference signal. The adjustable frequency reference oscillator provides the synchronized frequency reference signal for a radio frequency circuit and a timing signal indicates whether radio signal processing by a radio frequency circuit is active or inactive. Adjustment of the frequency of the adjustable frequency reference oscillator is inhibited based on the timing signal indicating that radio signal processing is active.

The present disclosure relates to a driver system, the driver system comprising: a driver circuit, a compensation circuit, a first driver terminal, a second driver terminal, and a third driver terminal, wherein the driver circuit comprises a first switching transistor and a first current mirror, wherein the first current mirror comprises a first reference transistor and a first mirror transistor, wherein the first reference transistor is integrated into a first circuit branch of the driver circuit, wherein the first switching transistor and the first mirror transistor are integrated into a second circuit branch of the driver circuit, such that the first switching transistor and the first mirror transistor are connected in series, wherein the compensation circuit is coupled to the gate terminal of the first mirror transistor, and wherein a second switching transistor and a compensation capacitor are integrated in the compensation branch.

Systems and methods for pin lift detection compensation in Low Dropout (LDO) regulators. In an illustrative, non-limiting embodiment, a System-On-Chip (SoC) may include: a circuit; and an LDO regulator coupled to the circuit, where the LDO includes a transistor having a first terminal coupled to a first voltage rail and a second terminal coupled to the circuit, where the second terminal is configured to receive a probe current produced from a second voltage rail, and where the first voltage rail is coupled to a compensating current source configured to draw a compensating charge equal to or greater than a charge imparted upon the second terminal by the probe current.

A memory includes a data array divided into a plurality of input/output (IO) groups and a redundant IO group, each group including a set of columns. A column decoder selects one column from each IO group to provide selected data lines, and one column from the redundant group to provide a redundant data line. Repair circuitry, during normal operation, performs column repair using the selected one column from the redundant group to repair a defective column within one of the plurality of IO groups. Read/write circuitry, in response to a read access during a test mode, outputs read data sensed from the redundant data line in parallel with read data sensed from all the selected data lines. Control circuitry, in response to the read access during the test mode, provides the output read data sensed from the redundant data line external to the memory via a memory output pin.

A method, system, and apparatus for bandsteering a client station to an access point. A non-6 GHz AP receives a plurality of probe requests from the client station and determines that the client station is operable to communicate with the 6 GHz AP based on an indication in the probe requests. A threshold estimated number of probe requests transmitted by the client station is ignored to bandsteeer the client station to connect to the 6 GHz AP based on the determination where the threshold is based on a number of probe requests transmitted by the client station in a scan cycle. A probe response is then transmitted after the threshold estimated number of the probe requests are transmitted by the client station, wherein the client station is allowed to connect to the non-6 GHz AP.

An apparatus and method for aggregating multiple data streams over a single aggregate link. Two or more serial communication signals are received. A minimum effective transfer rate (M) for a single aggregate link for a given frame structure is determined. A minimum frame length (FLEN) based on a combination of sync bits (S), propagation delay (PD), turnaround (TA), and payload (P) is set. A transfer rate per bit (R) based on the payload (P) and minimum frame length (FLEN) is evaluated. In response to the transfer rate per bit (R) being less than or equal to the minimum effective transfer rate (M), increment the payload (P) of the given frame structure and repeat the steps above. Otherwise, the serial communication signals are encoded to generate an encoded serial communication signal, wherein the encoded serial communication signal enables the reconstruction of the serial communication signals independent of a clock signal.

A radio frequency amplifier device includes four power amplifiers. The first power amplifier output is coupled through a first inductive element to a first signal output terminal and through a second inductive element to a first shunt circuit access terminal. The second power amplifier output is coupled through a third inductive element to the first shunt circuit access terminal. The third power amplifier output is coupled through a fourth inductive element to a second signal output terminal and through a fifth inductive element to a second shunt circuit access terminal. The fourth power amplifier output is coupled through a sixth inductive element to the second shunt circuit access terminal. A first output combiner circuit includes the second and third inductive elements, and a second output combiner circuit includes the fifth and sixth inductive elements. External shunt capacitors are coupled to the first and second shunt circuit access terminals.

A time to digital converter including multiple programmable buffers coupled in series for receiving a pulse signal, latches configured to provide binary values indicative of the state of the buffers at the end of a timing pulse asserted on the pulse signal, and a phase converter configured to convert the binary values into a digital output value indicative of a measured delay of the timing pulse. Each of the buffers is configured with an adjustable delay based on a delay select input. The adjustable delay is used to select from among multiple different transition delays of each buffer. The buffers may be configured to be compatible with a standard cell layout. The buffers may be configured as standard cell logic gate with modified connections. The buffers may be calibrated by selecting a fastest delay value that does not cause overflow in response to a calibration pulse.

A temperature correction circuit for a voltage reference circuit includes two amplifiers, each having an output that controls a respective transistor that produces correction current for adjusting the reference voltage. Both amplifiers include one input coupled in a path to a reference voltage source and another input coupled in a path to a temperature sensing diode circuit. One amplifier's output controls the conductivity of its respective transistor to adjust the reference voltage when the temperature exceeds a high temperature set point. The other amplifier's output controls the conductivity of its respective transistor to adjust the reference voltage when the temperature falls below a low temperature set point.

Aspects of this disclosure are directed to systems and methods, for controlling access to a vehicle. The system comprises: a transceiver device, configured to transmit signals to, and receive signals from, an access device of a user, thereby to provide an indication that the user is within a first range of the system; a sensing system, comprising a video camera, and configured to, in response to the indication, record movements of the user; and a processor, coupled to the sensing system, and configured to: analyse the movements, determine, from the movements, whether the user is one of a group of known users, and in response to determining that the user is a one of the group of known users, authenticate the user.

There is provided a substrate package and method of manufacturing thereof. The substrate package comprises a carrier; a substrate having a first major surface and a second major surface, wherein the second major surface faces the carrier; a non-conductive first barrier wall extending from the second major surface towards the carrier, the first barrier wall defining first and second regions of the substrate package; and a ball grid array comprising a plurality of solder balls located between the substrate and the carrier, wherein a first subset of the solder balls is located within the first region and a second subset of the solder balls is located within the second region.

A power device system (100) comprising: a power device (101) and a controller (102), the power device (101) comprising: a power switch (103); and a control terminal driver (104), and wherein the power device (101) is configured to operate in both a ramp-up and ramp-down diagnostic mode in which the control terminal driver (104) is respectively configured to: apply a test current at the first node of the conduction channel (105) of the power switch (103); apply a first driver voltage that is less than or greater than the threshold voltage at control terminal (106) of the power switch (103); increase or decrease, respectively, the first driver voltage until a voltage drop or voltage increase, respectively is detected; and measure the first driver voltage at which the voltage drop is detected as a ramp-up threshold voltage or ramp-down threshold voltage, respectively, wherein the controller (102) is configured to determine a state of health of the power switch (101) based on the ramp-up threshold voltage and the ramp-down threshold voltage.

A method of producing a circuit die where the method includes applying a pre-patterned backing tape to a first surface of a semiconductor substrate that includes the first surface and a second surface, the second surface including one or more circuits; coating the second surface with an encapsulant; removing a patterned portion of the pre-patterned backing tape to expose one or more contact pads on the first surface; applying one of an electrically conductive adhesive (ECA) or solder to the one or more contact pads on the first surface; and coupling an electrical component to the contact pads using the ECA or solder.

Improved half-duplex communication systems and methods are disclosed herein. In an example embodiment, an improved half-duplex communication system includes a first communication portion configured to operate at a first time as a first transmitter portion, and to receive a plurality of first data stream signals provided by a plurality of first ports, and also a second communication portion configured to operate at the first time as a first receiver portion, and configured to send a plurality of second data stream signals to be received by a plurality of second ports. The first communication portion includes each of a first data aggregation block, a first framing block, and a first modem device, and the second communications portion includes each of a first data deaggregation block, a first deframing block, and a second modem device.

Methods and apparatus for generating a codebook for a reconfigurable intelligent surface (RIS) having a plurality of reflective elements (RIS elements). In an example, a method includes determining relative location information regarding a transmitter and the RIS and a receiver and the RIS. Based on the relative location information, angle of arrival information is calculated for signals from the transmitter to the RIS elements, and angle of departure information is calculated for signals from the RIS elements to the receiver. Phase shift information for the RIS elements is calculated based on the angle of arrival and angle of departure information, and is used to select reflection coefficients for the RIS elements such that a transmitted signal is reflected from the RIS to the receiver as a coherent reflected beam. The reflection coefficients are stored as a codeword in a RIS codebook used to configure the RIS elements.

A time to digital converter including multiple delay lines and an output adder. Each delay line includes multiple series-coupled buffers receiving a start signal, multiple latches each having an input coupled to an output of a buffer and an output providing one of multiple binary values in response to a stop signal, and an adder. Each adder adds the binary values from corresponding latches in response to the stop signal and provides a corresponding one of multiple digital output values. The output adder adds the digital output values from the delay lines and provides a digital output value indicative of a measured delay. The start and stop signals may be buffered to provide multiple start and stop signals each provided one of the delay lines. Each start signal may be delayed by one of multiple different delays. Select logic may combine multiple delay lines into a longer delay line group.

The disclosure relates to methods and systems for gauging a state of charge of a battery (200) in a chargeable device. An example method of gauging a state of charge of a battery (200) in a chargeable device comprises: measuring a current (I_DSG, I_CHG, I_SPM) at a charge control transistor (102); measuring a voltage (V_{bat_sense}) of a battery (200); providing the measured current (I_DSG, I_CHG, I_SPM) at the charge control transistor (102) and the voltage (V_{bat_sense}) of the battery (200) to a processor (300); determining, using the processor (300), the state of charge of the battery (200).

Techniques for processing a wafer involve patterning the wafer to define via locations within dies of the wafer and simultaneously define saw street indentation locations within saw street regions of the wafer. The saw street regions are disposed between the dies of the wafer. Such techniques further involve creating a set of indentations within the wafer. The set of indentations includes via indentations at the via locations within the dies configured to support electrically conductive interconnects and saw street indentations at the saw street indentation locations within the saw street regions configured to facilitate dicing.

The disclosure relates to a power amplifier apparatus. A power amplifier apparatus (300) comprises: a power amplifier circuit (310) configured to receive an RF input signal at an RF input (RF_in) and to generate an RF output signal at an RF output (RF_out); an adaptive bias circuit (320) comprising a biasing transistor (M3), the biasing transistor (M3) having a common terminal coupled to the RF input (RF_in) and to a tail current source (I_bias), and the biasing transistor (M3) further having an input terminal coupled to a DC bias voltage source (dc_bias); and a rectification booster (330) comprising a current mirror device, wherein a first side of the current mirror device is coupled to an output terminal of the biasing transistor (M3) and wherein a second side of the current mirror device is coupled to the RF input (RF_in).

A multi-level interconnect structure is formed on a semiconductor wafer to include conductive power-distribution rail bonding structures which are positioned for mounting on a package substate by forming a patterned insulator layer on the multi-level interconnect structure which includes a defined array of patterned openings, and then forming an array of conductive power-distribution rail bonding structures in the defined array of patterned openings to extend substantially over the top surface of the interconnect structure, where the array of conductive power-distribution rail bonding structures includes a plurality of parallel conductive rails which are aligned in parallel and distributed uniformly to directly electrically connect power over the plurality of conductive interconnect structures to the IC device.

A voltage gate driver (400) comprising:an OpAmp (401);a current source (402);a pull switch (403) configured to switchably operate in one of: a disconnected mode; and a pull mode,wherein one or both of:a) the operational amplifier (401) is configured to switchably operate in one of:a regulation mode;a pull mode, wherein the operational amplifier operates in the pull mode when the pull switch operates in the pull mode; anda disconnected mode in which the output node is disconnected from the operational amplifier and the reference voltage node; andb) the current source (402) is configured to switchably operate in one of:a controlled shutdown mode;a pull mode, wherein the current source operates in the pull mode when the pull switch operates in the pull mode; anda disconnected mode in which the output node is disconnected from the current source and the reference voltage node.

To help reduce the amount of time before a safety power management integrated circuit (PMIC) releases a processing system from a safety state, the safety PMIC includes a first digital circuitry that first configures a voltage threshold comparator and then enables a voltage regulator to provide power to the rest of the PMIC. Additionally, concurrently with the rest of the PMIC powering on, the safety PMIC includes a second digital circuitry that is distinct from the first digital circuitry and that performs a logic built-in self-test (LBIST) for a safety logic circuitry configured to monitor the voltage threshold comparator.

A method for Channel Sounding (CS) localization with multiple vehicle anchors includes performing a CS procedure to generate a first remote data at a digital key and a first local data at a first one of a plurality of anchors. A first distance between the digital key and the first anchor is determined from the first remote data received from the digital key and the first local data. A connection handover from the first anchor to a second one of a plurality of anchors is performed. The CS procedure is performed to generate a second remote data at the digital key and a second local data at the second anchor. A second distance between the digital key and the second anchor is determined from the second remote data received from the digital key and the second local data. A location of the digital key is trilaterated using at least the first distance and the second distance.

A fully differential CMOS demodulator includes a CMOS bias control circuit, a CMOS squarer rectifier, a CMOS summing circuit, at least one CMOS gain stage, and a CMOS mismatch control circuit. CMOS bias control circuit produces a bias signal that biases the other components. The CMOS squarer rectifier receives the reference voltage, a first modulated analog information signal, and a second modulated analog information signal and demodulates the first and second modulated analog information signals to produce differential demodulated information signals and average voltage levels of the differential demodulated information signals. The CMOS summing circuit sums the differential demodulated information signals and average voltage levels of the differential demodulated information signals to produce a differential demodulated information signal pair. The at least one CMOS gain stage amplifies the differential demodulated information signal pair, and the CMOS mismatch control circuit alters the differential demodulated information signal pair for offset compensation.

One example discloses a module, including: a set of e-switches configured to be coupled to a power supply line and a set of loads; a communications circuit coupled to the e-switches and configured to be coupled to a communications bus; a controller coupled to the e-switches and the communications circuit; wherein the communications circuit and the controller are powered by the e-switches; wherein the communications circuit and the controller are configured to be in a low-power state until receiving a wake-up signal from the e-switches; and wherein the e-switches are configured to receive the wake-up signal over the power supply line.

Methods and systems are described for monitoring and diagnosing the health of a processing unit within an embedded system using a power management integrated circuit (PMIC). The PMIC measures the current power consumption and temperature of the processing unit and compares these measurements against expected ranges derived from mission profiles, operational modes, and/or historical data. An alert is generated to prompt corrective action if the measurements are determined to be outside an expected range.