MediaTek Patente

A compute die (200) includes a high bandwidth memory, HBM, interface subsystem (204). The HMB interface subsystem (204) includes an HBM controller circuit (206) and an HBM physical layer, PHY, circuit (208). The HBM controller circuit (206) is configured to control access of at least one HBM. The HBM PHY circuit (208) is configured to communicate with the at least one HBM. The HBM interface subsystem (204) is configured to tolerate failure of at least one HBM channel through channel redundancy.

A memory device (100) includes a memory array (102) and a plurality of bitlines (BL_A, BL_B, BLB_A, BLB_B). The bitlines (BL_A, BL_B, BLB_A, BLB_B) include a first bitline (BL_A). The first bitline (BL₄) includes a first bitline segment (108_1) and a second bitline segment (108_2). The first bitline segment (108_1) is routed on a first metal layer but not a second metal layer, and coupled to a plurality of first memory cells in the memory array (102), wherein the second metal layer is different from the first metal layer. The second bitline segment (108_2) is routed on the second metal layer but not the first metal layer, and coupled to the first memory cells through the first bitline segment. At least a portion of the first bitline segment (108_1) and at least a portion of the second bitline segment (108_2) are connected in a shunt configuration.

Techniques pertaining to joint subframe and bit synchronization of data signals in satellite and mobile communications are described. An apparatus, e.g. a user equipment, receives a signal, e.g. a GNSS signal, (910) and detects the transmitted data symbols in the signal (920). The apparatus then computes a subframe hypothesis test correlation including the sync word correlation and the bit correlations (930). The apparatus also synchronizes the data subframe and bit timing (940).

An on-die power sensor (100) includes a digital current sensor (10), a digital voltage sensor (20) and a power calculator (40) for performing run-time power/voltage/current management. The digital current sensor (10) measures speed counts of two identical ring oscillators (ROSC1, ROSC2), acquire an overall delta speed count between the two ring oscillators (ROSC1, ROSC2), converts the overall delta speed count to a voltage drop based on a trimmed slope of a first lookup table, and convert the voltage drop to a run-time current based on a trimmed DCR of a second lookup table. The digital voltage sensor (20) records values of the speed counts measured by the digital current sensor (10) to quantify a run-time voltage based on a third lookup table. The power calculator (40) obtains a run-time power by multiplying the run-time current and the run-time voltage.

An image processing method (300) may include processing an original image (100) to generate a plurality of activated patches, performing a first scanning operation (S1) on the plurality of activated patches according to a first scanning pattern to collect first scan data (D1), performing a second scanning operation (S2) on the plurality of activated patches according to a second scanning pattern to collect second scan data (D2), and processing at least the first scan data (D1) and the second scan data (D2) to generate an improved image. The first scanning pattern is different from the second scanning pattern.

A system including multiple artificial intelligence, AI, agents generates test cases for a test target in multiple stages. A first AI agent uses a large multimodal model, LMM, to process a first prompt and specifications of the test target to generate respective identifiers of test plans (1110). A second AI agent uses the LMM to process a second prompt, the specifications of the test target, and an output of the first AI agent to generate an ordered list of test steps in each test plan (1120). A third AI agent uses the LMM to process a third prompt and an output of the second AI agent to expand the test plans into test cases (1130). The system verifies the output of each of the first AI agent, the second AI agent, and the third AI agent (1140), and generates a test case document according to the test cases (1150).

Techniques pertaining to coordinated multi-access point transmission in wireless communications are described. A first access point, AP, may perform a frame exchange applicable to a coordinated transmission with a second AP (1610). The coordinated transmission may include at least one of a coordinated beamforming, CoBF, and a coordinated spatial reuse, CoSR. The first AP may transmit a physical layer protocol data unit, PPDU, based on the frame exchange (1620). The frame exchange may include an invite frame transmitted by the first AP for inviting the second AP to participate in the coordinated transmission, a response frame received by the first AP from the second AP for indicating a participation in the coordinated transmission in response to the invite frame, and a trigger frame transmitted by the first AP to the second AP prior to a transmission of the PPDU. The trigger frame may include confirmed information for performing the coordinated transmission.

The present invention provides an ESD protection circuit including a BOX device and at least one ESD device. The BOX device includes a BOX layer placed between a substrate and an active silicon layer, and the BOX device and the ESD device are connected in cascode. The ESD protection circuit has a higher trigger voltage and will not be falsely triggered, and an active layer of the BOX device does not form any parasitic paths with the underlying layers.

A semiconductor device is provided. The semiconductor device includes a first circuit board, a first semiconductor chip assembly, a first cooling unit and a first supporting component. The first circuit board has a first surface. The first semiconductor chip assembly is disposed on the first surface of the first circuit board. The first supporting component connects the first cooling unit with the first circuit board in a thickness direction of the semiconductor device.

A spatial audio playback device, comprises: a transceiver unit, which communicates with the head-mounted device through wireless communication, is configured to receive information of a motion of the head-mounted device on a motion sensing signal and information or a transmission standard of the wireless communication from the head-mounted device; and a processing unit, which is coupled to the transceiver unit, is configured to predict head information after a predetermined time based on the information of the motion, adjust spatial audio based on the head information after the predetermined time to generate adjusted spatial audio and transmit the adjusted spatial audio to the transceiver unit, and transmit the adjusted spatial audio to the head-mounted device through the transceiver unit; the adjusted spatial audio is transmitted to the head-mounted device by the transceiver unit; and the predetermined time changes according to the information or the transmission standard of the wireless communication.

The present invention provides a circuitry (100) including a TIA stage (120). The TIA stage (120) is configured to receive a current signal (Iin) to generate an output voltage signal (Vout), wherein the TIA stage (120) includes a first transistor (M2), a second transistor (M3) and a high-pass filter (124). A gate electrode of the first transistor (M2) is coupled to the current signal, and the first electrode of the transistor is coupled to a supply voltage. The second transistor (M3) has a gate electrode, a first electrode and a second electrode, wherein the first electrode of the second transistor is coupled to the second electrode of the first transistor, and the second electrode of the second transistor is coupled to a ground voltage. The high-pass filter (124) is configured to filter the current signal (Iin) to generate a filtered current signal to the gate electrode of the second transistor (M3).

A primitive adaptive variable rate shading method includes generating a first absolute difference of depths in x direction (S202), generating a second absolute difference of depths in y direction (S204), adding the first absolute difference with the second absolute difference to generate a third absolute difference (S206), and setting the variable shading rate according to at least the plurality of thresholds, and the third absolute difference (S208).

The present invention provides a circuitry (100) including a regulator (110), a load circuit (120) and a signal processing circuit (130). The regulator (110) is configured to receive a supply voltage to generate a regulated supply voltage according to a reference voltage and a feedback signal. The load circuit (120) is supplied by the regulated supply voltage, wherein the load circuit (120) includes an internal sensing circuit to generate an internal sensing signal. The signal processing circuit (130) is configured to process the internal sensing signal to generate the feedback signal to the regulator.

A Wi-Fi device (112, 104) includes a wireless interface circuit (134, 124) and a control circuit (132, 122). The control circuit (132, 122) receives a timing profile of scheduled traffic of a non-Wi-Fi wireless communication device (114), and refers to the timing profile to instruct the wireless interface circuit (134, 124) to transmit at least one frame for triggering a non-primary channel access mechanism between the Wi-Fi device (112, 104) and another Wi-Fi device (104, 112).

The present invention provides a wireless communication method, which includes the steps of: establishing a link with another device; and transmitting a Bluetooth packet to the another device, wherein the Bluetooth packet includes a preamble, a control header and a payload, and a bandwidth used for transmitting the preamble and the control header is different from a bandwidth used for transmitting the payload.

A semiconductor package structure includes a package substrate and a semiconductor die. The package substrate includes a core structure, an integrated capacitor structure, and a redistribution layer. The integrated capacitor structure is embedded in the core structure. The redistribution layer is disposed over the integrated capacitor structure. The semiconductor die is disposed over the package substrate and is thermally coupled to the integrated capacitor structure through the redistribution layer.

A power management method includes: receiving an input video signal, wherein the input video signal comprises multiple frames; extracting at least one video feature from each of the multiple frames; performing a prediction operation according to the at least one video feature to generate a coarse prediction result, wherein the coarse prediction result is indicative of a value of a required power of the each of the multiple frames; and for the each of the multiple frames, adjusting a frequency of a video decoder (16, 206) according to a refined prediction result to drive the video decoder (16, 206), wherein the refined prediction result is an error calibrated version of the coarse prediction result.

An execution in parallel method for a graphic processing unit includes providing a plurality of threads (400), enabling a first program counter, and the first program counter running a first program on the plurality of threads (400). When receiving a fork instruction, enable a second program counter, and if a first active mask of the fork instruction is set as a pass mask, and a second active mask is set as a fail mask, the first program counter activates a first set of threads (410) corresponding to the pass mask. When the first set of threads is blocked, the second program counter activates a second set of threads (420) corresponding to the fail mask. When the second set of threads is blocked, the first program counter activates the first set of threads. When receiving a join instruction, disable the second program counter, and the first program counter activates the plurality of threads (450).

An integrated circuit structure is provided. The integrated circuit structure includes a substrate, a patterned ground shield structure, and a shielded circuit. The patterned ground shield structure is disposed above the substrate. The patterned ground shield structure includes a central portion and branches. The branches are connected to the central portion. The branches substantially extend radially from a central point of the central portion and surround the central portion. The shielded circuit including at least one conductive line is located directly above the patterned ground shield structure.

A method for processing memory commands in a computing system (100) comprises: transmitting, from a coherence hub (110) to a downstream cache subsystem (130), a plurality of sub-commands, each of the sub-commands corresponding to a cache line size; receiving, at the downstream cache subsystem (130), at least one of the plurality of sub-commands; in response to receiving the at least one sub-command, determining, by the downstream cache subsystem (130), a full address range of the data block; and performing, by the downstream cache subsystem (130), an optimized memory operation directed to a downstream memory subsystem (140).

A power control method includes measuring an internal resistance of a battery of the system (S210), measuring a maximum boot-up current of the system (S220), generating a voltage drop according to the internal resistance and the maximum boot-up current (S230), generating a minimum boot-up voltage according to a predetermined voltage and the voltage drop (S240), and performing a boot-up process using a setting with the minimum boot-up voltage where the battery is charged to at least the minimum boot-up voltage in the boot-up process (S250).

An electronic device is provided. The electronic device includes an antenna module (1) and a guiding structure (2). The antenna module (1) includes a plurality of antenna units (10) and a substrate (19). The antenna units (10) are arranged in a matrix on the substrate (19). The antenna units (10) include a first antenna unit (11) and a second antenna unit (12). The first antenna unit (11) transmits a first wireless signal (S1), and the second antenna unit (12) transmits a second wireless signal (S2). The guiding structure (2) is formed with a plurality of guiding through-holes (20). The guiding through-holes (20) correspond to the respective antenna units (10), and the guiding through-holes (20) include a first guiding through-hole (21) and a second guiding through-hole (22). The first guiding through-hole (21) guides the first wireless signal (S1) primarily along a first axis (A1), and the second guiding through-hole (22) guides the second wireless signal (S2) primarily along a second axis (A2). The first axis (A1) and the second axis (A2) extend outward from the substrate (19) separately.

A front-end-of-line, FEOL, floorplan (200) of an integrated circuit includes a plurality of FEOL components (202, 204, 206, 208), a non-rectangle-shaped empty region, a first FEOL dummy (218), and a second FEOL dummy (216). The non-rectangle-shaped empty region is located between the FEOL components (202, 204, 206, 208), and includes a first empty region (212) in a first direction and a second empty region (210) in a second direction perpendicular to the first direction, where the first empty region (212) has a first end connected to the second empty region (210). The first FEOL dummy (218) is inserted in the first empty region (212). The second FEOL dummy (216) is inserted in the second empty region (210). The first FEOL dummy (218) is separated from the second FEOL dummy (216) at the first end of the first empty region (212).

The present invention provides a circuitry (200) including an output driver (210) and an ESD lock circuit (250). The output driver (210) includes a first transistor (M1) and a second transistor (M2), wherein the first transistor (M1) is coupled between an I/O pad (202) and a ground voltage, and the second transistor (M2) is coupled between the I/O pad (202) and a supply voltage. The ESD lock circuit (250) is coupled between the I/O pad (202) and the ground voltage, and is configured to generate a control signal to control the first transistor (M1) according to a voltage at the I/O pad (202).

A semiconductor structure is provided. The semiconductor structure includes a substrate, electronic devices, and an interconnection structure. The electronic devices are disposed on the substrate. The electronic devices includes first gate structures. The interconnection structure including a first interconnection-level conductive trace is located directly above the electronic devices. The first interconnection-level conductive trace has first openings for exposing at least one of the first gate structures.

An oscillator circuit (100, 300) includes a first cross coupled pair (110, 310), a second cross coupled pair (120, 320), a resonant circuit (130) coupled between the first cross coupled pair (110, 310) and the second cross coupled pair (120, 320) and a first injection circuit (140-1, 340-1). The resonant circuit (130) includes a first node outputting a first voltage signal (VoscP) and a second node outputting a second voltage signal (VoscN). The first injection circuit (140-1, 340-1) is coupled to the first cross coupled pair (110, 310) and injects a first compensating current with a first predetermined phase to a predetermined node of the first cross coupled pair (110, 310).

A chip with electrostatic discharge protection is shown. The chip has an output driver and an electrostatic discharge (ESD) protection control circuit. The output driver has a first output driver transistor coupled between an input/output (I/O) pad of the chip and ground, and a second output driver transistor coupled between a power source and the I/O pad. The ESD protection control circuit has a first output terminal coupled to a control terminal of the first output driver transistor, to control the first output driver transistor for electrostatic discharge protection. The ESD control circuit is enabled in response to electrostatic disturbance at the I/O pad.

A laminate non-planar radio-frequency, RF, choke device includes a first RF choke (200). The first RF choke (200) has a first winding structure including a plurality of first conductive traces (202, 204) and a plurality of first vias (206, 208). The first conductive traces (202, 204) are formed on a first layer (L1) and a second layer (L3) of a laminate. The first vias (206, 208) are formed between the first layer (L1) and the second layer (L3) of the laminate. The first vias (206, 208) are stitched in a winding direction through the first conductive traces (202, 204).

The present invention provides a circuitry (100, 200, 300) including a driver (114, 214), a band-pass filter (120, 220), a routing trace (130, 230) and at least one receiver (140, 144, 240_1 - 240_N, 244_1 - 244_N) is disclosed. The driver (114, 214) is configured to generate a first signal. The band-pass filter (120, 220) is configured to filters the first signal to generate a second signal. The second signal passes through the routing trace (130, 230) to generate a third signal. The at least one receiver (140, 144, 240_1 - 240_N, 244_1 - 244_N) is configured to receive the third signal to generate an output signal.

A read-only memory, ROM, (100) includes a first ROM cell (104), a second ROM cell (106), and a third ROM cell (102). The first ROM cell (104) is configured to store a first data value of a ROM code, and includes a first meta-oxide-semiconductor, MOS, transistor (114). The second ROM cell (106) is configured to store a second data value of the ROM code, and includes a second MOS transistor (116), wherein a source node of the second MOS transistor is electrically connected to a drain node of the first MOS transistor (114). The third ROM cell (102) is configured to store a third data value of the ROM code, and includes a third MOS transistor (112), wherein a drain node of the third MOS transistor (112) is electrically connected to a source node of the first MOS transistor (114).

A wireless communication method includes: generating a plurality of duplicated frequency-domain segments (211_1 - 211_N), wherein each of the plurality of duplicated frequency-domain segments (211_1 - 211_N) includes a plurality of orthogonal frequency division multiplexing (OFDM) subcarrier tones; performing a phase rotation operation upon the plurality of duplicated frequency-domain segments (211_1 - 211 _N), including applying different phase rotations to different OFDM subcarrier tones within a same duplicated frequency-domain segment; and generating an OFDM signal according to an output of the phase rotation operation.

A memory controller in an integrated circuit system includes a receiver circuit that performs oversampling in time and voltage. The receiver circuit receives a data signal modulated with pulse amplitude modulation (PAM) having N signal levels from a memory module over a data lane, N > 2. The receiver circuit generates K samples by sampling the data signal at a sequence of time points in a unit time interval. The receiver circuit uses R voltage comparator blocks to generate R signal level estimates from the same sample out of the K samples. The voltage comparator blocks compare the same sample against (N-1) voltage thresholds with different offsets configured for different voltage comparator blocks. The receiver circuit identifies one of the N signal levels to which the data signal is mapped based on all signal level estimates generated from the K samples, and outputs a symbol corresponding to the identified signal level.

A memory controller in an integrated circuit system includes a transmitter module. The transmitter module receives from a processor a bit stream including a given symbol to be transmitted according to pulse-amplitude-modulation (PAM) with N signal levels on a first lane of multiple lanes. The lanes connect the transmitter module to a memory module in the integrated circuit system. The transmitter module identifies parameters for cancelling crosstalk from other lanes on the first lane. The parameters are identified based on a pending transition in signal levels in each of the other lanes. The transmitter module superposes the parameters of the other lanes on the given symbol to adjust the given symbol on the first lane. A digital-to-analog converter (DAC) on the first lane generates an analog output to the memory module. The analog output represents the adjusted given symbol.

A memory controller in an integrated circuit system performs bi-directional data transfer at a clock frequency between the memory controller and a memory module. The data transfer in a first direction is at a first pulse amplitude modulation (PAM) level and in a second direction at a second PAM level. When receiving an indication of an increased demand for data transfer in the first direction, the memory controller increases the first PAM level to a target PAM level for data transfer in the first direction while maintaining the clock frequency and the second PAM level in the second direction.

An integrated circuit includes a host die and a base die, both of which are disposed on an interposer. The host die includes multiple processors, and the base die includes at least two high-bandwidth memory (HBM) stacks that are disposed on the base die and communicate with the host die through the base die and the interposer. The at least two HBM stacks and the host die are arranged in a row with the host die at one end of the row. The base die further includes a controller circuit operative to multiplex outgoing data from the at least two HBM stacks to the host die, and demultiplex incoming data from the host die to the at least two HBM stacks.

A system and method for wireless communication are disclosed herein. In one embodiment, a wireless communication device receives an authentication reject message from a wireless communication node as part of a procedure. In response to receiving the authentication reject message, the wireless communication device deletes a network list to which the wireless communication node belongs. The network list may include a Public Land Mobile Network (PLMN) list or an equivalent Standalone Non-Public Network (SNPN) list. Additionally, the wireless communication device may reset various counters, including a registration attempt counter, an attach attempt counter, a service attempt counter, and a Tracking Area Update (TAU) attempt counter. The procedure may be a registration procedure, an attach procedure, or a Tracking Area Update (TAU) procedure. The system and method may also be implemented in an apparatus comprising a transceiver and a processor configured to perform the described operations.

A semiconductor device (1a) includes a substrate (100); a first terminal (A) and a second terminal (B); and a conductor (210) arranged on the substrate (100) between the first terminal (A) and the second terminal (B) to constitute an inductor (IN) shaped for forming a first loop (L1) and a second loop (L2) arranged side-by-side along a first direction (D1). A crossing (C) of the conductor (210) with itself is present between the first loop (L1) and the second loop (L2). The first loop (L1) and the second loop (L2) define a first enclosed area (A1) and a second enclosed area (A2), respectively. A first ground bar (GB1) traverses the first loop (L1) and a second ground bar (GB2) traverses the second loop (L2).

A system and method for managing network availability for Internet Protocol Multimedia Subsystem (IMS) services are disclosed herein. In one embodiment, the system and method are configured to maintain a plurality of networks indicated as unavailable for an IMS service, and delete a network from the plurality upon identifying that it becomes available for the IMS service. The method includes monitoring for network availability changes and updating network selection priorities accordingly. The system comprises a wireless communication device with a transceiver for communicating with wireless communication nodes and a processor for executing the network management operations.

A semiconductor package and a semiconductor package assembly are provided. The semiconductor package includes an interconnect structure, a chip, a redistribution layer (RDL), a molding compound, and through mold vias (TMVs). The chip is arranged on and coupled to the interconnect structure. The RDL is arranged on and coupled to the chip. The molding compound is arranged on the interconnect structure and encapsulates the chip and the RDL. The TMVs pass through the molding compound and are connected between the RDL and the interconnect structure. The chip includes a back-side connect structure, a transistor layer, a front-side connect structure and a carrier. The back-side connect structure is connected to the interconnect structure. The transistor layer is located on the back-side connect structure. The front-side connect structure is located on the transistor layer. The first carrier is located on and coupled to the interconnect structure.

A battery power computing method, applied to a battery and a corresponding electronic device (100), the electronic device comprising: a battery (101); and a processing circuit (103), configured to perform following steps: acquiring a battery resistance table of the battery (101), wherein the battery resistance table comprises first mapping relations between a plurality of battery resistances of the battery (101) and a plurality of battery power levels; acquiring a resistance conversion table, wherein the resistance conversion table comprises second mapping relations between a plurality of battery resistance conversions and a plurality of conditions of the battery (101); and measuring the battery power according to the first mapping relations and the second mapping relations, while charging or discharging the battery (101).