MediaTek Patente

A primitive adaptive variable rate shading method includes generating a first absolute difference of depths in x direction (S202), generating a second absolute difference of depths in y direction (S204), adding the first absolute difference with the second absolute difference to generate a third absolute difference (S206), and setting the variable shading rate according to at least the plurality of thresholds, and the third absolute difference (S208).

A power management method includes: receiving an input video signal, wherein the input video signal comprises multiple frames; extracting at least one video feature from each of the multiple frames; performing a prediction operation according to the at least one video feature to generate a coarse prediction result, wherein the coarse prediction result is indicative of a value of a required power of the each of the multiple frames; and for the each of the multiple frames, adjusting a frequency of a video decoder (16, 206) according to a refined prediction result to drive the video decoder (16, 206), wherein the refined prediction result is an error calibrated version of the coarse prediction result.

A front-end-of-line, FEOL, floorplan (200) of an integrated circuit includes a plurality of FEOL components (202, 204, 206, 208), a non-rectangle-shaped empty region, a first FEOL dummy (218), and a second FEOL dummy (216). The non-rectangle-shaped empty region is located between the FEOL components (202, 204, 206, 208), and includes a first empty region (212) in a first direction and a second empty region (210) in a second direction perpendicular to the first direction, where the first empty region (212) has a first end connected to the second empty region (210). The first FEOL dummy (218) is inserted in the first empty region (212). The second FEOL dummy (216) is inserted in the second empty region (210). The first FEOL dummy (218) is separated from the second FEOL dummy (216) at the first end of the first empty region (212).

The present invention provides a circuitry (200) including an output driver (210) and an ESD lock circuit (250). The output driver (210) includes a first transistor (M1) and a second transistor (M2), wherein the first transistor (M1) is coupled between an I/O pad (202) and a ground voltage, and the second transistor (M2) is coupled between the I/O pad (202) and a supply voltage. The ESD lock circuit (250) is coupled between the I/O pad (202) and the ground voltage, and is configured to generate a control signal to control the first transistor (M1) according to a voltage at the I/O pad (202).

A semiconductor structure is provided. The semiconductor structure includes a substrate, electronic devices, and an interconnection structure. The electronic devices are disposed on the substrate. The electronic devices includes first gate structures. The interconnection structure including a first interconnection-level conductive trace is located directly above the electronic devices. The first interconnection-level conductive trace has first openings for exposing at least one of the first gate structures.

An oscillator circuit (100, 300) includes a first cross coupled pair (110, 310), a second cross coupled pair (120, 320), a resonant circuit (130) coupled between the first cross coupled pair (110, 310) and the second cross coupled pair (120, 320) and a first injection circuit (140-1, 340-1). The resonant circuit (130) includes a first node outputting a first voltage signal (VoscP) and a second node outputting a second voltage signal (VoscN). The first injection circuit (140-1, 340-1) is coupled to the first cross coupled pair (110, 310) and injects a first compensating current with a first predetermined phase to a predetermined node of the first cross coupled pair (110, 310).

A chip with electrostatic discharge protection is shown. The chip has an output driver and an electrostatic discharge (ESD) protection control circuit. The output driver has a first output driver transistor coupled between an input/output (I/O) pad of the chip and ground, and a second output driver transistor coupled between a power source and the I/O pad. The ESD protection control circuit has a first output terminal coupled to a control terminal of the first output driver transistor, to control the first output driver transistor for electrostatic discharge protection. The ESD control circuit is enabled in response to electrostatic disturbance at the I/O pad.

A laminate non-planar radio-frequency, RF, choke device includes a first RF choke (200). The first RF choke (200) has a first winding structure including a plurality of first conductive traces (202, 204) and a plurality of first vias (206, 208). The first conductive traces (202, 204) are formed on a first layer (L1) and a second layer (L3) of a laminate. The first vias (206, 208) are formed between the first layer (L1) and the second layer (L3) of the laminate. The first vias (206, 208) are stitched in a winding direction through the first conductive traces (202, 204).

The present invention provides a circuitry (100, 200, 300) including a driver (114, 214), a band-pass filter (120, 220), a routing trace (130, 230) and at least one receiver (140, 144, 240_1 - 240_N, 244_1 - 244_N) is disclosed. The driver (114, 214) is configured to generate a first signal. The band-pass filter (120, 220) is configured to filters the first signal to generate a second signal. The second signal passes through the routing trace (130, 230) to generate a third signal. The at least one receiver (140, 144, 240_1 - 240_N, 244_1 - 244_N) is configured to receive the third signal to generate an output signal.

A read-only memory, ROM, (100) includes a first ROM cell (104), a second ROM cell (106), and a third ROM cell (102). The first ROM cell (104) is configured to store a first data value of a ROM code, and includes a first meta-oxide-semiconductor, MOS, transistor (114). The second ROM cell (106) is configured to store a second data value of the ROM code, and includes a second MOS transistor (116), wherein a source node of the second MOS transistor is electrically connected to a drain node of the first MOS transistor (114). The third ROM cell (102) is configured to store a third data value of the ROM code, and includes a third MOS transistor (112), wherein a drain node of the third MOS transistor (112) is electrically connected to a source node of the first MOS transistor (114).

A wireless communication method includes: generating a plurality of duplicated frequency-domain segments (211_1 - 211_N), wherein each of the plurality of duplicated frequency-domain segments (211_1 - 211_N) includes a plurality of orthogonal frequency division multiplexing (OFDM) subcarrier tones; performing a phase rotation operation upon the plurality of duplicated frequency-domain segments (211_1 - 211 _N), including applying different phase rotations to different OFDM subcarrier tones within a same duplicated frequency-domain segment; and generating an OFDM signal according to an output of the phase rotation operation.

A memory controller in an integrated circuit system includes a receiver circuit that performs oversampling in time and voltage. The receiver circuit receives a data signal modulated with pulse amplitude modulation (PAM) having N signal levels from a memory module over a data lane, N > 2. The receiver circuit generates K samples by sampling the data signal at a sequence of time points in a unit time interval. The receiver circuit uses R voltage comparator blocks to generate R signal level estimates from the same sample out of the K samples. The voltage comparator blocks compare the same sample against (N-1) voltage thresholds with different offsets configured for different voltage comparator blocks. The receiver circuit identifies one of the N signal levels to which the data signal is mapped based on all signal level estimates generated from the K samples, and outputs a symbol corresponding to the identified signal level.

A system and method for managing network availability for Internet Protocol Multimedia Subsystem (IMS) services are disclosed herein. In one embodiment, the system and method are configured to maintain a plurality of networks indicated as unavailable for an IMS service, and delete a network from the plurality upon identifying that it becomes available for the IMS service. The method includes monitoring for network availability changes and updating network selection priorities accordingly. The system comprises a wireless communication device with a transceiver for communicating with wireless communication nodes and a processor for executing the network management operations.

A semiconductor device (1a) includes a substrate (100); a first terminal (A) and a second terminal (B); and a conductor (210) arranged on the substrate (100) between the first terminal (A) and the second terminal (B) to constitute an inductor (IN) shaped for forming a first loop (L1) and a second loop (L2) arranged side-by-side along a first direction (D1). A crossing (C) of the conductor (210) with itself is present between the first loop (L1) and the second loop (L2). The first loop (L1) and the second loop (L2) define a first enclosed area (A1) and a second enclosed area (A2), respectively. A first ground bar (GB1) traverses the first loop (L1) and a second ground bar (GB2) traverses the second loop (L2).

A system and method for wireless communication are disclosed herein. In one embodiment, a wireless communication device receives an authentication reject message from a wireless communication node as part of a procedure. In response to receiving the authentication reject message, the wireless communication device deletes a network list to which the wireless communication node belongs. The network list may include a Public Land Mobile Network (PLMN) list or an equivalent Standalone Non-Public Network (SNPN) list. Additionally, the wireless communication device may reset various counters, including a registration attempt counter, an attach attempt counter, a service attempt counter, and a Tracking Area Update (TAU) attempt counter. The procedure may be a registration procedure, an attach procedure, or a Tracking Area Update (TAU) procedure. The system and method may also be implemented in an apparatus comprising a transceiver and a processor configured to perform the described operations.

An integrated circuit includes a host die and a base die, both of which are disposed on an interposer. The host die includes multiple processors, and the base die includes at least two high-bandwidth memory (HBM) stacks that are disposed on the base die and communicate with the host die through the base die and the interposer. The at least two HBM stacks and the host die are arranged in a row with the host die at one end of the row. The base die further includes a controller circuit operative to multiplex outgoing data from the at least two HBM stacks to the host die, and demultiplex incoming data from the host die to the at least two HBM stacks.

A memory controller in an integrated circuit system performs bi-directional data transfer at a clock frequency between the memory controller and a memory module. The data transfer in a first direction is at a first pulse amplitude modulation (PAM) level and in a second direction at a second PAM level. When receiving an indication of an increased demand for data transfer in the first direction, the memory controller increases the first PAM level to a target PAM level for data transfer in the first direction while maintaining the clock frequency and the second PAM level in the second direction.

A memory controller in an integrated circuit system includes a transmitter module. The transmitter module receives from a processor a bit stream including a given symbol to be transmitted according to pulse-amplitude-modulation (PAM) with N signal levels on a first lane of multiple lanes. The lanes connect the transmitter module to a memory module in the integrated circuit system. The transmitter module identifies parameters for cancelling crosstalk from other lanes on the first lane. The parameters are identified based on a pending transition in signal levels in each of the other lanes. The transmitter module superposes the parameters of the other lanes on the given symbol to adjust the given symbol on the first lane. A digital-to-analog converter (DAC) on the first lane generates an analog output to the memory module. The analog output represents the adjusted given symbol.

A battery power computing method, applied to a battery and a corresponding electronic device (100), the electronic device comprising: a battery (101); and a processing circuit (103), configured to perform following steps: acquiring a battery resistance table of the battery (101), wherein the battery resistance table comprises first mapping relations between a plurality of battery resistances of the battery (101) and a plurality of battery power levels; acquiring a resistance conversion table, wherein the resistance conversion table comprises second mapping relations between a plurality of battery resistance conversions and a plurality of conditions of the battery (101); and measuring the battery power according to the first mapping relations and the second mapping relations, while charging or discharging the battery (101).

A semiconductor package and a semiconductor package assembly are provided. The semiconductor package includes an interconnect structure, a chip, a redistribution layer (RDL), a molding compound, and through mold vias (TMVs). The chip is arranged on and coupled to the interconnect structure. The RDL is arranged on and coupled to the chip. The molding compound is arranged on the interconnect structure and encapsulates the chip and the RDL. The TMVs pass through the molding compound and are connected between the RDL and the interconnect structure. The chip includes a back-side connect structure, a transistor layer, a front-side connect structure and a carrier. The back-side connect structure is connected to the interconnect structure. The transistor layer is located on the back-side connect structure. The front-side connect structure is located on the transistor layer. The first carrier is located on and coupled to the interconnect structure.

Devices including a substrate structure with laterally offset ground vias and metal balls are provided. A device may include a substrate, a plurality of first ground vias, and a plurality of first metal balls. The plurality of first ground vias may be formed within the substrate and surrounding a plurality of signal vias. The plurality of first metal balls may be disposed on the substrate and electrically coupled to the plurality of first ground vias. One first metal ball may be electrically coupled to one first ground via. A part of the plurality of first ground vias may be laterally offset from a corresponding part of the plurality of first metal balls along a direction orthogonal to the substrate.

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