Nexperia Patente

A goal of the current disclosure is to provide a module for electric circuitry having lower parasitic inductance. This is achieved because in an example, the module for an electric circuit comprises a substrate comprising electric circuitry containing a Direct Current, DC, pad and an Alternating Current, AC, pad. In particular, a first group of semiconductor dies is mounted on the AC pad, whereas a second group of semiconductor dies is mounted on the DC pad. Furthermore, the module comprises a first DC terminal electrically connected to the first group of semiconductor dies, a second DC terminal being electrically isolated from the first DC terminal, and at least electrically connected to the DC pad of the electric circuitry, and an Alternating Current, AC, terminal at least connected to the AC pad of the electric circuitry. Also, the module comprises first connecting means for electrically connecting the first group of semiconductor dies to the AC pad, second connecting means for electrically connecting the second group of semiconductor dies to the DC pad, and third connecting means for electrically connecting the second group of semiconductor dies to the AC pad.

The object of the present disclosure is to provide semiconductor assembly allowing to avoid cutting of the lead frame while separating the adjacent semiconductor assemblies, and allowing to perform sawing of the assemblies before trimming off the leads, for small packages. According to the first aspect, the object of the present disclosure has been achieved by providing a semiconductor assembly comprising a semiconductor die held in an encapsulant, wherein the encapsulant has a top part and a bottom part with leads extending out of the two opposite sides of the bottom part, wherein the bottom part of the encapsulant has a smaller width than the top part of the encapsulant, when measured along the lead bearing surfaces of the encapsulant. Providing a bottom part narrower than the top part allows for partial package sawing, where only the top part of the encapsulant is cut and cutting of the lead frame is avoided.

A method of manufacturing a semiconductor package assembly and a semiconductor package is provided, with integral electrically conductive layers seeded on the first die side and on the part of the at least one lead frame terminal.

A continuous time comparator, comprising a first Field Effect Transistor, FET, (Mn1) arranged for receiving a first input signal, and a second FET (Mn2) arranged for receiving a second input signal, two branches, a first of said two branches comprises a first transistor (Mp1) and a second of said two branches comprises a second transistor (Mp2), wherein said first of said two branches is connected to said first FET (Mn1) and wherein said second of said two branches is connected to said second FET (Mn2), a first dynamic clamp circuitry connected in parallel over said first branch, wherein said first dynamic clamp circuitry is arranged to dynamically clamp a voltage at a gate of a first output transistor (Mp4), and a second dynamic clamp circuitry connected in parallel over said second branch, wherein said second dynamic clamp circuitry is arranged to dynamically clamp a voltage at a gate of a second output transistor (Mp3), said first and second output transistors (Mp3, Mp4) for providing an output of said comparator and for providing an inverting output of said comparator.

An ElectroStatic Discharge, ESD, protection device for protecting an integrated circuit, said ESD protection device comprising a two-stage protection circuit arranged to be connected to an input of the integrated circuit, wherein the two-stage protection circuit comprises a first protection stage connected to an external input and to ground, wherein the first protection stage is arranged for, when triggered, providing a low ohmic path to said ground, an impedance connected to the external input and arranged to be connected to the input of the integrated circuit, a second protection stage arranged to be connected to the input of the integrated circuit and connected to ground, wherein the second protection stage is arranged for, when triggered, providing a low ohmic path to said ground, a triggering mechanism arranged for triggering the second protection stage with the first protection stage.

A method for manufacturing a semiconductor device is proposed, the method comprising: a) providing a lead frame structure with a first lead frame surface and an opposite second lead frame surface, where the lead frame structure comprises an outer frame, an at least one lead frame die pad, an at least one lead frame terminal, and the plurality of lead frame junctions. The at least one lead frame die pad and/or the at least one lead frame terminal are accommodated in a floating orientation within the lead frame structure; b) providing a pre-binding material for fixing the floating lead frame die pads and/or floating lead frame terminals within the lead frame structure; c) mounting an at least one semiconductor die on the at least one lead frame die pad; d) mounting an at least one connecting element for creating an electrical connection between the at least one semiconductor die and the at least one lead frame terminal, e) encapsulating by a mold compound the lead frame structure, the at least one semiconductor die, the at least one connecting element and the pre-binding material to form the semiconductor device, such that at least part of the at least one lead terminal is exposed and thereby forming an encapsulated semiconductor device. According to the second aspect of the disclosure, there is provided a semiconductor device as manufactured in accordance with the method according to the disclosure.

The present disclosure provides a semiconductor package comprising: a semiconductor die attached to a lead frame having lead terminals; at least one bond clip connecting the die to a lead terminal; a die top solder connecting the bond clip and the die, and an encapsulant. The clip comprises a die attachment portion having a die attachment portion side structured to be connected to the die, whereby said side is provided with a cavity functioning as an expansion space for the die top solder. This allows to prevent the molten die top solder from spreading toward die edge and lead terminals, since the molten solder flow is directed inward to the cavity, instead of flowing outward. A bond clip for use in a semiconductor package is also provided, comprising a cavity functioning as an expansion space for the die top solder. The cavity is arranged at the die attachment portion side of the bond clip.

A semiconductor device and a semiconductor package including such semiconductor device are presented. The semiconductor device includes one or more dies, a power source clip, a signal source clip, a signal gate clip and a power drain clip, with each clip electrically connected to each of the dies. A Kelvin source connection is integrated on the signal source clip. At at least one of the dies an angle between a path of a power source current between the power source clip and a die and a path of a signal source current between the signal source clip and the die is equal to or larger than 90°.

An encapsulated semiconductor package is proposed, comprising a plurality of rivets, and a plurality of connection pins, each connection pin having a pin tip and a pin end, wherein the plurality of rivets are disposed in the encapsulant of the encapsulated semiconductor package, each rivet having a first rivet end and a second rivet end, each rivet being electrically mounted with a first rivet end on a corresponding bond pad of the semiconductor package; each rivet comprises a rivet cavity configured to receive the pin tip of the connection pin; the pin tip of the connection pin is configured as a press-fit pin tip having an outer diameter larger than an inner diameter of the rivet cavity and configured for friction-based engagement with the rivet cavity.

According to a first example of the disclosure a single cell lateral oriented Metal-Oxide-Semiconductor device is proposed. The device comprises a semiconductor comprising a first surface; a first region having a first conductivity type; an at least one pair of trenches, wherein each trench extends from the first surface into the first region, each of the trench comprising an insulating element and a conductive element, wherein the insulating element is arranged in between the conductive element and the first region, and wherein the insulating element has a substantially uniform width; a second region having a second conductivity type being different from the first conductivity type, wherein the second region extends from the first surface into the first region and is located on an outer side of the pair of trenches and adjacent to the trench, and a third region having a second conductivity type being different from the first conductivity type, wherein the third region extends from the first surface into the first region and is located in between trenches and adjacent to the trench, and an insulating region on the first surface comprising openings to provide electrical contacts to the second and third region.This disclosure also relates to a method of manufacturing a lateral oriented Metal-Oxide-Semiconductor device.

A semiconductor device is proposed, comprising a substrate, at least a first semiconductor die having a first die surface and a second die surface opposite to the first die surface, wherein the at least one semiconductor die is mounted with the first die surface on the substrate, and at least one heat transfer component comprising a spatial configuration composed of a first component face and a second component face spaced apart from each other defining a spatial enclosure comprising a heat transfer medium, wherein the at least one heat transfer component is in heat exchanging contact with the second die surface and the substrate.

A Switched Mode Power Supply, SMPS, circuit, comprising an SMPS comprising a driver and a low-side switch responsible for regulating power flow to an output of said SMPS circuit, wherein said driver is arranged for controlling said low-side switch and wherein said SMPS operates in a second power domain, a level-shifter circuit arranged for translating signals from a first power domain to the second power domain, an ElectroStatic Discharge, ESD, protection circuit arranged for detecting an ESD event and for enabling said low-side switch upon detection of said ESD event, wherein said ESD protection circuit is implemented in said level-shifter circuit and is connected to a voltage supply in said first power domain.

A method of manufacturing a plurality of semiconductor devices, wherein the method comprises the steps of providing a carrier layer comprising a first surface and a second surface opposite to the first surface, attaching a first metallization layer to the first surface of the carrier layer, transferring a metal paste to the first metallization layer for creating first patterned metal pads and dicing the carrier layer to provide the plurality of semiconductor devices.

In the first aspect of the present disclosure, there is provided a method of manufacturing a semiconductor device (100), comprising the steps of:- providing a substrate (110);- mounting a semiconductor die (120) having a first die surface and a second die surface opposite to the first die surface, with its first die surface to the substrate;- mounting a spacer (140) having a first spacer surface and a second spacer surface opposite to the first spacer surface, with its first spacer surface on the second die surface;- fusing bonding means (150) to the second spacer surface by means of ultrasonic fusing.

A semiconductor device, a semiconductor package comprising such semiconductor device and a method of manufacturing such semiconductor package are presented. The semiconductor device comprises a die (202) and a leadframe (204). The semiconductor device further comprises a wire-bond interconnect structure comprising one or more pairs (208) of wires. Herein, a pair (208) of wires comprises two wires that are bonded together at one end at the die (202) and that are bonded together on the other end at the leadframe (204).

The present disclosure relates to a method of manufacturing a semiconductor device, specifically of the connection of a bonding wire to a semiconductor die. In a first aspect of the disclosure, there is provided a method of manufacturing a semiconductor device, comprising the steps of:- providing a semiconductor die onto a substrate;- applying a paste to said semiconductor die;- connecting a bonding wire to said paste by means of ultrasonic motion.

A method limits an inrush current of a buck converter having an inductor element during a startup period in which the buck converter is first enabled. The inrush current flows through the inductor element by enabling a zero current detection algorithm for a first few operational cycles. A system is also configured to limit the inrush current of a buck converter having an inductor element during a startup period in which the buck converter is first enabled.

A Switched Mode Power Supply (SMPS) with a switching stage has a high-side switch, a low-side switch, and an output inductor. The SMPS also has control circuitry for controlling the high-side switch and the low-side switch based on a clock signal. The control circuitry is configured to detect that an output voltage of the switching stage deviates from a reference voltage and thereby enable negative valley regulation. Upon enabling negative valley regulation, the control circuitry detects that a current flowing through the inductor falls below a threshold and, based on the detection, initiates a next clock cycle of the clock signal.

A method for soft recovery for switched mode power supplies includes: (a) detecting a drop of the output voltage value FB; (b) starting the output voltage values FB recovery using a current FB value stored as a Vref start value from which the recovery is to be made; (c) detecting the start of the recovery of the output voltage; (d) generating a timing pulse; (e) measuring a FB value on the rising edge of the timing pulse and comparing the FB value with the Vref value, and if the FB value is greater than the Vref value, storing the FB value and setting the FB value as the new Vref start value from which the recovery is to be made going forward; and (f) repeating step (d) and (e), after a preset time delay, until the FB value is less than or equal to the Vref for the FB value.

A clip-bonded semiconductor package comprising: a semiconductor die comprising a bond pad on a top side of the semiconductor die, wherein the bond pad is arranged to receive a bond clip, the bond clip arranged to provide electrical connection to the bond pad via a connection part of the bond clip, wherein the bond clip further comprises a buffer layer provided to at least the connection part, wherein a hardness of a material of the buffer layer is lower than a hardness of a material of the bond clip.

A device is proposed for stretching a wafer foil that is held by a film frame carrier and on which a plurality of electronic components is arranged. In particular, the device comprises a holding member for holding the film frame carrier; a tensioning member structured to engage with the wafer foil. Additionally, it comprises a drive that is structured to move at least the tensioning member from a first operational position, at which an intermediate distance between adjacent electronic components is minimal, towards a second operational position, at which the intermediate distance between adjacent electronic components is maximal, wherein a foil engaging part of the tensioning member engaging with the wafer foil is configured to move from the first operational position towards the second operational position in a direction perpendicular as well as in a direction parallel to a plane defined the wafer foil.

A bidirectional bootstrapped switch device, comprising: a switch transistor having a gate, a source, and a drain configured for bidirectional switching between source and drain; and a gate control circuit arranged to provide first and second voltage levels to the gate of the switch transistor in response to a control signal, wherein the first voltage level, applied to the gate in response to a first state of the control signal, being generated by rapidly discharging the gate voltage to a threshold voltage of the switch transistor via a first discharge path, resulting in a high discharge current of the switch transistor, and the second voltage level, applied to the gate in response to a second state of the control signal, being generated by slowly discharging the gate voltage below the threshold voltage of the switch transistor via a second discharge path resulting in a low discharge current of the switch transistor.

The present disclosure proposes a semiconductor device as well as a method for manufacturing such semiconductor device related to a method of generating a dual exposed drain with common gate and source clip-bonded package for reverse battery protection. The semiconductor device comprises a first lead frame with an external first lead frame terminal and a first die paddle, a second lead frame with an external second lead frame terminal and a second die paddle, a common clip with an external source clip terminal, a two source contacts, a common gate clip with an external common clip gate terminal, a clip contact and a gate clip contact, a first semiconductor die with a first die gate terminal, a first die source terminal, and a first die drain terminal, a second semiconductor die with a second die gate terminal, a second die source terminal, and a second die drain terminal.

A power module comprising a three-level active neutral point clamp topology comprising at least six devices comprising two inner switches, two outer switches and two clamping devices, a sandwich structure comprising a first sub-assembly, wherein the first sub-assembly comprises the first inner switch, the first clamping device and the first inner switch and a second sub-assembly, wherein the second sub-assembly comprises the second inner switch, the second clamping device and the second inner switch, wherein the sandwich structure is arranged such that the first inner switch faces the second inner switch, such that the first outer switch faces the second clamping device and such that the first clamping device faces the second outer switch, a conductive connection element connecting the first and second inner switches.

The present invention disclosures a semiconductor device preferably a MOSFET transistor, having a EPI layer which is made of semiconductor material such as silicon. The EPI layer has a top surface and a bottom surface opposite to the front surface. The proposed MOSFET is a trench type transistor with the source-polysilicon element embedded in the trench formed in the substate

A method of manufacturing a split-gate trench in a semiconductor material, said method comprising the steps of: providing a gate trench in said semiconductor material, said gate trench having an oxide material provided at a bottom side of said gate trench and provided on a sidewall of said gate trench, said gate trench further comprising a polysilicon material provided on top of said oxide material that is provided at said bottom side of said gate trench; providing a nitride spacer against the oxide material that is provided at the sidewall of the gate trench; growing an inter-poly oxide, IPO, on top of said polysilicon material, wherein said nitride spacer at least reduces growth of IPO at said oxide material provided at said sidewall, wherein IPO is grown preferentially and locally at said oxide material provided at a bottom-end of said nitride spacer; removing said nitride spacer.

According to a first example of the disclosure, a press fit pin is proposed. A press fit pin comprising a sheet spring, a roll spring, a metal pillar, a base, wherein the base comprises a bottom part and a cylinder part, wherein the cylinder part on one side is connected to the bottom part and on the other side comprises a closing means, wherein the bottom part, the cylinder part and a flange are forming a blind hole, wherein the metal pillar comprises a top metal pillar part, a bottom metal pillar part, a first rim located at the outer end of the top metal pillar part, and a second rim located between the top metal pillar part and the bottom metal pillar part, and wherein the bottom metal pillar part is connected to the first rim with a connecting portion having smaller diameter than the bottom metal pillar part, wherein the sheet spring is surrounding the top metal pillar part and is placed between the first rim and the second rim, wherein the roll spring that serves as a stress buffer rests on the bottom part of the base and on the outer end of the bottom metal pillar part, wherein the bottom metal pillar part is inserted into the base such that the flange is surrounding the connecting portion in a movable manner and wherein a diameter of the blind hole in a section defined by the flange is smaller than a diameter of the bottom metal pillar part and the second rim.

The present disclosure proposes a carrier tape for accommodating a plurality of dual in-line semiconductor packages. The carrier tape is formed of a flexible elongated tape having a first elongated tape side and a second elongated tape side oriented parallel to the first elongated tape side. One single elongated recess is provided between and extending along both elongated tape sides. Additionally, the carrier tape comprises a plurality of spacing elements present within the single elongated recess, which spacing elements orient - during use - the plurality of dual in-line semiconductor packages within the single elongated recess in a side-by-side manner, such that at least one lead terminal of a first semiconductor package interleaves with lead terminals of a neighboring semiconductor package.

An encapsulated semiconductor package is proposed at least comprising a lead frame made from an electrically conductive metal material as well as at least two terminals; at least one semiconductor die structure having a first die side and a second die side opposite to the first die side and mounted with its second die side on the lead frame; a plurality of connections electrically and mechanically connecting the at least one semiconductor die structure with the at least two terminals of the lead frame; at least one heat sink pad mounted to the first die side of the semiconductor die structure; and a moulding resin encapsulating the lead frame, the at least one semiconductor die structure, the plurality of connections, the at least one heat sink pad and the at least two terminals leaving at least a portion of the heat sink pad and at least a portion of the at least two terminals exposed, and forming the semiconductor package having a heat sink pad package surface side and a lead frame package surface side, wherein the moulding resin at the heat sink pad package surface side and/or the lead frame package surface side is provided with at least one resin spacer element extending from the respective package surface side.

A lateral oriented transistor embodied in a semiconductor material, comprising a first group of directly adjacently placed transistor cells, a second group of directly adjacently placed transistor cells, wherein said second group is spaced apart from said first group thereby providing a spacing, wherein each of said transistor cells comprises a drain, a source and a gate, wherein said lateral oriented transistor further comprises a gate interconnect placed in said spacing between said first and second group, wherein said gate interconnect connects to said gates of said transistor cells

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