Samsung Electronics Patente

Provided is a method of inspecting semiconductor devices, the method including selecting a type of a target structure and a type of a target defect to be inspected, selecting a filter based on the target structure and the target defect, performing an ultrasonic signal simulation based on the target structure, selecting, based on the ultrasonic signal simulation, a type of a probe configured to generate an ultrasonic signal by applying a vibration to the semiconductor device, setting a frequency of the vibration based on the ultrasonic signal simulation, generating the ultrasonic signal by applying, using the tip, the vibration to the semiconductor device, measuring the ultrasonic signal, processing the measured ultrasonic signal using the selected filter, performing a fitting for each of a signal generated by the ultrasonic signal simulation and the measured ultrasonic signal processed by the selected filter, and determining an accuracy of the fitting.

Provided are systems, methods, and apparatuses for short-wave infrared pixels based on non-scattering nanostructures. In one or more examples, a pixel of a of an image sensor comprises a back reflector (205) formed on a substrate, the back reflector being configured to reflect electromagnetic radiation; a first doped region of a first semiconductor formed adjacent to the back reflector (205); an absorption region of a second semiconductor configured as a photodetector (210) of the pixel, the absorption region being formed adjacent to at least a portion of the first doped region; a second doped region of the first semiconductor formed adjacent to the absorption region, the second doped region being configured to pass the electromagnetic radiation to the absorption region; and a nanostructure (230) formed adjacent to the second doped region, the nanostructure (230) being configured to: steer light that passes through the nanostructure (230) towards the absorption region; and steer, towards the absorption region, a portion of the light that reflects off the back reflector (205).

Methods and devices for performing channel sounding, including: receiving a channel sounding signal generated based on a sounding sequence and an artificial noise symbol from the second electronic device; subtracting the artificial noise symbol from the channel sounding signal to reconstruct the sounding sequence; calculating a travel time between the first electronic device and the second electronic device based on the sounding sequence; and determining a distance between the first electronic device and the second electronic device based on the travel time.

A method and an apparatus for performing a read operation on a memory block of a storage device. The method includes determining an optimal read level voltage for a current memory block, based on a failure of a read operation performed on the current memory block; performing, based on the optimal read level voltage determined for the current memory block, one of: determining a recalibrated read level voltage for an existing read level cluster among one or more existing read level clusters created previously for one or more memory blocks of the storage device; and creating a new read level cluster with respect to the optimal read level voltage; and performing, based on a subsequent read operation request for the current memory block, the read operation on the current memory block based on the recalibrated read level voltage or the new read level voltage.

A method may include accessing, by at least one host, using a first memory access link between a switch and a first memory device, data at the first memory device, and transferring, based on a throughput of the first memory device, using a second memory access link between the switch and a second memory device, a portion of the data from the first memory device to the second memory device. The method may further include accessing, by the at least one host, using the second memory access link, the portion of the data at the second memory device. The method may further include selecting, based on the throughput of the first memory device, one of the at least one host to perform the transferring.

A memory device includes a memory cell array including memory cells arranged in a matrix, the memory cell array including a first memory cell (MC<p>) and a second memory cell (MC<p+1>) arranged in a column direction, a first bitline and a second bitline connected to the first memory cell (MC<p>) and the second memory cell (MC<p+1>), and a strap circuit (SC) provided between the first memory cell (MC<p>) and the second memory cell (MC<p+1>). Each of the first and second bitlines includes a first sub-bitline (BL<a>, BL'<a>) connected to the strap circuit (SC) and the first memory cell (MC<p>), a second sub-bitline (BL<b>, BL'<b>) connected to the strap circuit (SC) and the second memory cell (MC<p+1>), and a third sub-bitline (BL<c>, BL'<c>) connected to the strap circuit (SC) through the first sub-bitline (BL<a>, BL'<a>).

Storage systems and methods of operating storage systems are provided. In one aspect, a storage system includes: a host (100) configured to provide power voltage, and a storage device (200) configured to generate a plurality of candidate voltages based on the power voltage (S103), generate analysis data (S105) including a plurality of state data indicating a state of the storage device by applying each of the plurality of candidate voltages to a host interface, and drive the host interface with a driving voltage determined based on the analysis data (S115), wherein the host interface configured to transmit and receive a plurality of packets with the host (100).

A nonvolatile memory device (11A) includes a memory cell array including a plurality of planes (PLN1-PLNn), a page buffer circuit (PBC) connected to the memory cell array through a plurality of bitlines and comprising at least one cache latch, and a plurality of input/output pads (DQ1-DQk) connected to the page buffer circuit through a plurality of data lines and configured to transmit data to and receive data from a memory controller (12A). A command set may include at least one of cache latch address information or input/output pad address information, and the nonvolatile memory device is configured to perform a readout operation or a write operation based on at least one of the cache latch address information or the input/output pad address information included in the command set.

A semiconductor device includes a backside wiring line including a first side and a second side opposite to the first side in a first direction, a lower pattern on the first side of the backside wiring line, the lower pattern including a first side and a second side opposite to the first side in the first direction, where the second side of the lower pattern faces the backside wiring line, a sheet pattern on the first side of the lower pattern, and that is spaced apart from the lower pattern in the first direction, a first source/drain pattern on the lower pattern and connected to the sheet pattern, and an active region insulating pattern contacting the lower pattern, the active region insulating pattern including a line portion and a protruding portion, the line portion of the active region insulating pattern extending along the second side of the lower pattern.

A semiconductor memory device includes cell and peripheral structures. The cell structure includes first local bit lines extending in a vertical direction and spaced apart in a first horizontal direction, second local bit lines extending in the vertical direction and spaced apart from the first local bit lines in a second horizontal direction, a first global bit line extending in the first horizontal direction and electrically connected to the first local bit lines, and a second global bit line extending in the first horizontal direction and electrically connected to the second local bit lines. The peripheral circuit structure includes a peripheral circuit transistor, a first transistor electrically connected to the peripheral circuit transistor and the first global bit line, and a second transistor electrically connected to the peripheral circuit transistor and the second global bit line. The semiconductor memory device is configured to selectively turn on the first and second transistors in a complementary manner.

A method of forming a TFR and a semiconductor device are provided. The method includes depositing a first interlayer dielectric, ILD, film (305) on a substrate (205) to define a vertical dimension of the TFR; patterning a first photoresist using a photomask to define a horizontal dimension of the TFR; etching the first ILD film (305) using the patterned first photoresist to form a trench in the first ILD film (305); and depositing a resistive thin film material (405) on the first ILD film and within the trench.

An integrated circuit device includes at least one nanosheet, a pair of source/drain regions contacting the at least one nanosheet, a gate line between the pair of source/drain regions in a first horizontal direction and surrounding the at least one nanosheet, an insulating wall structure having a first sidewall contacting the pair of source/drain regions and facing the gate line, a gate dielectric film surrounding the gate line, and a pair of blocking insulating spacers arranged, in a plan view, in a gap area between the first sidewall and the gate line, in a second horizontal direction, and respectively contacting the pair of source/drain regions, wherein the pair of blocking insulating spacers are spaced apart from one another in the first horizontal direction in the gap area and each include a portion contacting the gate dielectric film and a portion contacting the first sidewall of the insulating wall structure.

Provided are systems and methods for providing a memory group. The system includes a first memory device (MD1) associated with a first host (H1), the first memory device (MD1) including a first memory (LM1), at least a first portion of the first memory (LM1) being a first shared memory (LMA1) that is configured to receive a first transaction request associated with a first data operation, the first transaction request from outside of the first host (H1), a first local-memory manager (LMM1) configured to manage the first shared memory (LMA1), and a first access gateway (AG1) of the first memory device (MD1), the first access gateway (AG1) configured to determine, based on a first data structure of the first memory device (MD1), to route the first transaction request to the first shared memory (LMA1).

An integrated circuit device includes an engineering change order, ECO, transistor cell structure (102) including a first region (I) and a second region (II) adjacent the first region (I), and a backside power rail (105b) extending in a first direction (X) under the ECO transistor cell structure (102). The first region (I) of the ECO transistor cell structure (102) is free of overlap with the backside power rail (105b) in a second direction (Y) that is perpendicular to the first direction (X). The second region (II) of the ECO transistor cell structure (102) overlaps the backside power rail (105b) in the second direction (Y), and includes one or more conductive elements (108f) that electrically connect the backside power rail (105b) to a frontside power rail (115f). Related devices and revision methods are also discussed.

Provided is a light-emitting device including an epitaxial structure that includes first, second, and third light-emitting structures having widths increasing in a vertical direction and each including a p-type semiconductor layer, an active layer, and an n-type semiconductor layer, first, second, and third p-electrodes, at least one of which has a conductive via structure, are on the epitaxial structure and respectively contact the p-type semiconductor layers of the first, second, and third light-emitting structures, an n-common electrode including an n-common portion on the epitaxial structure, and n-electrode portions extending from the n-common portion and respectively contacting side surfaces of the n-type semiconductor layers of the first, second, and third light-emitting structures, and a separation structure separating side surfaces of the p-type semiconductor layers and the active layers of the first, second, and third light-emitting structures from the n-common electrode.

Disclosed is an electronic apparatus. The apparatus includes: a memory storing instructions; and at least one processor including processing circuitry, wherein, if executed individually or collectively by the at least one processor, the instructions cause the electronic apparatus to: obtain a persona corresponding to a query among a plurality of personas corresponding to content based on a database if user input corresponding to the query related to the content is received; and provide a response corresponding to the query based on the obtained persona, the plurality of personas being based on a knowledge graph corresponding to the content and the database.

According to various embodiments, an electronic device and an operation method of the electronic device are provided. The electronic device may include a plurality of antennas including a first antenna, a second antenna, a third antenna, and a fourth antenna, first TRx circuitry electrically connected to the first antenna, first Rx circuitry electrically connected to the second antenna, second TRx circuitry electrically connected to the third antenna, second Rx circuitry electrically connected to the fourth antenna, memory storing a computer program including instructions, and at least one processor, wherein the instructions are configured to, when executed by the at least one processor, cause the electronic device to, while transmitting a signal and receiving a primary Rx signal via the first antenna and receiving a diversity Rx signal via the third antenna, identify the number of spatial streams in response to satisfying a condition in which Tx antenna switching using the first and third antennas is activated, in case that the number of spatial streams is equal to or less than a designated number, control the first Rx circuitry to receive the primary Rx signal via the second antenna and control the second Rx circuitry to receive the diversity Rx signal via the fourth antenna while performing the Tx antenna switching and, as the Tx antenna switching is completed, control the second TRx circuitry to transmit the signal and receive the primary Rx signal via the third antenna and control the first TRX circuitry to receive the diversity Rx signal via the first antenna, and in case that the number of the spatial streams exceeds the designated number, transmit, to a base station, a signal requesting to configure the number of the spatial streams to be equal to or less than the designated number, and as the number of the spatial streams is changed to be less than or equal to the designated number, control the first Rx circuitry to receive the primary Rx signal via the second antenna and control the second Rx circuitry to receive the diversity Rx signal via the fourth antenna while performing the Tx antenna switching.

Methods and devices are provided in which a volume manager determines a bucket of a variable-granularity volume map, VVM, for block volume storage, based on a corresponding volume logical block address, vLBA, set; and determines an entry for the vLBA set in the VVM or a fine-grained volume map, FVM, for the block volume storage, based on the determined bucket comprising at least one empty entry or entries of the VVM occupied, wherein the FVM comprises a higher granularity than the VVM.

A device, system, and method are disclosed for processing-in-memory, PIM, compression. In an embodiment, a method includes obtaining, by an input/output sense amplifier, IOSA (204), from an associated RAM bank (202), compressed data (702); sending, by the IOSA (202), the compressed data (702) divided into a plurality of portions (704); receiving, by a respective decompressor of a plurality of decompressors (306) of a PIM block (212) associated with the RAM bank (202), a respective portion of the compressed data (702); decompressing, by the respective decompressor, the respective portion of the compressed data to obtain a respective portion of decompressed data; and sending, by the respective decompressor, the respective portion of the decompressed data to a respective Arithmetic Logic Unit, ALU, of a plurality of ALUs (308) of the PIM block (212) for processing.

A system (100) and a method are disclosed for wireless communication. The method includes transmitting, by a first access point, AP (101), capability information indicating one or more multi-access point coordination, MAPC, schemes; and transmitting, by the first AP (101), an MAPC negotiation indication indicating an enabled state or a disabled state for MAPC negotiation.

A device, system, and method are disclosed for efficiently enabling Processing-in-Memory, PIM, or processing-near-memory, PNM, compression on mobile systems on a chip, SoC. In an embodiment, a memory device (310) includes a cryptographic engine, CE (316), wherein the memory device (310) is configured to receive encrypted data via a memory input/output, IO, bus (320), and the CE (316) is configured to decrypt the encrypted data to obtain decrypted data. The memory device (310) can further comprise a PIM or PNM device (314) configured to process the decrypted data.

A circuit device (100) includes a semiconductor substrate (102) having a first transistor structure (104). The first transistor structure includes at least one first channel region (106) extending between first source/drain regions (108), first source/drain contacts (110) on the first source/drain regions, respectively, and a first gate (112) on the at least one channel region between the first source/drain contacts. A first spacer (115) electrically isolates one of the first source/drain regions from one of the first source/drain contacts thereon. Related devices and fabrication methods are also discussed.

Semiconductor devices and methods of manufacturing the semiconductor devices are provided. For example, a semiconductor device (1) may include: a stack of semiconductor layers including a first semiconductor layer (200B), and a second semiconductor layer (200C) stacked on the first semiconductor layer (200B) in a first direction (Z); a heat sink (300) stacked on the second semiconductor layer (200C) in the first direction (Z); and a heat pipe (100) that extends in the first semiconductor layer (200B), the second semiconductor layer (200C), and the heat sink (300) in the first direction (Z).

A system and a method are disclosed for coordinating for a coordinated beamforming, Co-BF, in an overlapping basic service set, BSS. The method includes detecting, with at least one of a first access point, AP, an overlapping BSS between a first AP (AP1) and a second AP (AP2) and transmitting, with the first AP (AP1), an indication of whether the first AP (AP1) received a cross-BSS channel state indicator, CSI, report (214c). The method also includes coordinating with the second AP (AP2) by the first AP (AP1), to perform a Co-BF based on the cross-BSS CSI report (214c).

An example capacitor structure includes a lower electrode structure (70), a dielectric pattern (95) and an upper electrode (105). The lower electrode structure (70) includes a first lower electrode (65) on a substrate (10), and a second lower electrode (62) on a sidewall of the first lower electrode (65). The second lower electrode (62) includes an alloy of a first metal and a second metal. The dielectric pattern (95) is disposed on a surface of the lower electrode structure (70). The upper electrode (105) is disposed on a surface of the dielectric pattern (95). The second lower electrode (62) has a thickness varying in a vertical direction perpendicular to an upper surface of the substrate (10). A weight ratio between the first metal and the second metal is uniform in the vertical direction in the second lower electrode (62).

Provided are non-volatile memory devices, storage devices, and methods of operating the storage devices. The non-volatile memory device includes a memory interface circuit including a data pin configured to output a data signal, a command address pin separated from the data pin and configured to receive a first data output packet, and a first pin configured to receive a toggle signal corresponding to the first data output packet, a first page buffer configured to output first data in response to the first data output packet, and a first register configured to provide the first data to the memory interface circuit through a first path based on receiving a first clock signal generated based on the toggle signal, and provide the first data to the memory interface circuit through a second path different from the first path in response to receiving a second clock signal different from the first clock signal.

A storage device includes a nonvolatile memory device including an input/output register, the nonvolatile memory device sensing data from a memory region corresponding to an address and transmitting the data that is sensed from the memory region, and a storage controller that transmits a command and the address to the nonvolatile memory device via a first bus and that transmits and receives data to and from the nonvolatile memory device via a second bus. The nonvolatile memory device, in response to a first command that is received from the storage controller, outputs a sensing status of first data and stores the first data in the input/output register.

An integrated circuit is provided. The integrated circuit includes: a voltage-dividing circuit including a plurality of resistors connected to each other in series, wherein the voltage-dividing circuit is configured to generate, based on a test signal, an internal test signal, at least one first reference signal, and at least one second reference signal; a first low-pass filter configured to receive the at least one first reference signal and generate a first reference voltage; a second low-pass filter configured to receive the at least one second reference signal and generate a second reference voltage; a first comparator configured to compare the first reference voltage to the internal test signal; and a second comparator configured to compare the second reference voltage to the internal test signal.

A semiconductor device comprising: a substrate (110) includes a first surface (110a) and a second surface (110b) opposing each other; an epitaxial layer (131) positioned on the first surface (110a) of the substrate (110), including a gate trench (160), and the epitaxial layer (131) having a first conductivity type; a channel layer (300) positioned on the inner sidewall (160_s) of the gate trench (160) and having the first conductivity type; a gate electrode (150) positioned on the inner side surface of the channel layer (300); a gate insulating layer (140) positioned on the bottom surface of the gate trench (160), and between the channel layer (300) and the gate electrode (150); a source electrode (173) positioned on the epitaxial layer (131); and a drain electrode (175) positioned on the second surface (110b) of the substrate (110).

Methods, devices, and systems for training a deep learning recommendation model (DLRM), include: offloading (S101) one or more storage tables to a memory device; training (S102) a DLRM based on training data, wherein during the training, a storage table prefetched from the memory device is loaded according to a training phase; and storing (S103) feature data obtained during the training into the loaded storage table.

Provided is an operation method of user equipment in communication with a satellite in a non-terrestrial network, the operation method including receiving a synchronization signal block (SSB) burst through wide beams from the satellite, performing, based on the SSB burst, an indexing operation on narrow beams corresponding to the wide beams, estimating an optimal narrow beam, based on the indexed narrow beams, and performing random access to the satellite, based on the estimated narrow beam.

Systems, methods, and apparatuses are disclosed for reducing cell search time. In one or more examples, the systems, devices, and methods include discarding (905) a first candidate of a first set of candidates of carrier frequencies based the first candidate failing to satisfy a power ratio threshold; storing (910) a second candidate based on the second candidate satisfying the power ratio threshold; generating (915), at the UE, an increased power ratio threshold based on the respective power ratios of the two or more accumulations of the second candidate satisfying the minimum power ratio threshold, the increased power ratio threshold being greater than the power ratio threshold; identifying (920), based on the UE storing one or more candidates, a second set of candidates that is a subset of the first set of candidates, the second set of candidates including the second candidate; and establishing (925) a connection to a cell based on the second candidate.

A memory device includes a first semiconductor layer including a first cell region and a second cell region over the first cell region, and a second semiconductor layer under the first semiconductor layer in a substantially vertical direction and including a page buffer circuit which includes a first page buffer set associated with odd data and a second page buffer set associated with even data, the first cell region includes first memory cells, a first odd bit line transmitting odd data of the first memory cells, and a first even bit line transmitting even data of the first memory cells, the second cell region includes second memory cells, a second odd bit line transmitting odd data of the second memory cells, and a second even bit line transmitting even data of the second memory cells.

A memory device includes: a cell semiconductor layer respectively including sub-cell regions arranged in a first direction, and contact regions between the sub-cell regions, wherein the sub-cell regions include memory cells; and a circuit semiconductor layer on the cell semiconductor layer and including a circuit configured to control the memory cells. The cell semiconductor layer includes: sub-wordlines extending in the first direction from the sub-cell regions to adjacent contact regions; odd wordline interconnection lines extending from an odd sub-cell region to adjacent contact regions; and even wordline interconnection lines extending from an even sub-cell region to the adjacent contact regions.

A random number generation device includes an instantiate and reseed function logic configured to receive an entropy input having a size smaller than or equal to a reference size of a reference seed material that may be processed at one time during a crypto operation and configured to repeatedly perform the crypto operation, based on a seed material configured to be processed at one time during the crypto operation in a current crypto operation sequence and an operation result in a previous crypto operation sequence, and a random number generation logic configured to generate random number data.

A storage device includes a memory device including command and address pins, data pins, first control signal pin, memory blocks, and a transceiver transmitting or receiving data through the data pins and a memory controller transmitting a command and an address to the memory device through the command and address pins, transmitting and receiving data to and from the memory device through the data pins, and transmitting a first control signal to the memory device through the first control signal pin. The memory device transmits, in response to receiving a select chip enable packet received through the command and address pins, a second control signal in an activated state to at least one driving circuit that, in response to receiving the second control signal in an activated state, drives the transceiver transmitting and receiving data. The memory device then transmits or receives first data based on the select chip enable packet and the first control signal through the data pins.

An encryption device includes a controller configured to output random data including K random bits, where K is an integer greater than or equal to 2, and a random shuffling circuit configured to receive N input bits and perform a random shuffling operation on the N input bits, where N=3×2^b, and b is a non-negative integer, based on a plurality of layers each including the random data and an even number of multiplexers, to output final shuffling data having a uniform distribution, wherein a total number of multiplexers included in the random shuffling circuit is 2×K, each of the K random bits is input to two multiplexers included in one layer, and a number of layers is a smallest integer from among integers greater than or equal to K divided by a largest integer from among integers less than or equal to N/2.

A semiconductor device includes a substrate, a first conductivity type semiconductor layer on a first surface of the substrate and penetrated by a first trench and a second trench, a gate electrode in the first trench and including a first side surface and a second side surface opposing each other, a first gate insulating layer on the first side surface and a lower surface of the gate electrode, a second conductivity type doping layer on the first conductivity type semiconductor layer and covering a portion of a side surface of the first gate insulating layer, a first conductivity type doped region on the second conductivity type doping layer and covering another portion of the side surface of the first gate insulating layer, a source electrode on the first conductivity type doped region, a drain electrode on a second surface of the substrate and a shielding pattern around the second trench.

A nonvolatile memory device includes a memory cell array including a plurality of planes, a page buffer circuit connected to the memory cell array through a plurality of bit lines, an input/output circuit connected to the page buffer circuit through a plurality of data lines, a control logic circuit controlling an operation for the planes in response to a command, a first command-address pad set electrically connected to the control logic circuit and receiving a first command, and a second command-address pad set electrically connected to the control logic circuit and receiving a second command. A time during which the first command is received overlaps with a time during which the second command is received.

A memory cell array may include a first memory cell including a first transistor structure and a first capacitor structure, a second memory cell including a second transistor structure and a second capacitor structure, and a first wordline contact connected to the first transistor structure and the second transistor structure, wherein the first capacitor structure is spaced apart from the first transistor structure in a first direction, and the second capacitor structure is spaced apart from the second transistor structure in a second direction different from the first direction.