STMicroelectronics International Patente

A method of operating a foldable touchscreen device (100) includes detecting self-capacitances (124) sensed in a folding area (108) of a touchscreen (102) using a self-sensing scan by a touchscreen controller (110), determining a reference strength sensed by the touchscreen (102) in the folding area (108) based on the self-capacitances (124) in the folding area (108) when the device (100) is in a partially folded position, determining temperature information of the touchscreen (102) in the partially folded position, in response to determining that the temperature information of the touchscreen (102) is outside a predetermined temperature window, determining a corrected reference strength from the reference strength based on the temperature information, determining an angle strength for the partially folded position based on the corrected reference strength, and determining whether the device (100) is open or closed based on the angle strength.

An integrated photonics device (100), such as a thermal phase shifter, for instance, comprises: a substrate of integrated photonics material having an optical waveguide (110) extending therealong as well as first (112a) and second (112b) lateral strips extending sidewise of the optical waveguide (110) and thermally coupled therewith; first (115a) and second (115b) heat transfer formations, such as arrays of copper pillars, configured to transfer heat from a proximal end distanced away from the first lateral strip (112a) and the second lateral strip (112b) in the substrate of integrated photonics material towards a distal end thermally coupled to the first lateral strip (112a) and the second lateral strip (112b) in the substrate of integrated photonics material; and first (130a) and second (130b) electric heaters thermally coupled with the proximal ends of the first (115a) and second (115b) heat transfer formations. Heat generated by the first (130a) and second (130b) electric heaters is transferred to the optical waveguide (110) via the first (115a) and second (115b) heat transfer formations and the first (112a) and second (112b) lateral strips in the substrate of integrated photonics material.

A deployment circuit (105) for controlling the deployment of a pyrotechnic device (30) is disclosed. The deployment circuit (105) comprises a deployment driver circuit (20) configured to energize the pyrotechnic device (30) by connecting (20a, 20b) respective terminals (PR, PF) to a supply voltage (V_SUP), diagnostic circuitry (160) configured to perform diagnostic controls on the deployment circuit (105), a communication interface (SCLK, SDI, SDO, NCS) configured to be connected to a microcontroller (11), a terminal configured to be connected to the microcontroller (11) in order to provide a fault signal (FAULT) to the microcontroller (11) and a control circuit (110).Specifically, the control circuit (110) comprises a hardware Finite-State Machine configured to execute one or more diagnostic routines (300, 350, 360, 370), wherein each diagnostic routine (300, 350, 360, 370) comprises a sequence of diagnostic operations (301-307; 351-356; 363-364; 374-375). In each diagnostic operation, the control circuit (110) is configured to generate control signals for the diagnostic circuitry (160) in order to execute a respective diagnostic operation of the deployment circuit (105), monitor one or more signals (CS, DS) provided by the diagnostic circuitry (160), and determine whether the one or more signals (CS, DS) indicate one or more faults of the deployment circuit (105). In response to determining that the one or more signals (CS, DS) indicate one or more faults of the deployment circuit (105), the control circuit (110) asserts the fault signal (FAULT) and stores a fault code (ZF) indicative of the fault detected. Moreover, the control circuit (110) is configured to receive via the communication interface (SCLK, SDI, SDO, NCS) a request and, in response to the request, transmit the stored fault code (ZF).

A deployment circuit (20) for a pyrotechnic device (101) is disclosed. The deployment circuit (20) comprises a first terminal (122a) and a second terminal (122b) configured to be connected to the pyrotechnic device (101). A driver circuit (200) comprises at least one electronic switch (2002a) configured to selectively connect the first terminal (122a) and the second terminal (122b) to a supply voltage (V_IN) in response to determining that a deployment control signal (DEP_CMD) is asserted. A current limiter (2000a) limits the current (I_PYRO) provided via the first terminal (122a) and the second terminal (122b) to a maximum value (IMAX). A control circuit (202) drives the driver circuit (200) as a function of a fire request signal (REQ).Specifically, when the fire request signal (REQ) is de-asserted, the control circuit determines (1004) whether a first value (MR) indicative of a resistance (R_PYRO) between the first terminal (122a) and the second terminal (122b) is between a first threshold and a second threshold. In response to determining that the first value (MR) is not between the first threshold and the second threshold, the control circuit signal (1016) an error.Conversely, when the fire request signal (REQ) is asserted, the control circuit starts (1006) a deployment cycle by asserting the deployment control signal (DEP_CMD), and stops (1010) the deployment cycle after a given time-period (t_DC) by de-asserting the deployment control signal (DEP_CMD). The control circuit monitors (1008) during the deployment cycle a value (CNT) indicative of the time (t_DEPLOY) where the current (I_PYRO) provided via the first terminal (122a) and the second terminal (122b) is greater than a current threshold (I_TH). Moreover, once the deployment cycle has been stopped, the control circuit obtains (1012) a second value (MR) indicative of the resistance (R_PYRO) between the first terminal (122a) and the second terminal (122b), and determines (1014) whether the monitored value (CNT) indicates that the time (t_DEPLOY) is greater than a time threshold (t_TH) and whether the second value (MR) is greater than a third threshold. Specifically, when both conditions are satisfied, the control circuit signals (1020) a correct deployment of the pyrotechnic device (101).

La présente description concerne un dispositif d'amplification à gain variable (1) et un procédé d'amplification à gain variable, dans lesquels une segmentation d'une commutation en courant (102) est mise en œuvre en au moins deux parties (1021, 1022).

Method for managing an embedded Universal Integrated Circuit Card, eUICC, for Internet of Things, IoT, devices configured to have associated therewith:- a fallback remote manager module, in particular a fallback eSIM IoT remote Manager eIM, which upon association (300) with the eUICC for IoT devices is configured to have its operation disabled; and- at least one further remote manager module, in particular at least one further eSIM IoT remote Manager eIM;said method comprising, at the eUICC for IoT devices:- checking (304) whether the at least one further remote manager module, which is associated with said eUICC for IoT devices, is reachable; and- in response to said operation of checking (304) indicating (306) an absence (N) of reachable further remote manager modules associated with said eUICC for IoT devices, enabling (308) said fallback remote manager module to operate on the eUICC for IoT devices.

Method for manufacturing a semiconductor die (1), comprising the steps of: arranging a semiconductor body (2) having a front side (2a) and a back side (2b) opposite to each other; concurrently forming, through part of the semiconductor body (2), a first trench (6) and a second trench (8), having respective side walls (6a, 8a) and bottom wall (6b, 8b); forming, at the side walls (6a) and the bottom wall (6b) of the first trench (6), a first insulation layer (12) having a first thickness (t1); forming, at the side walls (8a) and the bottom wall (8b) of the second trench (8), a second insulation layer (26) having a respective second thickness (t4) lower than the first thickness (t1); and filling the first and the second trenches (6, 8) with a conductive material layer (32).

La présente description concerne un boitier (100) de puce électronique comprenant : - au moins une première borne (103) adaptée à recevoir et/ou à fournir un potentiel d'alimentation ; - au moins une deuxième borne (102) adaptée à recevoir et/ou à fournir un potentiel de référence ; et - au moins une troisième borne (104) adaptée à recevoir et/ou à fournir un signal de données, dans lequel ladite au moins une troisième borne est disposée en périphérie, et ladite au moins une première borne est disposée plus au centre que ladite au moins une troisième borne.

A method is provided for filling a high aspect ratio trench extending into the upper surface of a semiconductor substrate (114), comprising :- a first filling phase which forms a conformal layer (134) ,-an etch back to recess the portion of the conformal layer (134) extending over the upper surface of the semiconductor substrate (114) and form a funnel-shaped opening at the top of the trench,-a second filling phase which forms a filling layer that fills the remainder of the trench including the funnel-shaped opening and extends over the upper surface of the semiconductor substrate,- a further etch back to recess the portion of the filling layer extending over the upper surface of the semiconductor substrate (114).

A method of performing write operations in a Phase Change Memory, PCM, device, the PCM device comprising a current pulse source configured to generate a highest level of source current and to produce current pulses out of set current pulses (PS<a>; PS<b>) and reset current pulses (PR<a>; PR<b>), and a plurality of cells arranged in a plurality of groups (100<a>; 100<b>), wherein groups in the plurality of groups (100<a>; 100<b>) comprise respective sets of cells configured to be written via respective write operations. The method comprises performing the write operations via set current pulses (PS<a>; PS<b>) for each set of cells comprising at least one cell to be written via a set write operation, and via reset current pulses (PR<a>; PR<b>) for each set of cells comprising at least one cell to be written via a reset write operation. The set current pulses (PS<a>; PS<b>) provided to cells comprised in one group of the plurality of groups (100<a>; 100<b>) are time-shifted with respect to set current pulses (PS<a>; PS<b>) provided to cells comprised in the other groups, and the reset current pulses (PR<a>; PR<b>) provided to cells comprised in one group of the plurality of groups (100<a>; 100<b>) are dis-overlapped with respect to reset current pulses (PR<a>; PR<b>) provided to cells comprised in the other groups. A sum of the set current pulses (PS<a>; PS<b>) and the reset current pulses (PR<a>; PR<b>) provided to cells comprised in the plurality of groups (100<a>; 100<b>) at a common write time is equal to or lower than the highest level of source current of the current pulse source.

A fault detection circuit (10) for checking configuration registers (REG₁...REG_N) of a processing unit, performing a configuration register test on a given set of registers (REG₁...REG_N) of said processing unit, reading settings of the configuration registers (REG₁...REG_N) and comparing them with expected settings,wherein said fault detection circuit (10) comprisesa set of parity calculator units (PAR_CALC₁...PAR_CALC_N), each parity calculator unit (PAR_CALC_X) configured to receive from at least a configuration register (REG_X) in said given set of registers (REG₁...REG_N) at least a subset of bits (SB_X) of a set of bits stored in said at least configuration register (REG_X) and configured to calculate a parity code (P_X) of said subset of bits (SB_X) which binary value indicates a parity of said subset of bits (SB_X),a set of capture units (CAPT₁...CAPT_N) each configured to receive a parity code (P_X) output from a respective parity calculator unit (PAR_CALC_X) in said set of parity calculator units (PAR_CALC₁...PAR_CALC_N) and to hold it on its output as captured parity code (PC_X) under the control of a capture control signal (TRIG_CAPT).a controller module (RCC) configured to, for each parity calculation unit (PAR_CALC_X) and respective capture unit (CAPT_X),issue a parity calculation control signal (TRIG_CALC) enabling the calculation of the parity code (P_X) by the corresponding parity calculation unit (PAR_CALC_X) at a given time,issue said capture control signal (TRIG_CAPT) to enable holding of the parity code value (P_X) as captured parity code (PC_X) ,receive said captured parity code (PC_X) and compare it with a captured parity code (PC_X) received at a previous time andsignal (ERR) a fault if the comparison indicates a change in the value of the captured parity code (PC_X), storing an index (X) identifying the register (REG_X) which comparison indicates a change in the value of the captured parity code (PC_X).

A circuit (35) for detecting electrical short circuits in a full-bridge class-D amplifier that comprises: a first branch (HP, LP) comprising a first high-side switch (HP) and a first low-side switch (LP); and a second branch (HM, LM) comprising a second high-side switch (HM) and a second low-side switch (LM). The circuit (35) comprising: a measuring unit configured to provide a first measure of a first operating characteristic of the high-side switch (HP; HM) comprised in one of the first branch (HP, LP) and the second branch (HM, LM) of the full-bridge class-D amplifier, and a second measure of a second operating characteristic of the low-side switch (LM; LP) comprised in the other of the first branch (HP, LP) and the second branch (HM, LM) of the full-bridge class-D amplifier; a checking unit configured to receive from the measuring unit the first measure and the second measure and to provide an unbalance signal indicative of the presence of unbalance between said first measure and said second measure; and a detection unit configured to receive from the checking unit said unbalance signal and to detect the presence of an electrical short circuit in response to said unbalance signal indicating the presence of unbalance between said first measure and said second measure.

The present disclosure relates to a reflection-type phase shifter device (700), RTPS, comprising at least two reflective loads (102, 104) whose values can be set independently of one another.

La présente description concerne un circuit électrique de puissance (100), comprenant au moins : - plusieurs sources d'alimentation électrique (102, 103) ; - un bus d'interconnexion électrique (104) couplé aux sources d'alimentation électrique (102, 103) ; - des dispositifs de commutation (114 - 120) comprenant chacun au moins un thyristor (124, 128, 132, 136) et un transistor à effet de champ (122, 126, 130, 134) couplés en parallèle l'un à l'autre, et configurés pour coupler les sources d'alimentation électrique (102, 103) en série ou en parallèle.

Un capteur d'images est constitué de pixels rétroéclairés (110) formés dans et sur un substrat semiconducteur (101). Un rayonnement dans le domaine infrarouge proche atteint le photodétecteur rétroéclairé (112) des pixels via une surface éclairée supérieure (102) du photodétecteur. Une structure hybride combinant réseau de diffraction (114) au niveau de cette surface supérieure et filtre interférométrique à couches non-régulières (115) déposé sur le réseau de diffraction permet de piéger les photons dans le silicium du photodétecteur. Le rayonnement est diffracté dans le photodétecteur avec un angle suffisant pour qu'après réflexion sur des tranchées (113) isolant les photodétecteurs adjacents et sur la couche métallique (111) déposée sur la surface opposée du photodétecteur rétroéclairé, il soit réfléchi par le filtre interférométrique. Les photons sont piégés dans le substrat ; leur absorption et donc le rendement quantique du pixel rétroéclairé sont améliorés.

A phase frequency detector circuit, a method for generating a first output signal and a second output signal based on a reference signal and a feedback signal, and a phase-locked loop are provided. The phase frequency detector circuit includes a plurality of reference signals, a plurality of feedback signals, a first output signal, and a second output signal. The plurality of reference signals, including a primary reference signal having a reference triggering edge. The plurality of feedback signals, including a primary feedback signal having a feedback triggering edge. The first output signal and the second output signal indicating a phase difference between the primary reference signal and the primary feedback signal. The first output signal remains asserted after the primary feedback signal arrives, when the phase difference exceeds a max phase difference indicated by a difference between the primary reference signal and the reference signal.

Embodiments of the present disclosure provide techniques for optimizing quiescent current in an amplifier. The amplifier (100) may include an output stage (132, 134) associated with a quiescent current (140, Iqs); a set of NMOS transistors comprising a first NMOS transistor (118) and a second NMOS transistor (116) connected together. The first NMOS transistor (118) may have a first bias current (125). The amplifier (100) may further include a first set of PMOS transistors comprising a first PMOS transistor (122) and a second PMOS transistor (120). The first PMOS transistor (122) may have a second bias current (123). The amplifier may further include an optimization circuit (111). The optimization circuit may include a current steering circuit (130) that is driven by a threshold current (129). The optimization circuit may further include a level shifting device (124) connected to the current steering circuit (130). The current steering circuit may be configured to adjust the first bias current (125) based on the threshold current (129).

According to an embodiment, a glitch rejection circuit includes a first stage averaging circuit with programmable length, a second stage averaging circuit, and a hysteresis comparator. The first stage implements a recursive moving sum average using a FIFO buffer to process a binary input signal. The second stage provides moving average filtering. The hysteresis comparator uses programmable thresholds set based on peak signal values to generate a clean output signal. The circuit removes glitches from frequency-shift keying (FSK) demodulator input signals while maintaining signal integrity at high bitrates. The programmable parameters allow optimization based on expected glitch characteristics and system requirements.

A floating reference generation circuit for a SMPS includes core biasing, driver logic, and transient biasing blocks. The core biasing block generates temperature and process-tracking reference voltages. The driver logic block uses these references to generate a floating reference voltage through level-shifting and output circuits, with compensation capacitors improving settling time and stability. The transient biasing block employs a diode-transistor cascade and feedback loops to control transitions between voltage levels while maintaining voltage stress limits. The circuit can be configured as either a floating ground generator or floating supply generator through polarity adaptation of the components. Coordination between floating ground and supply reference signals enables precise timing control of voltage transitions. The open-loop architecture enables stable high-speed operation across varying load and line conditions, while eliminating separate reference generation circuits. Implementation provides improved efficiency and noise isolation for analog components while reducing settling time and maintaining high-voltage tolerance.

According to an embodiment, a system can dynamically control integration time in a time-of-flight (ToF) device based on current operating conditions. A signal scaler processes calibration data and real-time measurements to determine expected signal and ambient rates. Parallel calculations determine required integration times-one based on achieving maximum ranging distance and another based on measurement precision requirements. The system selects the longer integration time and applies user-defined bounds to optimize power consumption while maintaining specified performance. By adapting integration time to ambient light conditions and target reflectance characteristics, the system enables shorter integration times in favorable conditions while automatically increasing duration when needed for distant or low-reflectance targets.

In accordance with various embodiments of the present disclosure, a method for outputting data from an inertial measurement unit having a first accelerometer having a first operating range and a second accelerometer having a second operating range comprises comparing an absolute value of data from the first accelerometer and/or from the second accelerometer for each of three axes to a first threshold and a second threshold; if the absolute value of the data from the first accelerometer and/or from the second accelerometer is less than the first threshold for all of the three axes, writing the data from the first accelerometer to a data buffer; and if the absolute value of the data from the first accelerometer and/or from the second accelerometer is greater than the second threshold for any of the three axes, writing the data from the second accelerometer to the data buffer.

La présente description concerne un procédé de configuration d'un microcontrôleur (100), comprenant l'autorisation de modifier un registre contenant des octets d'options (User_OB1) de configuration du microcontrôleur si un premier étage de programme de démarrage (ROT) du microcontrôleur (100), sécurisé par le fabricant du microcontrôleur, est exécuté ; et si un niveau d'autorisation d'accès de programme du microcontrôleur correspond à un état de fabrication du microcontrôleur (HDPL0) ou un état où seul un premier étage de programme de démarrage du microcontrôleur (HDPL1) est autorisé.

A circuit configured to supply a load at an output node (vout) comprises driver circuitry including voltage boost capacitive circuitry (C<1A>, C<1B>, C<2A>, C<2B>) configured to apply to the control terminals (B<1>, C<1>, B<2>, C<2>) of one or more driver transistors (M<DPV_1A>, M<CASC_2A>, M<DRV_1B>, M<CASC_2B>) a voltage-pumped (100B, vbl_boost_var) replica of the comparison signal (COMP_OUT) between a reference voltage and a voltage that is a function of the output voltage (vout). Voltage refresh transistor circuitry (M<1A>, M<2A>, M<1B>, M<2B>) coupled to the voltage boost capacitive circuitry (C<1A>, C<1B>, C<2A>, C<2B>) is configured to transfer thereon the voltage-pumped (100B, vbl_boost_var) replica of the comparison signal (COMP_OUT). The driver circuitry is controllably (PA_LV, PB_LV) switchable between a first mode of operation during which the current flow path therethrough is conductive or non-conductive in response to the voltage-pumped (100B, vbl_boost_var) replica of the comparison signal (COMP_OUT) while the voltage refresh transistor circuitry (M<1A>, M<2A>, M<1B>, M<2B>) is de-activated, and a second mode of operation during which the voltage refresh transistor circuitry (M<1A>, M<2A>, M<1B>, M<2B>) is activated and the current flow path through the driver circuitry (M<DRV_1A>, M<CASC_2A>, M<DRV_1B>, M<CASC_2B>) is non-conductive. The circuit comprises variable boosted voltage generation circuitry (1000, 200, 202, 204) sensitive to a supply voltage at a supply node and configured to produce a variable boosted voltage (vbl_boost_var) wherein the variable boosted voltage generation circuitry (200, 202) is configured to increase the variable boosted voltage (vbl_boost_var) in response to a decrease of the supply voltage at the supply node

La présente description concerne un dispositif électronique (14) comprenant une première source (22) d'un courant aléatoire (IA) reliée entre l'alimentation (16) et la masse (18) du dispositif.

La présente description concerne un dispositif électronique (14) comprenant un premier circuit de protection contre des attaques, le premier circuit comprenant une mémoire (18) configurée pour contenir un premier paramètre configurable (PPA) correspondant à la perte de performance acceptable, le premier circuit comprenant au moins deux modules distincts de perturbation (22) du courant de masse, le premier circuit étant configuré pour, lorsque la protection est activée :- générer des phases de fonctionnement ;- durant chaque phase, multiplier la fréquence d'un signal d'horloge (CLK) par un premier pourcentage (CLK_PERF) ; et- durant chaque phase, mettre en œuvre au moins une partie des modules de perturbation,le premier pourcentage (CLK_PERF) et les paramètres des modules de perturbation étant déterminés au début de la phase de telle manière que la perte de performance acceptable (PPA) n'est pas dépassée.

An example near-field communication (NFC) tag device, NFC card emulation device, and a method for initializing an NFC application protocol at an NFC communication listener are provided. The example NFC tag device includes one or more applications and an NFC transceiver. The one or more applications, each include a unique application identifier. The NFC transceiver is configured to receive an application identifier polling command from an NFC reader, wherein the application identifier polling command comprises a first application identifier and transmit a second application identifier corresponding to a supported application of the one or more applications.

A phase change memory (PCM) cell includes a phase change material region and a heater element coupled to phase change material region. The heater element is made of an electrically conductive material having an activated resistance in temperature property. The electrically conductive material of the heater element is an alloy having a silicon content in a range of 14-19%. The alloy for the conductive material of the heater element is deposited by an atomic layer deposition process in a conformal layer having a substantially constant thickness.

Electronic device (10), comprising: a semiconductor body (12); trenches (13) in the semiconductor body (12) from the first side (12a) towards the second side (12b), terminating in the semiconductor body (12) and arranged at the side of each other along a second axis (X) orthogonal to the first axis (Z); a respective insulating field plate region (14) with a main body (14a) in each of said trenches (13), covering the lower and lateral walls of the respective trench (13); a respective field plate region (16) in each of said trenches (13), each field plate region (16) being buried in the insulating field plate region (14) and being electrically insulated from the semiconductor body (12) by means of the insulating field plate region (14); and a respective first conductive gate region (15a) for each of said trenches (13), each first conductive gate region (15a) extending in the semiconductor body (12) from the first side (12a) towards the second side (12b) and terminating in the semiconductor body (12), extending laterally to the main body (14a) of the respective insulating field plate region (14) along the second axis (X), being of conductive material and being electrically insulated from the semiconductor body (12) and the respective field plate region (16).

A voltage reference circuit (10; 20; 30; 50; 60) for supplying a reference voltage (V<Zener_comp>; V<zener_diff>, VREFH, VREFL) comprising a Zener circuitry (13, 14) configured to generate a Zener voltage (V<Zener>) and a temperature compensation circuit arrangement (11; 51) configured comprising a generator (15) generating a temperature depending current (I<PTAT>), in particular a PTAT current, and supplying at its output (11a, 11b) a current proportional or equal to said temperature depending current (I<PTAT>) to a Zener voltage compensation circuit (12; 22; 32; 42; 62) comprising a compensation resistor (R<x>), receiving current proportional or equal to said temperature depending current (I<PTAT>), on which a compensation voltage (ΔV<X>) is formed, said voltage reference circuit (10; 20; 30; 50; 60) being configured to supply an output voltage (V<Zener_comp>; V<diff>, VREFH, VREFL) which depends on said Zener voltage (V<Zener>) and said temperature compensation voltage (ΔV<X>), wherein said voltage reference circuit (10; 20; 30; 50; 60) is configured to supply said output voltage (V<zener_diff>, VREFH, VREFL) as differential voltage between a first voltage (VREFH) and a second voltage (VREFL), at least one of said first voltage (VREFH) and second voltage (VREFL) being taken from said Zener voltage compensation circuit (32; 42; 62).

A method, comprising: providing a set of measured characteristic curves values (MS) of an electronic device having a control node and a current flow path therethrough between a first current node and a second current node, the measured characteristic curves values (MS) comprising measured electric current values through the current flow path as a function of electric voltage values across first and second current nodes with a set of control voltage levels applied at said control node of the semiconductor device (10); applying an artificial neural network, ANN processing pipeline (30) to the set of measured characteristic curves values (MS), obtaining a set of reconstructed physical parameter values of the semiconductor device (10) as a result. The ANN processing pipeline (30) comprises a plurality of ANN processing stages (340, 342, 343, 344, 346, 347, 348) each having at least one respective set of ANN processing weights (W1, W2, W3, W4, W5, W6; WG). The method further comprises: computing reconstructed characteristic curves values of the semiconductor device (10) based on the set of reconstructed physical parameter values and a set of device modeling equations; performing a comparison (36) of reconstructed characteristic curves values and measured characteristic curves values (MS), and based on the performed comparison, providing an indicator (D) of a variation of physical values of the semiconductor device (10).

Computational weight data for an in-memory computation operation is stored in a column of memory cells (14). The in-memory computation operation is executed by actuating word lines (WL) connected to the column of memory cells (14) in response to feature data of the in-memory computation operation. An analog signal generated on a bit line of the column is converted, during a converter computation cycle, a digital signal. That digital signal is processed to generate an output of the in-memory computation operation. A randomization signal is generated and applied to control application of a randomized variation to the converter computation cycle. The processing of the digital signal includes adjusting the digital signal to remove error introduced by the random variation applied to the converter computation cycle. The applied random variation affects the power waveform of the in-memory computation device making it more difficult for a power-based side channel attack to succeed.

MEMS pressure transducer (100) including: a semiconductor body (2); a fixed electrode region (12); and a membrane (155), which is suspended above the fixed electrode region (12) so as to delimit a cavity (39), the membrane (155) being deformable as a function of pressure. The membrane (155) includes: a lower conductive region (36) of polysilicon, which delimits the cavity (39) at the top and is traversed by one or more holes (38) which face the cavity (39), the lower conductive region (36) being impermeable to gases, except for the holes (38); an intermediate structure (146;246) of polysilicon permeable to gases, which closes the holes (38); and an upper conductive region (156) of polysilicon or amorphous silicon, which extends on the intermediate structure (146;246) and the lower conductive region (36) and is impermeable to gases. The membrane (155) is laterally delimited by a lateral surface (S<lat>), which is formed by the lower conductive region (36) and the upper conductive region (156); the intermediate structure (146;246) does not face the lateral surface (S<lat>) of the membrane (155).

L'invention concerne une structure multicouches pour dispositif photonique, comprenant, sur un substrat support (10), un empilement de couches (20) comprenant : une couche sous-jacente (21) en oxyde de magnésium, une couche active (22) en sulfure d'antimoine, disposée sur la couche sous-jacente (21) et en contact direct avec elle, une couche sus-jacente (23) en oxyde de magnésium, disposée sur la couche active (22) et en contact direct avec elle, et une couche de recouvrement (24) disposée au-dessus de la couche sus-jacente (23).

La présente description concerne un dispositif électronique (30) comprenant : une porte logique (31) relié à un premier noeud (18) d'application d'une tension de référence ; un générateur de tension aléatoire (100), configuré pour générer une tension aléatoire (VRAND) sur un deuxième noeud (34) ; une première diode (32), la cathode de la première diode (32) étant reliée au premier noeud (18) et l'anode de la première diode (32) étant reliée au deuxième noeud (34).

A digital communication system (1) comprises a master device (2) and a plurality of slave devices (4). The master and slave devices are, in operation, communicatively coupled over a communication bus (5) and also coupled together in a daisy-chain configuration using a separate line. A daisy-chain input (DC_IN) of a subsequent device is coupled to a daisy-chain output (DC_OUT) of a previous device in the daisy-chain configuration. Any slave device (4) propagates an interrupt value at their daisy-chain input to their daisy-chain output. In a case of a local interrupt event (99), a slave device (4) changes its daisy-chain output from an operating value to the interrupt value. The master device, responsive to detecting a change of its daisy-chain input (FB_IN) into the interrupt value, triggers a sequential polling of all the slave devices, from the last one to the first one, for feedback collection using the communication bus.

La présente description concerne un microcontrôleur (200) comprenant une mémoire (152) ; un bloc de calcul de code de correction d'erreur (142) de cette mémoire ; un premier registre (SBS_CFGR2) ; et un premier bit (202) qui, lorsqu'il a une première valeur et que le premier registre (SBS_CFGR2) comprend une deuxième valeur (ECCL=1), entraîne l'interdiction de la modification du contenu du premier registre (SBS_CFGR2) jusqu'à ce qu'une séquence donnée soit écrite dans un deuxième registre (SBS_KEYR) du microcontrôleur (200).

Lors de la conversion à faible gain, on génère une impulsion du signal de commande de mode (DCG) encadrant l'impulsion (TG2) déclenchant le transfert de charges. Ceci permet de n'utiliser que trois rampes (RAMP1, RAMP2, RAMP3).

La présente description concerne une puce électronique comprenant un dispositif de détection de fissures formé dans et sur un substrat ou sur le substrat, le dispositif comportant un chemin conducteur comportant une alternance de bandes conductrices inférieures (201) et supérieures (203),le chemin comprenant, pour chaque bande inférieure : un premier (205A) et un deuxième (205B) vias conducteurs en contact avec la bande inférieure, un troisième (207A) et un quatrième (207B) vias conducteurs en contact avec respectivement une bande et une autre bande supérieure, au moins une première (209A) et une deuxième (209B) pistes conductrices connectant respectivement les premier et troisième vias et les deuxième et quatrième vias,le premier et le deuxième via étant situés à l'aplomb respectivement d'une première et d'une deuxième extrémité de la bande inférieure, le troisième et le quatrième étant situés à l'aplomb respectivement d'une extrémité de la bande et de l'autre bande supérieure.

A processing system (10a) is described. The processing system comprises a non-volatile memory (104a) comprising a first memory slot arranged to store a first master password (MPW0), a second memory slot arranged to store a second master password (MPW1) and a third memory slot arranged to store a security password (SPW0). A password verification circuit (152a) is configured to set an overwrite signal (OW; OWM) to indicate a success verification of the first master password (MPW0) or a success verification of said second master password (MPW1). Specifically, a protection circuit (150a) is configured to manage write access to the third memory slot arranged to store a security password (SPWO). For this purpose, the protection circuit receives a write request (CMD) for writing a new security password to the third memory slot. Moreover, the protection circuit determines whether security access data (SIi, SPW_CTR) indicate that the third memory slot is associated with the first master password (MPW0) or with the second master password (MPW1), and determines whether the overwrite signal (OW; OWM) indicates a success verification of the first master password (MPW0) or the second master password (MPW1). Accordingly, the protection circuit may selectively enable or disable the writing of the new security password to the third memory slot based on whether the security access data (SIi, SPW_CTR) indicate that the third memory slot is associated with the first master password (MPW0) or with the second master password (MPW1), and the value of the overwrite signal (OW; OWM).

La présente description concerne un dispositif électronique comprenant une diode à avalanche à photon unique (22), la diode à avalanche à photon unique (22) comprenant une jonction PN (26-28a), la jonction PN ayant une première dimension (R) inférieure à 1,2 µm, la diode à avalanche à photon unique (22) étant entourée d'un mur isolant (30), la première dimension (R) étant la plus petite dimension de la jonction.