STMicroelectronics International Patente

A voltage reference circuit (10; 20; 30; 50; 60) for supplying a reference voltage (V<Zener_comp>; V<zener_diff>, VREFH, VREFL) comprising a Zener circuitry (13, 14) configured to generate a Zener voltage (V<Zener>) and a temperature compensation circuit arrangement (11; 51) configured comprising a generator (15) generating a temperature depending current (I<PTAT>), in particular a PTAT current, and supplying at its output (11a, 11b) a current proportional or equal to said temperature depending current (I<PTAT>) to a Zener voltage compensation circuit (12; 22; 32; 42; 62) comprising a compensation resistor (R<x>), receiving current proportional or equal to said temperature depending current (I<PTAT>), on which a compensation voltage (ΔV<X>) is formed, said voltage reference circuit (10; 20; 30; 50; 60) being configured to supply an output voltage (V<Zener_comp>; V<diff>, VREFH, VREFL) which depends on said Zener voltage (V<Zener>) and said temperature compensation voltage (ΔV<X>), wherein said voltage reference circuit (10; 20; 30; 50; 60) is configured to supply said output voltage (V<zener_diff>, VREFH, VREFL) as differential voltage between a first voltage (VREFH) and a second voltage (VREFL), at least one of said first voltage (VREFH) and second voltage (VREFL) being taken from said Zener voltage compensation circuit (32; 42; 62).

Electronic device (10), comprising: a semiconductor body (12); trenches (13) in the semiconductor body (12) from the first side (12a) towards the second side (12b), terminating in the semiconductor body (12) and arranged at the side of each other along a second axis (X) orthogonal to the first axis (Z); a respective insulating field plate region (14) with a main body (14a) in each of said trenches (13), covering the lower and lateral walls of the respective trench (13); a respective field plate region (16) in each of said trenches (13), each field plate region (16) being buried in the insulating field plate region (14) and being electrically insulated from the semiconductor body (12) by means of the insulating field plate region (14); and a respective first conductive gate region (15a) for each of said trenches (13), each first conductive gate region (15a) extending in the semiconductor body (12) from the first side (12a) towards the second side (12b) and terminating in the semiconductor body (12), extending laterally to the main body (14a) of the respective insulating field plate region (14) along the second axis (X), being of conductive material and being electrically insulated from the semiconductor body (12) and the respective field plate region (16).

A phase change memory (PCM) cell includes a phase change material region and a heater element coupled to phase change material region. The heater element is made of an electrically conductive material having an activated resistance in temperature property. The electrically conductive material of the heater element is an alloy having a silicon content in a range of 14-19%. The alloy for the conductive material of the heater element is deposited by an atomic layer deposition process in a conformal layer having a substantially constant thickness.

An example near-field communication (NFC) tag device, NFC card emulation device, and a method for initializing an NFC application protocol at an NFC communication listener are provided. The example NFC tag device includes one or more applications and an NFC transceiver. The one or more applications, each include a unique application identifier. The NFC transceiver is configured to receive an application identifier polling command from an NFC reader, wherein the application identifier polling command comprises a first application identifier and transmit a second application identifier corresponding to a supported application of the one or more applications.

Lors de la conversion à faible gain, on génère une impulsion du signal de commande de mode (DCG) encadrant l'impulsion (TG2) déclenchant le transfert de charges. Ceci permet de n'utiliser que trois rampes (RAMP1, RAMP2, RAMP3).

La présente description concerne un microcontrôleur (200) comprenant une mémoire (152) ; un bloc de calcul de code de correction d'erreur (142) de cette mémoire ; un premier registre (SBS_CFGR2) ; et un premier bit (202) qui, lorsqu'il a une première valeur et que le premier registre (SBS_CFGR2) comprend une deuxième valeur (ECCL=1), entraîne l'interdiction de la modification du contenu du premier registre (SBS_CFGR2) jusqu'à ce qu'une séquence donnée soit écrite dans un deuxième registre (SBS_KEYR) du microcontrôleur (200).

A digital communication system (1) comprises a master device (2) and a plurality of slave devices (4). The master and slave devices are, in operation, communicatively coupled over a communication bus (5) and also coupled together in a daisy-chain configuration using a separate line. A daisy-chain input (DC_IN) of a subsequent device is coupled to a daisy-chain output (DC_OUT) of a previous device in the daisy-chain configuration. Any slave device (4) propagates an interrupt value at their daisy-chain input to their daisy-chain output. In a case of a local interrupt event (99), a slave device (4) changes its daisy-chain output from an operating value to the interrupt value. The master device, responsive to detecting a change of its daisy-chain input (FB_IN) into the interrupt value, triggers a sequential polling of all the slave devices, from the last one to the first one, for feedback collection using the communication bus.

La présente description concerne un dispositif électronique (30) comprenant : une porte logique (31) relié à un premier noeud (18) d'application d'une tension de référence ; un générateur de tension aléatoire (100), configuré pour générer une tension aléatoire (VRAND) sur un deuxième noeud (34) ; une première diode (32), la cathode de la première diode (32) étant reliée au premier noeud (18) et l'anode de la première diode (32) étant reliée au deuxième noeud (34).

La présente description concerne une puce électronique comprenant un circuit mémoire comprenant :un empilement d'interconnexion ;plusieurs cellules mémoire, chacune comprenant un élément mémoire (108) au-dessus de l'empilement et un fin-FET comprenant un premier nœud et formé dans le substrat,chaque élément comprend une première électrode, une couche (114) comprenant un matériau OTS, et une deuxième électrode (116) connectée à la couche du côté opposé à la première électrode,dans chaque cellule, le premier nœud du transistor est connecté à l'élément par l'intermédiaire d'un via conducteur (138) traversant toute l'épaisseur de l'empilement,le circuit mémoire comprend un circuit de commande configuré pour appliquer, entre la première et la deuxième électrode de chaque élément, une première ou une deuxième impulsion de tension de respectivement une première ou une deuxième polarité,opposée à la première polarité, pour définir respectivement un premier ou un deuxième état logique de l'élément.

A MUX (72) for a battery management system (10') includes a first input terminal for coupling to a first pin (C<i>) of a battery stack (B), a second input terminal for coupling to a second pin (C<i-1>) of the battery stack (B), and a third input terminal for coupling to a third pin (C<i-2>) of the battery stack (B). A first switch (SW<i>) has a respective first terminal (100<i>) coupled to the first input terminal of the MUX, a second switch (SW<i-1>) has a respective first terminal (100<i-1>) coupled to the second input terminal of the MUX, and a third switch (SW<i-2>) has a respective first terminal (100<i-2>) coupled to the third input terminal of the MUX. An AFE and selection circuit (724) includes a first input terminal coupled to a second terminal (102<i>) of the first switch (SW<i>), a second input terminal coupled to a second terminal (102<i-1>) of the second switch (SW<i-1>), a third input terminal coupled to a second terminal (102<i-2>) of the third switch (SW<i-2>), a first output terminal for coupling to a positive input of a first level shifter circuit (16<i>), a second output terminal for coupling to a negative input of the first level shifter circuit (16<i>), a third output terminal for coupling to a positive input of a second level shifter circuit (16<i-1>), and a fourth output terminal for coupling to a negative input of the second level shifter circuit (16<i-1>). Each of the first, second, third and fourth output terminals of the AFE and selection circuit (724) is selectively couplable to any of the first, second and third input terminals of the AFE and selection circuit (724).

La présente description concerne un dispositif mémoire (300) comportant une pluralité de cellules mémoire organisées en une matrice de lignes mots et de bits, chaque cellule comportant un élément mémoire (M) à changement de phase et deux transistors (T), connectés par leurs premiers noeuds, eux même connectés à une première borne de l'élément, où :les éléments d'une ligne bits sont connectés par leurs deuxièmes bornes ;les deux transistors d'une ligne de mots sont connectés par leurs grilles ;chaque cellule est connectée à deux lignes de sources, respectivement connectées à deux deuxièmes noeuds des transistors, les cellules d'une ligne de mots étant connectées aux deux lignes de sources et les cellules de deux lignes de mots successives étant connectées à une ligne de sources commune ; etchaque transistor est disposé dans et sur une paire de deux ailettes disposées dans un substrat semiconducteur (301).

A processing system (10a) is described. The processing system comprises a non-volatile memory (104a) comprising a first memory slot arranged to store a first master password (MPW0), a second memory slot arranged to store a second master password (MPW1) and a third memory slot arranged to store a security password (SPW0). A password verification circuit (152a) is configured to set an overwrite signal (OW; OWM) to indicate a success verification of the first master password (MPW0) or a success verification of said second master password (MPW1). Specifically, a protection circuit (150a) is configured to manage write access to the third memory slot arranged to store a security password (SPWO). For this purpose, the protection circuit receives a write request (CMD) for writing a new security password to the third memory slot. Moreover, the protection circuit determines whether security access data (SIi, SPW_CTR) indicate that the third memory slot is associated with the first master password (MPW0) or with the second master password (MPW1), and determines whether the overwrite signal (OW; OWM) indicates a success verification of the first master password (MPW0) or the second master password (MPW1). Accordingly, the protection circuit may selectively enable or disable the writing of the new security password to the third memory slot based on whether the security access data (SIi, SPW_CTR) indicate that the third memory slot is associated with the first master password (MPW0) or with the second master password (MPW1), and the value of the overwrite signal (OW; OWM).

La présente description concerne une puce électronique comprenant un dispositif de détection de fissures formé dans et sur un substrat ou sur le substrat, le dispositif comportant un chemin conducteur comportant une alternance de bandes conductrices inférieures (201) et supérieures (203),le chemin comprenant, pour chaque bande inférieure : un premier (205A) et un deuxième (205B) vias conducteurs en contact avec la bande inférieure, un troisième (207A) et un quatrième (207B) vias conducteurs en contact avec respectivement une bande et une autre bande supérieure, au moins une première (209A) et une deuxième (209B) pistes conductrices connectant respectivement les premier et troisième vias et les deuxième et quatrième vias,le premier et le deuxième via étant situés à l'aplomb respectivement d'une première et d'une deuxième extrémité de la bande inférieure, le troisième et le quatrième étant situés à l'aplomb respectivement d'une extrémité de la bande et de l'autre bande supérieure.

La présente description concerne un dispositif électronique comprenant une diode à avalanche à photon unique (22), la diode à avalanche à photon unique (22) comprenant une jonction PN (26-28a), la jonction PN ayant une première dimension (R) inférieure à 1,2 µm, la diode à avalanche à photon unique (22) étant entourée d'un mur isolant (30), la première dimension (R) étant la plus petite dimension de la jonction.

Electronic device (10), comprising: a semiconductor body (12); trenches (13) within the semiconductor body (12) from a first side (12a) towards a second side (12b) of the semiconductor body (12) and terminating within the semiconductor body (12); an insulating field plate region (14) in each of said trenches (13); a conductive gate region (15) in each of said trenches (13) on the respective insulating field plate region (14), each being electrically insulated from the semiconductor body (12) by means of the respective insulating field plate region (14); a field plate region (16) in each of said trenches (13), buried in the respective insulating field plate region (14) and electrically insulated from the respective conductive gate region (15) and from the semiconductor body (12); gate interconnections (28) within the semiconductor body (12), from the first side (12a) towards the second side (12b), lateral to the trenches (13) and terminating in the semiconductor body (12), the gate interconnections (28) being of conductive material, insulated from the semiconductor body (12) and electrically connected to the conductive gate regions (15) in such a way as to electrically interconnect the conductive gate regions (15) with each other.

Selon un aspect, il est proposé un circuit intégré comprenant :- une unité de traitement numérique (MCU),- un circuit émetteur/récepteur (TRC) configuré pour transmettre des données entre l'unité de traitement numérique (MCU) et un bus de données « Controller Area Network », « CAN », le circuit émetteur/récepteur (TRC) étant configuré pour délivrer des signaux différentiels, appelés « CANH » » et « CANL », selon un mode dominant et un mode récessif, chaque transition des signaux différentiels « CANH » et « CANL » entre le mode dominant et le mode récessif étant synchronisée à partir de bits d'adaptation reçus par le circuit émetteur/récepteur,- un circuit d'ajustement (ADPC) d'au moins un bit d'adaptation en fonction d'au moins une comparaison entre le mode commun des signaux différentiels « CANH » et « CANL » et au moins une tension seuil.

A system in package (SiP) includes two or more integrated circuit (IC) packlets performing different functionalities. Each packlet includes a bare functional IC die encapsulated within a first body and including etched individual leads. The packlets are mounted to a leadframe and encapsulated within a second body. A metal heatsink is attached to the leadframe, on a side opposite the two or more IC packlets, using a non-electrically conductive adhesive material.

Electronic device (10), comprising: a semiconductor body (12); trenches (13) in the semiconductor body (12); an insulating field plate region (14) in each trench (13); a conductive gate region (15) in each trench (13), electrically insulated from the semiconductor body (12) by means of the respective insulating field plate region (14); a field plate region (16) in each trench (13); gate interconnections (28) within the semiconductor body (12), lateral to the trenches (13), electrically insulated from the semiconductor body (12) and electrically connected to the conductive gate regions (15) in such a way as to electrically interconnect the conductive gate regions (15) with each other; and body regions (17). The ones of the conductive gate regions (15) and the gate interconnections (28) are part of respective inactive gate structures (22') of the electronic device (10), adapted to locally inhibit the formation of a conduction channel through the body regions (17), and the others of the conductive gate regions (15) and gate interconnections (28) are part of respective active gate structures (22") of the electronic device (10), adapted to locally allow the formation of a conduction channel through the body regions (17).

La présente description concerne un circuit de commande (120) d'une fréquence d'un signal de sortie (Out100) d'un oscillateur en anneau (110) comprenant :- un premier transistor (T121) d'un premier type adapté à recevoir une tension de commande (Vctrl120) sur sa borne de commande et adapté à fournir un premier courant de commande (I121)de fréquence sur une première borne de conduction ;- un deuxième transistor (T122) d'un deuxième type, différent du premier type, adapté à recevoir ladite tension de commande (Vctrl120) sur sa borne de commande, et adapté à fournir un deuxième courant (I122) à une deuxième borne de conduction dudit premier transistor (T121).

A method of operating an amplifier circuit configured to provide an output signal at an output node based on an amplifier offset and at least one input signal received at input nodes of the amplifier circuit. The amplifier circuit further comprises at least one adjustment node configured to receive at least one adjustment signal. The method comprises, during a calibration phase of the amplifier circuit: selectively coupling the input nodes to a common calibration node and applying (110, 111) a common calibration voltage level thereto; iteratively varying (112, 114) the at least one adjustment signal based on a programmable control code (W) and applying the at least one varied adjustment signal to the at least one adjustment node; sensing the calibration output voltage produced at each iteration of the operation (112, 114) of varying the at least one adjustment signal and performing at least one comparison (116) among a i-th calibration output voltage provided by the amplifier and an (i+1)-th calibration output voltage; based at least on the comparison, checking (118) whether the (i+1)-th calibration output voltage has a polarity different from a polarity of the i-th calibration output voltage, and storing (119) the programmed value (W1) of the programmable control code (W) based on the positive result of the checking operation (118). The method further comprises, during an operating phase of the amplifier circuit: producing the at least one adjustment signal based on the stored (119) value (W1) of the control code (W) and applying the at least one produced adjustment signal to the at least one adjustment node as a result, and selectively decoupling the input nodes of the amplifier circuit from the common calibration node and applying at least one input signal to the input nodes of the amplifier circuit, providing an output signal at the output node of the amplifier circuit exempt from the amplifier offset as a result.

A process for forming silver-containing wettable material structures, wherein, on a metal layer (26) containing aluminum, a zinc layer (28) is deposited, the zinc layer reacting with the metal layer and creating a surface microroughness (30); the zinc layer (28) is removed; and a wettable layer (36) containing silver is deposited by vapor deposition. The wettable layer (36) is formed by an adhesion layer (33), containing titanium or chromium; a barrier layer (34), containing nickel, on the adhesion layer (33); and a bonding layer (35), containing silver, on the barrier layer (22).

Dans un contexte de croisement de domaine d'horloge, un synchroniseur à bascules présente un nombre réduit de bascules (110, 113) mises en série, recevant en entrée des données (A_q) d'un premier domaine d'horloge (107) et fournissant en sortie (120) des données dans le deuxième domaine d'horloge (114). Le deuxième signal d'horloge est à fréquence variable ajustée à une fréquence cible, par un facteur de division (k0). Les bascules (110, 113) sont cadencées par un signal d'horloge (CLK_k) sous-échantillonnant le deuxième signal d'horloge (CLK_B) par un facteur k1. Le signal d'horloge sous-échantillonné est généré par un diviseur de fréquence (301) propageant une impulsion du signal (CLK_B) toutes les k1 impulsions d'horloge, en gardant les fronts alignés. Des bascules théoriquement supplémentaires (111, 112) sont évitées.

Procédé de fabrication d'un circuit intégré monolithique, comprenant une réalisation de blocs fonctionnels (BF1, BF2) au sein et au-dessus d'au moins un matériau semiconducteur large bande disposé sur un substrat de silicium, une réalisation de parties d'interconnexion mutuellement séparées (BEOL1, BEOL2) au-dessus des blocs fonctionnels, une séparation des blocs fonctionnels, et une réalisation d'une liaison électriquement conductrice entre le substrat et une plage de contact située sur une face supérieure de la partie d'interconnexion associée à un bloc fonctionnel. La séparation (C2) des blocs fonctionnels et la réalisation (C1) de ladite liaison électriquement conductrice sont effectuées après la réalisation des parties d'interconnexion mutuellement séparées.

La présente description concerne un procédé d'authentification d'un premier dispositif (P) auprès d'un deuxième dispositif (V), le premier dispositif (P) stockant une première liste (M200) de groupes de données, comprenant les étapes suivantes : A) Envoyer, par le deuxième dispositif (V) au premier dispositif (P), une deuxième liste (I200) d'informations relatives à des données ; B) Envoyer, par le premier dispositif (P) au deuxième dispositif (V), un troisième liste (M(I200)) d'images, par une première fonction (g), de données de ladite première liste (M200) dont les informations sont celles de ladite deuxième liste (I200) ; et C) Vérifier, par le deuxième dispositif (V), si les images des données de ladite troisième liste (M(I200)) sont conformes aux données d'une quatrième liste (f(M200)) de groupes de données correspondant à l'image de la première liste (M200) par une deuxième fonction (f) dont les informations sont comprises dans la deuxième liste (I200).

An Ultra-Wideband (UWB) sensing system comprises a first and a second UWB anchors (101, 102) that reciprocally transmit an UWB frame to each other. The system obtains a channel impulse response (CIR) from each UWB frame signal received by the other UWB anchor, and compares the obtained CIR to a reference CIR to identify a path indicative of a static object's presence. The system localizes the static object using an Angle of Arrival (AoA) of each signal. By leveraging UWB anchors for dual purposes such as communication devices and radar sensors, the system enables the reuse of vehicle access infrastructure for enhanced parking sensing, potentially reducing costs.

According to an embodiment, a circuit includes a memory cell array storing memory words with data bits, data check bits, and address check bits. An error correction code (ECC) logic circuit includes an address ECC generator circuit generating address check bits, a data ECC generator circuit generating data check bits, an address ECC checker circuit verifying address check bits, and a data ECC checker/correction circuit verifying and correcting data bits using data check bits. A logic circuit arranges the bits within each memory word based on a predetermined arrangement. The address check bits may be scrambled within each word, with at least one as the least or most significant bit. The address ECC may use Single Error Detection Double Error Decoding (SEDDED) and the data ECC may use Single Error Correction Double Error Detection (SECDED). The architecture provides enhanced error detection and correction capabilities for high-integrity memory applications.

A pressure sensor (30) has a substrate (31); a deformable detection element (38) suspended on the substrate, extending at a distance from the substrate along a first direction (Z), and configured to undergo a deformation as a function of a pressure to be detected; and an anchoring structure (30) configured to support the deformable detection element (38) over the substrate. The anchoring structure has a plurality of anchoring portions (50) extending from the substrate (31), coupled to the deformable detection element (38), and arranged at a distance from each other along a second direction (Y) transversal to the first direction (Z); and a structural region (51) extending between the anchoring portions along the second direction (Y) and having at least one release opening (55).

Method for managing association between an embedded Universal Integrated Circuit Card, eUICC, for Internet of Things, IoT, devices (200) and a set of external remote manager modules (204) comprising external operational remote manager modules (204) configured to perform at least a set of operations comprising profile state management operations and remote manager modules management operations in said eUICC for IoT devices (200); wherein said method comprises: - performing in said eUICC for IoT devices (200) association between said eUICC for IoT devices (200) and at least one external handling remote manager module (202) further provided in said set of external remote manager modules (204) and configured to perform in said set of operations only remote manager modules management operations in said eUICC for IoT devices (200); and - upon receival of a request of associating an external operational remote manager module (204) issued via said at least one external handling remote manager module (202), performing in said eUICC for IoT devices (200) association between said eUICC for IoT devices (200) and at least one external operational remote manager module (204).

A Schottky diode includes a substrate with an active region. Sidewall and bottom surfaces of trench (140) extending into an epitaxial layer (104) of the substrate are lined with an insulating layer (150), and the remainder of each trench is filled with a polycrystalline silicon (polysilicon) fill (160). A doped region (164) having the same conductivity type dopant as the semiconductor substrate is implanted in the epitaxial layer at locations between adjacent trenches. A silicide (172) is provided at each polysilicon fill and a Schottky barrier (170) is provided at each doped region. An anode contact (189) for the diode contacts the silicide and Schottky barrier, and a cathode contact (196) for the diode contacts a lower surface of the substrate. The selection of a dopant concentration level for the doped region controls setting of a forward voltage V_F level for the Schottky diode.

An internal computation clock signal is derived from a clock signal and includes a number of pulses within each clock signal period equal to a number of in-memory computation (IMC) processing tiles of a tile cluster that are included within a stall domain of a neural processing circuit. The pulses of the internal computation clock signal are selectively gated to generate corresponding internal clock signals applied to respective IMC processing tiles of the tile cluster within the stall domain. Timing of IMC processing tile processing operations is controlled by the applied internal clock signal. Data communications output from the IMC processing tiles are time multiplexed over a shared resource bus to a shared compute circuit for processing in response to the internal computation clock signal.

A method, comprising: providing at least one executable software code portion (11) of a software component, SWC comprising instructions which, when the program is executed by an electronic control unit, ECU of a vehicle, cause the ECU to perform signal processing operations; providing at least one non-executable tagged software code portion (13) associated with the at least one executable software code portion (11) of the SWC, the non-executable tagged software code portions (13) comprising code comment tags of a set of code comment tags (12); providing a set of configuration values (15) of the at least one executable software code portion (11, 13) of the SWC; parsing (16) the at least one non-executable tagged software code portion (13) associated to the at least one executable software code portion (11) of the SWC, detecting the code comment tags in the at least one non-executable tagged software code portions (13); based on the detected code comment tags and on the set of configuration values (15), modifying the at least one executable software code portion (11) associated to detected code comment tags in the at least one executable software code portion (11), providing a configured SWC (17) as a result.

To form an integrated circuit package, an integrated circuit die is laterally encapsulated a by a first encapsulating body. A first plating layer, including first conductive lines and a second encapsulating body, is formed over coplanar faces of the IC die and first encapsulating body. From the opposite coplanar faces, via openings are formed extending through the first encapsulating body to the first conductive lines. A second plating layer, including second conductive lines and a third encapsulating body, is formed over the opposite coplanar faces, with the second plating layer filling the via openings and electrically connecting to the IC die.

In accordance with various embodiments of the present disclosure, a circuit board is provided that comprises a substrate (202), a metal layer (204) covering a portion of the substrate and forming at least one metal pad, and a solder mask (206) at least partly covering the metal layer and defining at least one opening. The at least one opening corresponds to the at least one metal pad such that opposing first and second edges of the metal pad are exposed within the at least one opening and opposing third and fourth edges of the metal pad are covered by the solder mask.

According to an embodiment, a high-voltage tolerant level shifter circuit (400, 500) includes input terminals for receiving complementary PWM input signals (CMDP, CMDN), output terminals for providing complementary output signals (OUTP, OUTN), and a latch circuit for translating the input signals to the output signals. The circuit has terminals for receiving floating ground (VFG) and supply (VFS) voltages, and a control circuit (802) to ensure operation within a known state. The latch circuit includes cross-coupled PMOS and NMOS transistors. NMOS input transistors are coupled to the latch circuit through cascode NMOS transistors. The floating voltages are generated based on a pre-regulated supply voltage (103), tracking ground (GND) over a first voltage range and controlled by ratio relationships over a second range. A monitoring circuit (600) generates control signals based on the pre-regulated supply voltage. The level shifter enables efficient voltage domain transfers at higher operating supplies using low-voltage devices, avoiding additional mask layers and reducing manufacturing costs and complexity.

Integrated bidirectional switch power device (930) based on gallium nitride, comprising a die (40) integrating a first and a second switch FET transistor (31, 32), and a substrate-biasing network (35; 635; 735; 835) configured to electrically couple the substrate node (SUB, 61) selectively to the source region of the first and the second switch FET transistors which is at a lower potential. The substrate-biasing network has a first and second diode (D1, D2) coupled in anti-series and formed by field effect, diode-connected transistors (M1, M2) having the same structure as the first and the second switch FET transistors (31, 32) in the same conduction, contact and gate layers. At least one resistor (R, R1, R2) has a terminal coupled to the substrate node (SUB, 61) and is formed by a resistive portion of the channel layer (43.3), laterally to a channel region (65) in a semiconductor body (41) of the die (40).

A hardware accelerator includes a plurality of functional circuits, a stream switch, and a plurality of neural network processing cores coupled to the plurality of functional circuits via the stream switch to stream data to and from functional circuits of the plurality of functional circuits, wherein the neural network processing cores include at least one sender core having a buffer whose buffer content is sharable with at least one receiver core of the neural network processing cores via at least one of a dedicated output stream link or dedicated virtual channel on a pre-existing output stream link, and wherein the at least one of the dedicated output stream link or dedicated virtual channel is dedicated to sharing the buffer content via the stream switch.

Disclosed herein is a method for controlling a stepper motor driver (5) including a control logic (14), a digital-to-analog converter, DAC (15), and two H-bridge circuits for controlling first and second windings (L1, L2) of a bipolar stepper motor (10). The method includes determining desired current signals for the windings (L1, L2) based on a rotational position of the stepper motor (10), converting the desired current signals into analog reference voltages using the DAC (15), generating pre-drive signals based on the analog reference voltages, and controlling the H-bridge circuits using the pre-drive signals to regulate currents through the windings (L1, L2). Voltage drops across sense resistors (RSNSA, RSNSB) are monitored by the control logic (14) as feedback. The desired current signals are determined by generating time-varying periodic current patterns for the windings (L1, L2), the current pattern for the second winding (L2) being phase-shifted relative to the current pattern for the first winding (L1), and both current patterns being dependent on a step frequency of the bipolar stepper motor (10).

La présente description concerne un substrat (100) stratifié pour application RF comprenant :- une première couche métallique (110) dans laquelle est formée une première cavité (116) et une ligne de transmission (400) pénétrant dans la première cavité (116),- une deuxième couche métallique (120) comprenant une deuxième cavité (126) fermée latéralement,- une troisième couche métallique (130) comprenant une troisième cavité (136) fermée latéralement,- une quatrième couche métallique (140) comprenant une quatrième cavité (146),une couche diélectrique (210, 220, 230) étant disposée entre chaque couche métallique (110, 120, 130, 140),la deuxième cavité (126), la troisième cavité (136) et la quatrième cavité (146) formant une traversée RF verticale dans le substrat (100),au moins l'une de la troisième couche métallique (130) ou de la quatrième couche métallique (140) ayant une partie faisant saillie, respectivement, dans la troisième cavité (136) ou dans la quatrième cavité (146).

An example apparatus, computer-implemented method, and electronic device comprising an ambient light sensor configured to mitigate the effects of dark count rate associated with avalanche photodiodes are provided. The example apparatus includes an exposed avalanche photodiode array, a dark avalanche photodiode array, and a controller. The exposed avalanche photodiode array is positioned to receive ambient light from an external environment. The dark avalanche photodiode array is obscured from the ambient light. The controller is configured to receive an exposed illumination count corresponding to the ambient light received at the exposed avalanche photodiode array. The controller is further configured to receive a dark illumination count corresponding to a dark count at the dark avalanche photodiode array. The controller determines an ambient light value based on a difference between the exposed illumination count and the dark illumination count.

A circuit (10; 10') comprising a switching circuit block (12) comprising a node (SW) configured to provide a modulated signal (PWM); a low-pass filter circuit block (14) coupled to the switching node (SW) of the switching circuit block (12) to receive the modulated signal (PWM), the low-pass filter circuit (14) configured to apply low-pass filtering processing to the modulated signal (PWM) at a low-pass cut-off frequency, providing a demodulated signal (RPL) to a load impedance (Rload) as a result; a replicating circuit block (16) coupled to the switching node (SW) of the switching circuit block (12) to receive the modulated signal (PWM), the replicating circuit (16) configured to apply to the modulated signal (PWM) a replica of the low-pass filtering processing of the low-pass filter circuit (14), providing a reference signal (REF) as a result; a signal processing circuit block (20) coupled to the low-pass filter circuit (14) and to the replicating filter circuit (16), the signal processing circuit block (20) configured to apply signal processing to the demodulated signal (RPL) and to the reference signal (REF), providing at least one indicator signal (Vc, Vpp) indicative of a variation of the cut-off frequency of the at least one demodulator circuit block (14) as a result.