STMicroelectronics International Patente

An input filtering stage for a processing unit in a hardware accelerator is disclosed. A hardware accelerator includes one or more processing units. Each of the one or more processing units includes a buffer and an input filtering stage. The input filtering stage is configured to receive an input data stream that includes a plurality of input channels. Data selection criteria that indicate one or more input channels of the plurality of input channels are obtained. The one or more input channels from the plurality of input channels are selected based on the data selection criteria and provided to the buffer.

A hardware accelerator includes a plurality of functional circuits, a stream switch, and a plurality of neural network processing cores coupled to the plurality of functional circuits via the stream switch to stream data to and from functional circuits of the plurality of functional circuits, wherein the neural network processing cores include at least one sender core having a buffer whose buffer content is sharable with at least one receiver core of the neural network processing cores via at least one of a dedicated output stream link or dedicated virtual channel on a pre-existing output stream link, and wherein the at least one of the dedicated output stream link or dedicated virtual channel is dedicated to sharing the buffer content via the stream switch.

Disclosed herein is a method for controlling a stepper motor driver (5) including a control logic (14), a digital-to-analog converter, DAC (15), and two H-bridge circuits for controlling first and second windings (L1, L2) of a bipolar stepper motor (10). The method includes determining desired current signals for the windings (L1, L2) based on a rotational position of the stepper motor (10), converting the desired current signals into analog reference voltages using the DAC (15), generating pre-drive signals based on the analog reference voltages, and controlling the H-bridge circuits using the pre-drive signals to regulate currents through the windings (L1, L2). Voltage drops across sense resistors (RSNSA, RSNSB) are monitored by the control logic (14) as feedback. The desired current signals are determined by generating time-varying periodic current patterns for the windings (L1, L2), the current pattern for the second winding (L2) being phase-shifted relative to the current pattern for the first winding (L1), and both current patterns being dependent on a step frequency of the bipolar stepper motor (10).

A first in-memory computation (IMC) circuit includes a first IMC processing tile coupled for data communication to a first interface circuit. A second IMC circuit includes a second IMC processing tile coupled for data communication to a second interface circuit. A shared resource bus connects the first and second interface circuits. The first and second interface circuits are controlled by mode control signals to operate in: a first communications mode where signal lines of the shared resource bus support data communications between the first and second IMC circuits; and a second communications mode where a first subset of signal lines of the shared resource bus support data communications between the first and second IMC circuits and a second, different, subset of signal lines of the shared resource bus are driven to a fixed voltage level to provide shielding for the data communications over the first subset of signal lines.

La présente description concerne un dispositif comprenant au moins : - un circuit d'émission - réception (102) configuré pour émettre des ondes radars (120) et recevoir des échos radars (1006, 1008, 1010) consécutifs à l'émission des ondes radars (120) ; - un circuit de commande (108) configuré pour commander des émissions successives d'ondes radars (120) avec des puissances croissantes d'émission par le circuit d'émission - réception (102), et pour adapter, après chaque réception des échos radars (1006, 1008, 1010) consécutifs à chacune des émissions successives d'ondes radars (120) par le circuit d'émission - réception (102), une valeur du gain en réception du circuit d'émission - réception (102) en fonction d'une durée écoulée depuis ladite émission tel qu'une amplitude maximale d'une réponse (124) des échos radars (1006, 1008, 1010) reçus du circuit d'émission - réception (102) soit inférieure à une valeur de saturation en réception du circuit d'émission - réception.

A MEMS gyroscope is described, having a microelectromechanical structure (10) with a main extension in a horizontal plane (xy) formed by a first and a second horizontal axes (x, y) and provided with: at least one first driving mass (12,D1) that performs a translation driving movement along the second horizontal axis (y) of the horizontal plane (xy); and at least one first sensing mass (14,P1), having an anchoring element (16) arranged centrally with respect to the same first sensing mass (14,P1) and connected to the anchoring element (16) by an elastic arrangement (18); wherein the first sensing mass (14,P1) is coupled to the first driving mass (12,D1) by an elastic coupling element (20) and performs a rotation movement in the horizontal plane (xy) around the anchoring element (16), dragged by the first sensing mass (12,D1), and a sensing movement of rotation outside the horizontal plane (xy) around a rotation axis (A) defined by the elastic arrangement (18), in response to a first angular velocity around the first horizontal axis (x). The rotation axis (A) extends along the second horizontal axis (y), parallel to the translation driving movement.

A method (1000), comprising: generating (1002) a range selection signal based on a comparison of a supply voltage to a threshold voltage; receiving (1004), with a floating ground generation circuit, the range selection signal; outputting (1006), with the floating ground generation circuit, either ground or a first divided voltage as a ground voltage based on a value of the range selection signal; receiving (1008), with a floating supply generation circuit, the range selection signal; and outputting (1010), with the floating supply generation circuit, either the supply voltage or a second divided voltage as a high supply voltage based on the value of the range selection signal. An integrated circuit includes a floating rail voltage generator configured to receive a supply voltage and ground and to generate a non-linear floating supply voltage and a non-linear floating ground voltage based on a range selection signal. The integrated circuit includes a range selection generator that generates the range selection signal based on a comparison between the supply voltage and a threshold voltage.

An electroacoustic actuator (10) that is microelectromechanical includes: a supporting frame (12), containing semiconductor material; a membrane (13) of semiconductor material connected to the supporting frame (12) along a perimeter; a peripheral piezoelectric actuator (14) on a peripheral portion (13a) of the membrane (13); and a central piezoelectric actuator (15) on a central portion (13b) of the membrane (13). The electroacoustic actuator (10) further comprises: elastic elements (17), defined by respective portions of the membrane (13), wherein the central portion (13b) is connected to the peripheral portion (13a) of the membrane (13) by the elastic elements (17); and metal lines (30, 35, 36) extending on the peripheral portion (13a) of the membrane (13), on respective elastic elements (17) and on the central portion (13b) of the membrane (13), from the peripheral piezoelectric actuator (14) to the central piezoelectric actuator (15).

A microelectromechanical electroacoustic transducer includes: a supporting frame (12) containing semiconductor material; a membrane (13) of semiconductor material connected to the supporting frame (12) along a perimeter; a central piezoelectric transducer (15) on a central portion (13b) of the membrane (13); elastic elements (17), defined by respective portions of the membrane (13), the central portion (13b) of the membrane (13) being connected to the supporting frame (12) by elastic elements (17); and metal lines (30, 35, 36) extending on respective elastic elements (17) and on the central portion (13b) of the membrane (13) from the elastic elements (17) to the central piezoelectric transducer (15). The metal lines (30, 35, 36) are of a metal immune to oxidation by exposure to the atmosphere.

Integrated electronic device (60) including: an upper semiconductive region (22) of a first conductivity type; a first and a second semiconductive well (24,30) of a second conductivity type, which extend in the upper semiconductive region (22); a first electronic component (2) formed in the first semiconductive well (24) and including a terminal (M2) coupled to the first semiconductive well (24); and a second electronic component (38) formed in the second semiconductive well (30) and including a terminal (M3), which is coupled to the second semiconductive well (30) and receives an electrical signal. The electronic device also includes a decoupling structure (48,62,149) interposed between the first and the second semiconductive wells (24,30) and including: a third semiconductive well (62) of the second conductivity type, which is arranged facing the second semiconductive well (30); a biasing terminal (T<p>) coupled to the third semiconductive well (62) and set to a supply voltage (VIN); and a barrier structure (149), which is arranged facing the first semiconductive well (24) and comprises a separation semiconductive region (49) of the first conductivity type and a dielectric structure (46,68) which laterally delimits the separation semiconductive region (49). Figure 5

La présente description concerne un procédé comprenant :- la détection, par un dispositif en mode carte (102), d'une première salve de communication en champ proche émise par un dispositif externe (104), la première salve comprenant une première pulsation d'une durée de Tw µs; et- l'émission, par le dispositif en mode carte en réponse au dispositif externe suite à la détection de la première pulsation de la première salve, d'une pulsation en radio fréquence d'une durée inférieure ou égale à Tw µs, dans un laps de temps inférieur ou égal à 10 µs à partir d'un front avant de la première pulsation.

A circuit (50; 50'; 55) for protection of a power transistor (14), in particular a power MOSFET, coupled at a first electrode to a battery power supply (15) and to another electrode to a load (18), and driven at a driving electrode by a driver circuit (13), whereinsaid circuit for protection (50; 50'; 55) comprises Safe Operating Area monitoring circuitry (60; 60'; 70) configured to control the transistor (14) operation with respect to its Safe Operating Area (PMS), which receives as input at least a current value (I_sense) proportional to a current (ID) flowing through said power transistor (14),said Safe Operating Area monitoring circuitry (60; 60'; 70) being configured to control the operation of the power transistor (14) with respect to said Safe Operating Area (PMS) as a function of transistor thermal behaviour information (PMS, SSI; 100) and said at least a current value proportional to a current (ID) flowing through said power transistor (14) to control the value of a junction temperature (Tj) of the transistor (14), outputting an output signal (OUT; OUT1) which value controls on and off states of said driver circuit (13) by a switch (23) driving of the power transistor to obtain a given behaviour in time of the junction temperature (Tj) of the transistor (14) within said Safe Operation Area.

A microelectromechanical electroacoustic transducer includes: a supporting frame (12) containing semiconductor material; a membrane (13) of semiconductor material connected to the supporting frame (12) along a perimeter; a piezoelectric transducer (15) on a central portion (13c) of the membrane (13). The piezoelectric transducer (15) is configured to cause a deflection at rest of the membrane (13) from a planar configuration towards a first side (13d) of the membrane (13), in the absence of electrical stimuli to the piezoelectric actuator (15), and to cause an induced deflection of the membrane (13) opposite to the deflection at rest towards a second side (13e) of the membrane (13) in response to an electrical driving signal (V<D>).

Operational amplifier (30) comprising: a first stage (32) of the current-reuse type; and a second stage (34) of the rail-to-rail type, cascaded with respect to the first stage (32). The first stage (32) comprises a first feedback assembly (32') configured to define a first feedback loop, independent of the second stage (34).

The present disclosure relates to a protection circuit (100), comprising: at least one transistor (102) having one first conduction node connected to a first node (N1) and one second conduction node connected to a second node (N2), the first node (N1) being configured to be connected to a power source (140) referenced to ground, and the second node (N2) being configured to be coupled to a load (130) referenced to ground; one driver circuit (160) coupling a control node (NG) of said at least one transistor to ground, and being configured to deactivate said at least one transistor (102) when an overvoltage or an overcurrent occurs; at least one first transient voltage suppressor diode (116) having its anode connected to a third node (N3) and its cathode coupled to the first node (N1); at least one second diode (120) having its anode connected to the third node (N3) and its cathode connected to the controlling node of said at least one transistor (102); a controllable rectifying arrangement coupling the second node (N2) to ground; and a third diode (150) having its cathode connected to a controlling node of the rectifying arrangement.

The present disclosure relates to an electronic device (100) and method of generating two phase quadrature signals using such a device, comprising: a Balun-type circuit (110) comprising a primary branch (111) and a secondary branch (112); and a filter circuit (120) adapted to provide two signals in phase quadrature on two first nodes (IM100, IP100), wherein said secondary branch (112) is connected between said first nodes (IM100, IP100), and wherein a first inductor (Lp101) of said primary branch is magnetically coupled with at least a second inductor (L101, L102) of said filter circuit (120).

Dans le boîtier (BT) on contient la colle entre la face arrière (12) de la puce (1) et la face avant (20) du substrat porteur (2) lors du placement et de la fixation de la puce (1) sur le substrat porteur (2).A cet égard, la face arrière de la puce comporte des premiers trous borgnes (13) et la face avant du substrat porteur comporte des deuxièmes trous borgnes (27) définissant des logements permettant de contenir la colle.

Electronic device (100), comprising a circuit module (6) and a protection module (50; 51). The circuit module (6) comprises a P-N junction (102) between a reference terminal (GND) and an electrical node (104), and a plurality of metal connection lines (20) coupled to the electrical node (104) and adapted to be charged due to antenna effect. The protection module (50) comprises an HV transistor (112) and a first capacitor (108). The capacitor (108) is connected between the electrical node (104) and the HV transistor (112) and is configured to turn on the HV transistor (112) when the electrical node (104) charges positively due to the antenna effect. The circuit module (6) is thus maintained at a potential that does not damage the electronic device (100).

The present disclosure relates to a transformer (3) comprising a first coil (300) and a second coil (302) inductively coupled the one with the other. The first coil comprises at least one first winding (3000) arranged in a first plan for generating a first magnetic field perpendicular to the first plan, and at least one second winding (3002) arranged in the first plan for generating a second magnetic field perpendicular to the first plan and opposite to the first field. In the first plan, a ratio between a surface delimited by the first winding (3000) and a surface delimited by the second winding (3002) is determined by a target value of a coupling coefficient between the two coils (300; 500).

A system and method are disclosed for training and optimizing machine learning models for computer vision using mixed activation functions across model layers. A baseline model is received and a search space of candidate activation functions is defined. For each candidate substitution, a zero-cost accuracy score is computed without full training, and latency and memory costs are benchmarked across target hardware devices. Using this information, an optimization process such as random search, integer linear programming, or Local Zero Cost Maxima selects a layer-specific configuration of mixed activation functions that satisfies application constraints including accuracy, latency, and memory budgets. The selected model is then trained or fine-tuned to produce an optimized model. Experimental results on YOLO architectures demonstrate improved mean Average Precision, lower latency, and reduced memory usage relative to baseline models. This approach enables efficient deployment of computer vision models across CPUs, GPUs, and neural processing units.

A system and method are provided for implementing transformer-based computer vision models on resource-constrained devices. An input image is divided into tokens, each corresponding to a patch. A background-aware vision transformer (BAViT) classifies tokens as foreground or background using a lightweight architecture without a class token and with a linear classifier for token-wise prediction. Training utilizes an accumulative cross entropy loss that aggregates token-level losses to improve accuracy. Tokens classified as background are pruned, thereby reducing computational complexity, runtime memory, and inference latency. Foreground tokens are processed in a downstream transformer-based object detection model, such as YOLOS, to generate detection outputs. The BAViT module operates as a pre-processing stage, facilitating integration with detection models without retraining. Configurations include BAViT-small with two transformer layers suitable for edge devices, supporting applications such as security and inventory tracking.

La présente description concerne un dispositif de localisation (100, 100.1, 100.2) assurant la localisation entre un utilisateur et un véhicule autonome (1000), configuré pour être embarqué dans un équipement de l'utilisateur (2000) ou dans le véhicule autonome (1000), et comprenant un circuit électronique qui échange des signaux RF avec un autre dispositif de localisation (100, 100.1, 100.2) embarqué dans le véhicule autonome (1000) ou dans l'équipement de l'utilisateur (2000) respectivement, mesurant au moins une distance, par des moyens directs tels que le temps de vol ou des moyens indirects, entre l'équipement de l'utilisateur (2000) et le véhicule autonome (1000) à l'aide des échanges de signaux RF, et localisant le véhicule autonome (1000) ou l'équipement de l'utilisateur (2000) respectivement à l'aide de la distance mesurée.

Techniques for detecting and characterizing impacts using saturation data of a low-g accelerometer are disclosed. A system for detecting impacts using a low-g accelerometer includes an accelerometer, one or more memory devices, and a processor. An acceleration measurement of an axis of the accelerometer that indicates that the axis is saturated is obtained. A direction of acceleration in the axis is obtained based on the acceleration measurement. A saturation period for the axis is determined. A determination of whether the saturation period satisfies a duration threshold is made. In response to the saturation period satisfying the duration threshold, an impact is detected and a record of the detected impact based on the direction of acceleration is stored in the one or more memory devices.

A hardware accelerator includes a plurality of functional circuits, a stream switch, one or more data reshape units coupled to the plurality of functional circuits via the stream switch to stream data to and from functional circuits of the plurality of functional circuits, and one or more In-Memory Computing (IMC) clusters coupled to the stream switch. In operation, inactive IMC devices of at least a subset of the one or more IMC clusters are accessible to at least a subset of the one or more data reshape units, via memory interface independent from the stream switch, to serve as at least part of Tightly-Coupled Memory (TCM) dedicated to at least one of the one or more data reshape units.

Apparatuses, systems, and methods for locating tag positions using a single-chip are provided. An exemplary method includes enabling a first antenna of a near-field communication (NFC) reader and disabling a second antenna of the NFC reader; obtaining a first signal via the first antenna based at least in part on enabling the first antenna and disabling the second antenna; after obtaining the first signal, enabling the second antenna and disabling the first antenna; obtaining a second signal via the second antenna based at least in part on enabling the second antenna and disabling the first antenna; and determining a respective location of a first NFC device and a second NFC device based at least in part on the first signal being indicative of a first identifier associated with the first NFC device and the second signal being indicative of a second identifier associated with the second NFC device.

La présente description concerne une alimentation à découpage (100) de type abaisseur de tension comportant : - une cellule de commutation (101) comprenant un premier commutateur (102, 104) configuré pour être périodiquement mis à l'état passant par un premier signal de commande modulé par une modulation de type modulation en largeur d'impulsion ou en fréquence d'impulsion ; - un amplificateur (114) configuré pour générer une tension d'erreur représentative d'une différence entre une tension de référence et une tension de sortie de l'alimentation destinées à être appliquées en entrée de l'amplificateur (114) ; - un circuit de retard (126) configuré pour appliquer sur le premier signal de commande un retard réduisant un écart entre la tension d'erreur et la tension de référence ; - un circuit de modulation de retard (130) configuré pour moduler la valeur du retard en fonction d'une différence entre la tension d'erreur et la tension de référence.

La présente description concerne un circuit de détection (150) d'un courant de sortie d'une alimentation à découpage (100) comprenant un montage échantillonneur bloqueur (SnH151) adapté à stocker une image dudit courant de sortie pendant une phase de non conduction d'un interrupteur haute tension (M101) de ladite alimentation à découpage (100).

Zusammenfassung wird geladen …

Zusammenfassung wird geladen …

Zusammenfassung wird geladen …

Zusammenfassung wird geladen …

Zusammenfassung wird geladen …

Zusammenfassung wird geladen …

Zusammenfassung wird geladen …

Zusammenfassung wird geladen …

Zusammenfassung wird geladen …

La présente description concerne un dispositif (10) comprenant une cellule mémoire à changement de phase (12), la cellule mémoire comprenant un premier empilement de couches (18), le premier empilement de couches (18) comprenant une couche intermédiaire (22) de matériau à changement de phase, une couche inférieure isolante (20) et une couche supérieure isolante (24), la cellule comprenant des premier (26) et deuxième (28) éléments conducteurs ayant une forme de L, le premier élément (26) s'étendant sur une première paroi latérale du premier empilement, le deuxième élément (28) s'étendant sur une deuxième paroi latérale de l'empilement opposée à la première paroi.

Zusammenfassung wird geladen …

Zusammenfassung wird geladen …

La présente description concerne un dispositif (100) de mesure d'un courant de puissance délivré par un FET de puissance principal (102), comprenant : - un FET de puissance de mesure de courant (110) couplé au FET principal ; - des premier et deuxième FET (114, 116) dont les grilles sont couplées entre elles, le premier FET étant couplé au FET de mesure de courant, dans lequel une électrode de source / drain (122) du deuxième FET est couplée à une électrode de source / drain (118) du premier FET, ou une électrode de source / drain (122) du deuxième FET est couplée à une électrode de source / drain (108) du FET principal ou à une source de tension ou une charge extérieure au dispositif, et des électrodes de source / drain (124, 126) des premier et deuxième FET sont couplées entre elles.