Intel Patente

Provided is a computer-readable medium including computer-readable instructions. When the instructions are executed by a computer, the computer may implement a method. According to this method, contextual information of a plurality of users in a conversation is generated based on messages from the plurality of users over a period of time. Then the contextual information of the plurality of users is sent to a first artificial intelligence (AI) language model as input for training the Al language model and a request is sent to the first Al language model, wherein the request requires a response associated with the contextual information.

Techniques related to accelerated video enhancement using deep learning selectively applied based on video codec information are discussed. Such techniques include applying a deep learning video enhancement network selectively to decoded non-skip blocks that are in low quantization parameter frames, bypassing the deep learning network for decoded skip blocks in low quantization parameter frames, and applying non-deep learning video enhancement to high quantization parameter frames.

Photonic packages and device assemblies that include photonic integrated circuits (PICs) are described. An example integrated circuit (IC) device assembly comprises: a circuit board; a photonic package above the circuit board and a coupling structure between the circuit board and a second surface of a package support. The photonic package comprises: the package support having a first surface and the second surface opposite the first surface; a photonic integrated circuit (PIC) die over a first portion of the second surface of the package support; a processor die over a second portion of the second surface of the package support; a first electronic integrated circuit (EIC) die coupled in a flip-chip configuration with the PIC die; a second EIC die coupled in a flip-chip configuration with the PIC die; an optical coupler at a lateral surface of the PIC die; an adhesive between the optical coupler and the lateral surface of the PIC die; and a heat sink. Each of the PIC die and the processor die is between the package support and the heat sink.

A dual inline memory module (DIMM) connector has pins to connect to pad footprints and signal routing that reduces crosstalk and noise. The shape and placement of ground pads and signal pads can improve grounding of noise signals and improve the signal isolation on the signal pins. The ground pads can have additional ground vias to increase the ground path to the ground plane.

Methods and apparatus to reduce cracking in glass cores are disclosed. An example apparatus includes a package substrate comprising a glass core having an opening extending between first and second surfaces of the glass core, the first surface opposite the second surface, and a conductive material, a first portion of the conductive material within the opening, a second portion of the conductive material protruding beyond the first surface of the glass core, a first surface of the first portion in continuity with a second surface of the second portion.

Provided is a computer-readable medium including computer-readable instructions. When the instructions are executed by a computer, the computer may implement a method. According to this method, a first group of distance-related information associated with a first proximity detection device and a user over a period of time is obtained. Furthermore, based on the first group of distance-related information, first proximity information indicating whether the first proximity detection device is proximate to the user is determined. Moreover, the first proximity information is used for authentication.

An apparatus, method, and computer-readable medium for configuring of microservices in a networked system. The method comprising monitoring one or more metrics of the networked system, determining a topology of the networked system based on the one or more metrics, and configuring of the plurality of microservices based on the topology.

It is provided an anon-transitory computer-readable medium storing instructions that, when executed by one or more processing circuitries, causing the one or more processing circuitries to perform a method for attestation of a running workload in a trusted execution environment. The method comprises generating a first measurement of a workload. The method further comprises capturing one or more snapshots of a trusted execution environment executing the workload. The one or more snapshots are captured based on one or more snapshot triggers. The method comprises generating a second measurement of the workload while the workload is being executed in the trusted execution environment. The method comprises verifying the generated second measurement. The method comprises triggering a verification failure action, if the verification of the second measurement fails.

Examples include techniques associated with causing a change to a configuration to access a storage device based on determined bandwidth capabilities for read and write transactions to the storage device and based on a determined needed bandwidth to complete monitored read and write transactions to the storage device. The configuration to be based, at least in part, on coupling to the storage device via a storage interface over a serial bus and the configuration to include a link width for the serial bus, a link speed for the serial bus, or a power state to operate the storage device.

Methods and apparatus to mitigate cracking in glass cores are disclosed. An example apparatus comprises a glass core having an opening extending between opposing surfaces of the glass core, and a metal within the opening, a gap between an interface of the metal and a sidewall of the opening.

An apparatus is disclosed that includes a network interface device comprising processors to implement network interface device functionality and communication protocol engine circuitry, wherein the network interface device is to: receive a request to write data to a memory node communicably coupled to the network interface device; identify network information corresponding to the request, wherein the network information includes at least one of quality of service (QoS), physical function (PF), virtual function (VF), name space identifier (NSID), flow ID, service level objectives (SLOs), or process address space ID (PASID); identify characteristics of the memory node, wherein the characteristics include at least page size of the memory node; and cause the data to be coalesced with other data on the memory node based on the network information and the characteristics.

A method and apparatus for authentication of a user. A user profile is generated during an initial registration. The user profile may include a trusted location of the user. During a subsequent authentication process for the user, it is determined whether the user is located in the trusted location of the user, and an access to a service for the user may be controlled based on a result of the authentication process and the determination whether the user is located in the trusted location of the user. A location-based parameter of the trusted location of the user may be determined and stored in advance, and it is determined whether the user is located in the trusted location of the user by comparing the location-based parameter of the current location of the user and the location-based parameter of the trusted location of the user.

Nanoribbon-based devices with separate gate, source, and/or drain contacts can enable forming multiple devices having one or more independent contacts from different nanoribbons in a stack. In one example, an integrated circuity structure includes a stack of two or more nanoribbons, a gate electrode material at least partially around portions of the two or more nanoribbons, and source or drain regions, where discontinuities (e.g., including an insulator material) may be present between portions of the gate electrode material and/or between portions of the source or drain regions. Independent contact structures may be coupled with the separate portions of the gate electrode material and/or with the separate portions of the source or drain regions.

This disclosure describes systems, methods, and devices for remotely controlling device settings for collaboration sessions. A device may identify an alphanumeric handle based on a location identifier of a first location associated with the device and a collaboration session identifier for a collaboration session of a collaboration application executed by the device; generate a Bluetooth Low Energy (BLE) advertising packet including a header and a payload, the header including the alphanumeric handle and a hardware identifier that identifies the device; transmit the BLE advertising packet; identify an authentication request received from a second device in the collaboration session, the authentication request including the alphanumeric handle; authenticate the second device based on the alphanumeric handle; and transmit a BLE notification packet including an indication of a volume at which the second device is to set a speaker for the collaboration session.

This disclosure describes systems, methods, and devices related to cross-channel interference. A device may detect energy on a non-primary channel to identify adjacent channel interference. The device may adjust transmission parameters based on detected interference. The device may enable communication on available channels within a basic service set bandwidth.

An integrated circuit structure comprises a first fin over a first sub-fin (104); a trench isolation structure (106) adjacent to the first sub-fin; a first gate dielectric layer (110) over the first fin, and the first gate dielectric layer on the trench isolation structure; a first gate electrode (112) over the first gate dielectric layer; a first dielectric gate cut plug (122) laterally spaced apart from the first fin, the first dielectric gate cut plug in contact with the first gate electrode; a fin-trim isolation structure (130) laterally adjacent to the first dielectric gate cut plug and the trench isolation structure; a second dielectric gate cut plug (122) laterally adjacent to the fin-trim isolation structure; a second fin over a second sub-fin (104); a second gate dielectric layer (110); and a second gate electrode (112).

Examples described herein relate to a first graphics processing unit (GPU) with at least one integrated communications system, wherein the at least one integrated communications system is to apply a reliability protocol to communicate with a second at least one integrated communications system associated with a second GPU to copy data from a first memory region to a second memory region and wherein the first memory region is associated with the first GPU and the second memory region is associated with the second GPU.

An integrated circuit structure (500) comprises: a gate stack structure (308D) comprising a gate dielectric layer and a gate electrode, the gate stack structure having a first side and a second side, the second side laterally opposite the first side; a first trench contact (310B) laterally spaced apart from the first side of the gate stack structure; a first spacer (520) laterally between the first trench contact and the first side of the gate stack structure; a second trench contact (310C) laterally spaced apart from the second side of the gate stack structure; a second spacer (520) laterally between the second trench contact and the second side of the gate stack structure; and an insulating cap layer (322, 522) on a top surface of the first spacer, on a top surface of the gate stack structure, on a top surface of the second spacer, and laterally between the first trench contact and the second trench contact.

Techniques for reconstructing a die unique wrapping key from non-volatile (NVM) memory by a memory controller circuit are described. In certain examples, a computer system includes a processing circuit to perform one or more operations according to the one or more values; a non-volatile memory; and a memory controller circuit coupled to the non-volatile memory, the memory controller circuit to: read data from the non-volatile memory, read a key mask from the non-volatile memory, perform a hashing operation on the data from the non-volatile memory to generate a digest value, perform a reversible function on the digest value and the key mask to recover a wrapping-key, and decrypt encrypted data of the data with the wrapping-key to recover one or more values for the processing circuit.

Data-dependent (memory) prefetcher support is described. In some examples, the data-dependent (memory) prefetcher utilizes metadata to predict if a data word is a valid pointer before doing a prefetch. Data words that are not deemed to be valid pointers are not used to prefetch. The metadata may be linear or physical depending on the example.

Systems and methods to trigger LLM inference based on the presences of relevant audio, such as a keyword or sound event of interest. A detection head receives acoustic embeddings from an audio encoder and determines whether the audio stream includes relevant sounds (e.g., a selected audio trigger). When the audio stream does not include relevant sounds, multimodal LLM inference is bypassed, thereby saving power and protecting privacy. When relevant sounds are detected in the audio stream by the detector, the acoustic embeddings from the audio encoder are transmitted to the multimodal LLM, which proceeds to perform inference on the acoustic embeddings. The audio encoder and/or detection head can be offloaded in the hardware and implemented before the multimodal LLM in the hardware pipeline, while the multimodal LLM can be implemented in a neural processing unit.

A method and device for generating a shared session secret with forward secrecy between a first device and a second device. The first and second devices perform mutual authentication. The first and second devices establish a first shared secret using a key encapsulation mechanism with a long-term cryptographic key pair of the devices. The first and second devices generate an ephemeral cryptographic key pair comprising an ephemeral public key and an ephemeral private key, respectively, and transfer the ephemeral public key of the device to the other device using the first shared secret. The first and second devices then establish a second shared secret using the key encapsulation mechanism with the ephemeral public keys of the first device and the second device. The second shared secret is used as a temporary shared session secret.

Integrated circuit (IC) devices having nonplanar transistor structures of complementary conductivity type.An IC device includes first and second transistors with a stack of nanoribbons in a channel region of the first transistor and one or more fins in a channel region of the second transistor, and the one or more fins may be on a trench isolation over the substrate. The nanoribbons may have upper and lower (100) surfaces, and sidewalls of the one or more fins may be (110) surfaces. The fins on the isolation structure may be between stacks of nanoribbons, the nanoribbons may be over subfins of the substrate, and the isolation structure may be between the subfins.The fins may be epitaxially grown as vertical nanoribbons from (and with a same crystal lattice and alignment as) a sidewall of the stack of nanoribbons in the first transistor.

An instruction is executed for performing a number theoretic transform (NTT). For example, one embodiment includes decode circuitry to decode the instruction; one or more packed data registers to store a first, a second, and a third plurality of source packed data elements and corresponding result packed data elements; and execution circuitry to perform the NTT using a butterfly operation including: a Montgomery multiplication of a source packed data element of the second plurality of source packed data elements and a corresponding source packed data element of the third plurality of source packed data elements using a modulus value or an inverse of the modulus value to generate a product. The product is added to a corresponding source packed data element of the first plurality for a first result and is subtracted from the corresponding source packed data element of the first plurality for the second result.

Embodiments herein relate to Static Random-Access Memory (SRAM) where a write assist technique is facilitated using power supply lines (Vcc) which extend in a word line direction. The SRAM can be implemented using complementary field-effect transistor (CFET) technology, where n-type and p-type transistors are arranged in a stacked configuration on top and bottom levels, respectively of a stack. In one aspect, a power supply line is shared by a row of adjacent memory cells. In another aspect, a power supply line is shared by a row of memory cells in alternate columns. The configurations avoid disturb of unselected cells due to a Vcc collapse during writing. In another aspect, an eight-transistor SRAM memory cell includes transistor gates to reduce Vmin, the minimum supply voltage at which a memory array can operate without failure.

Devices, transistor structures, systems, and techniques are described herein related to gate all around field effect transistors having nanoribbons selectively removed to allow for thicker gate dielectric materials. In forming an alternating stack of semiconductor and sacrificial layers, a cladding layer is applied to those semiconductor layers to be removed during nanoribbon release. Prior to nanoribbon release, atoms of the cladding layer are diffused into only those semiconductor layers having the cladding. During nanoribbon release etch, the sacrificial layers and those semiconductor layers having diffused atoms therein are removed while the semiconductor layers without cladding remain. By removing nanoribbons, an increased ribbon-to-ribbon spacing is attained for application of thicker gate dielectric materials in gate all around field effect transistors.

It is provided an apparatus comprising interface circuitry, machine-readable instructions, and processing circuitry to execute the machine-readable instructions. The machine-readable instructions include instructions to obtain a first set of data formats. The first set of data formats comprises data formats that are available to an attestation environment of a confidential computing environment for generation of attestation evidence of a confidential computing environment. The machine-readable instructions further comprise instructions to obtain a second set of data formats. The second set of data formats comprises data formats of attestation evidence that are available to an attestation verifier. The machine-readable instructions further comprise instructions to determine an optimal data format for attestation evidence of a confidential computing environment based on the first set of data formats and the second set of data formats and to generate attestation evidence of the confidential computing environment in the determined optimal data format.

Methods and apparatus to disengage a test head from an integrated circuit (IC) device are disclosed. An example apparatus comprises a test head to thermally interface with an IC device, a mounting piece to be coupled to the test head, and a push off tab to be mounted to the mounting piece, the push off tab including an arm to extend underneath the test head, the arm to contact the IC device before the test head is to contact the IC device.

Circuitry and methods for implementing conditional fence instructions are described. In certain examples, a hardware processor (e.g., core) includes a branch predictor to predict one of a taken path and a not taken path for a conditional branch instruction; decoder circuitry to decode an instruction into a decoded instruction, the instruction comprising a field that indicates a condition to be set by execution of another instruction, and an opcode that indicates execution circuitry is to, in response to the condition being satisfied, implement an execution fence to delay execution of the instruction until prior instructions in program order execute and delay execution of instructions after the instruction in program order until the instruction executes; and the execution circuitry to execute the decoded instruction according to the opcode.

Provided is an apparatus including interface circuitry, machine-readable instructions, and processing circuitry to execute the machine-readable instructions to decide on a migration of a workload from a first trusted execution environment (TEE) to a second TEE according to a migration policy. The migration policy is embedded into support infrastructure of the first TEE.

Semiconductor devices and systems with self-aligned backside contacts, and methods of forming the same, are disclosed herein. In one example, a semiconductor device includes a channel, a source and a drain, source and drain contacts, and a gate. The channel includes multiple channel structures arranged vertically and substantially in parallel. The source and the drain are at opposite ends of the channel. The source and drain contacts are coupled to the source and the drain, respectively. Moreover, one of the source contact or the drain contact is above the source or the drain and the other of the source contact or the drain contact is below the source or the drain. The gate is around the channel structures, where a portion of the gate below the channel structures is thicker than respective portions of the gate between the channel structures in cross-section view.

In embodiments of the present disclosure, enhanced nanoribbons of GAA FETs are formed using a high-temperature diffusion process before the source/drain regions are formed. The diffusion process includes forming an additive material layer (212), for example comprising germanium, around crystalline nanoribbons (210), for example comprising silicon, (Fig. 2D), forming a capping layer (214) around the additive material layer (212) (Fig. 2D), diffusing the additive material into the crystalline nanoribbons via heating, (Fig. 2E), and removing the capping layer (214) (Fig. 2F).

An apparatus includes a clock generation circuit coupled to a power train (PTR) circuit. The clock generation circuit includes an adaptive delay circuit to generate a first clock signal and a first clock delay signal based on a regulation clock signal. The clock generation circuit includes a fixed time delay circuit to generate a second clock signal and a second clock delay signal based on the regulation clock signal. The PTR circuit is to receive the first clock signal, the second clock signal, the first clock delay signal, and the second clock delay signal. The PTR circuit generates a voltage output signal based on the first clock signal, the second clock signal, the first clock delay signal, and the second clock delay signal.

Various systems and methods for establishing the management and functions of a software-defined vehicle platform are disclosed. An example technique for configuring power usage and management includes: evaluating data that enumerates characteristics of multiple vehicle electronic control units (ECUs) of the vehicle; determining power usage characteristics of the ECUs, such as power requirements and available power states of the ECUs; determining a power usage policy to apply in the vehicle, based on the power usage characteristics of the ECUs and operational conditions of the vehicle; and generating control signals to change power states used by the ECUs, based on the determined power usage policy (e.g., a power usage policy that includes restrictions for the vehicle and the various ECUs).

Methods and apparatus for semiconductor die fault analysis are disclosed. An example apparatus comprises interface circuitry, machine-readable instructions, and at least one processor circuit to be programmed by the machine-readable instructions to identify a location of a reference feature on a semiconductor die within a first image of the semiconductor die, the first image containing a region of interest on the semiconductor die adjacent to the reference feature, transform a baseline pattern of the semiconductor die to align a location of a baseline feature in the baseline pattern with the location of the reference feature in the first image, and determine a location of the region of interest in the first image based on the transformed baseline pattern.

Embodiments herein relate to compute-in-memory. In one aspect, memory cells in an array include a larger, primary element and a smaller, secondary element in parallel. The memory cells are phasechange memory (PCM) cells in an example implementation. The second elements are pre-programmed to narrow a conductivity distribution of a column of cells. The pre-programming is based on a measured conductivity distribution of the primary elements of the column. In another aspect, selected memory cells in an array are read using an alternating current (AC) signal which reduces sensing noise. Different bit lines can receive signals with different frequencies and/or amplitudes.

System and techniques for controlling or adjusting the power use of components in a vehicle are described herein. The technique may include obtaining a log of power use that records the power consumption of a component over a specified time period. Context data corresponding to this time period is collected, and a repetition metric is derived from the power consumption data. From this, a scenario context from the context data may be identified based on the repetition metric. A vehicle power profile is generated based on the identified scenario context and is subsequently applied within the vehicle to regulate a power function of the vehicle.

An apparatus for managing access to performance counters. one embodiment of a processor comprises: a plurality of cores to execute first program code at a first privilege level and second program code at a second privilege level higher than the first privilege level, a core of the plurality of cores comprising: performance monitoring circuitry including a plurality of performance counter control registers to indicate events to be counted by a corresponding plurality of performance counters; and a processor control register to store a global control value to indicate whether the first program code is permitted to read values from the corresponding plurality of performance counters; wherein each performance counter control register is to store a per-counter control value to indicate whether the first program code executed at the first privilege level is permitted to read a corresponding value from a respective performance counter, regardless of the global control value.

Integrated circuit structures having source or drain structures with vertical trenches having contacts therein are described. In an example, an integrated circuit structure includes a stack of nanowires above a sub-fin. An epitaxial source or drain structure is at an end of the stack of nanowires, the epitaxial source or drain structure having a trench therein. A conductive contact is in the trench and extends above the epitaxial source or drain structure, or an epitaxial layer is along sides and a bottom the trench and a conductive contact is within the epitaxial layer and extends above the epitaxial layer, where the epitaxial layer includes gallium.

Disclosed herein are devices, systems, and methods for cancelling an internal magnetic field caused by a test signal within a test chamber of a scanning electron microscope (SEM). A compensator device includes a set of one or more wire loops around a test chamber and an amplifier configured to drive a current in each wire loop of the set of one or more wire loops. The compensator device also includes a control circuit configured to adjust, via the amplifier, a corresponding amplitude modulation of the current in each wire loop, wherein the control circuit is configured to adjust the corresponding amplitude modulation based on a test signal within the test chamber.