Intel Patente

Systems and methods for multi-layer optical proximity correction (OPC) metrology. The OPC metrology system accesses three layers of OPC contour data, the layers of OPC data generated for a drawn integrated circuit layout characterized for a foundry process node. The three layers include a first metal layer, a second metal layer, and a via layer. A feature, such as a via, is formed in the three layers. The system receives user input defining a check (geometric analysis) for the feature, and a limit. The system performs the check on the features and generates a flag for the feature when the limit is exceeded. The system can generate output that reflects the integration of multiple checks and predicts risks and yields for the foundry process node.

According to various aspects of the present disclosure, a semiconductor testing equipment may include a thermal head assembly having a body with a recess that is unobstructed and designed to fit over a die on the semiconductor package. A sealing member on the thermal head assembly engages a landing area on the semiconductor package to form a sealed chamber. The semiconductor package may be uniformly loaded by introducing a gas and incrementally increasing the gas pressure in the sealed chamber and increasing mechanical load on the sealing member onto the landing area to prevent leakage. Once the sealed chamber is fully sealed, the combined internal pressure from the circulating gas and a sealing perimeter load enables the proper socketing of the semiconductor package. Thereafter, the gas may be replaced with a circulating liquid refrigerant to remove the heat generated by the die during the testing of the semiconductor package.

An integrated circuit (IC) device having complementary dielectric plugs separating gate electrodes. An IC device includes a first gate-cut plug of silicon and nitrogen between and in contact with two gate structures of transistors of a first conductivity type and a second gate-cut plug between and in contact with two gate structures of transistors of a second conductivity type, complementary to the first conductivity type, and the second gate-cut plug has within a liner of silicon and nitrogen either an airgap or a dielectric of silicon and oxygen. Pairs of gate structures of transistors having both of the first and second conductivity types are separated by first and second gate-cut plugs.

Devices, transistor structures, systems, and techniques are described herein related to gate all around field effect transistors having a stack of nanoribbons (i.e., semiconductor structures) contacted by epitaxial source and drain structures at opposite ends of the nanoribbons. The transistors include a gate structure vertically between the nanoribbons. The nanoribbons are doped at their opposing ends and/or gaps are laterally between the gate structure and the source and drain structures.

Integrated circuit (IC) devices having dielectric spacers between parallel channel structures (e.g., of nanoribbons, nanowires, etc.). A transistor structure may have first and second channel layers between source and drain bodies, a gate stack with a gate metal and gate dielectric between the channel layers, and a dielectric spacer between the channel layers and between the gate dielectric and one of the source and drain bodies. The dielectric spacer may have a significant (or minimal) curvature such that a width of the dielectric spacer between the channel layers is much greater (or not much greater) than widths of the dielectric spacer at the channel layers or than a minimum distance separating the gate metal between the channel layers from one of the source and drain bodies. An added or altered etch may remove sacrificial dummy gate material from between the channel layers and the gate side of the dielectric spacer.

In the various aspects, a wafer protection/coating material is provided with luminescent additives and is deposited over a BGA or a plurality of solder bumps as a protective layer during a laser scribe, a laser full cut, and/or plasma singulation process. The inclusion of luminescent additives facilitates assessing, in-line, the coating quality, i.e., thickness, specifically the coverage of the wafer protection material on top of the solder bumps using luminescent detection metrology. In an aspect, the wafer protection material may be water-soluble and may be removed after the laser/plasma process step using water.

In embodiments of the present disclosure, an integrated transistor device includes a gate-all-around (GAA) transistor and a FinFET transistor device on the same substrate. The FinFET transistor includes a dielectric region between the channel of the FinFET transistor and the substrate.

Systems, apparatus, articles of manufacture, and methods to reduce fan-induced vibration in electronic devices are disclosed. An example electronic device includes a mainboard; a fan; a chassis including a first cover and a second cover; andat least two of: (a) a fastener to couple the fan to the chassis; and a first dampener positioned between both (1) the fan and the fastener and (2) the fan and the chassis; (b) a plurality of check valves orientated in a first direction; anda plurality of inversed check valves oriented in a second direction different than the first direction, the inverse check valves to change a flow rate of air exhausted from the fan; or (c) a first plurality of second dampeners coupled between the mainboard and the first cover; and a second plurality of second dampeners coupled between the mainboard and the second cover.

Disclosed are voltage regulator embodiments with dynamically adjustable soft-switching entry (e.g., ZCD) thresholds to efficiently manage entry into soft-switching under different load conditions.

Systems, apparatus, articles of manufacture, and methods are disclosed to perform infield testing of a system in a package. An example die includes transmit circuits to communicate via respective communication channels and control circuitry to cause a first one of the transmit circuits to send a first pattern over a first one of the communication channels. Additionally, the example control circuitry is to cause second ones of the transmit circuits to respectively send a second pattern over second respective ones of the communication channels, the second pattern being at least one of an inverse of the first pattern or identical to the first pattern.

Systems, apparatus, articles of manufacture, and methods for power delivery through package substrates with stacks of glass layers having different coefficients of thermal expansion are disclosed. An example substrate for an integrated circuit package includes: a first glass layer having a first coefficient of thermal expansion (CTE); a second glass layer having a second CTE, the second CTE different from the first CTE; a conductive material extending through a first hole in the first glass layer and a second hole in the second glass layer; and a magnetic material between an inner wall of the first hole and the conductive material.

Thin film transistors are described. An integrated circuit structure includes a gate electrode. A gate dielectric layer is on the gate electrode. A channel material layer is on the gate dielectric layer. A dielectric layer is over the channel material layer. Source or drain contacts are on the channel material layer. Each of the source or drain contacts includes a semiconductor material layer, a conductive liner within the semiconductor material layer, and a conductive fill within the conductive liner. One, two or all three of the semiconductor material layer, the conductive liner, or the conductive fill has an uppermost surface below an uppermost surface of the dielectric layer.

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Techniques for encrypting data using a key generated by a physical unclonable function (PUF) or a virtual PUF key are described. An apparatus according to the present disclosure may include decoder circuitry to decode an instance of a single instruction having a field for an opcode to indicate that execution circuitry is to encrypt at least encrypt secret information from an input data structure with either a physical unclonable function (PUF) generated encryption key or a virtual PUF key, bind the wrapped secret information to an identified target, update the input data structure, generate a MAC over the updated data structure, store the MAC in the input data structure to generate a wrapped output data structure, store the wrapped output data structure having the encrypted secret information and an indication of the target;

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Technologies for epitaxial perovskite ferroelectric transistors on buffered silicon are disclosed. In an illustrative embodiment, a barrier layer of titanium nitride is deposited on a silicon substrate using domain matching epitaxy, which allows the titanium nitride to grow with relatively low stress and a low number of defects, despite a 22% misfit between the lattice constant for titanium nitride and that lattice constant for silicon. The barrier layer prevents silicon monoxide (SiO) from forming when oxides are grown as later layers. In some embodiments, some or all of the titanium nitride barrier layer may be used as a gate electrode for the transistor.

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