Intel Patente

An instruction is executed for performing a number theoretic transform (NTT). For example, one embodiment includes decode circuitry to decode the instruction; one or more packed data registers to store a first, a second, and a third plurality of source packed data elements and corresponding result packed data elements; and execution circuitry to perform the NTT using a butterfly operation including: a Montgomery multiplication of a source packed data element of the second plurality of source packed data elements and a corresponding source packed data element of the third plurality of source packed data elements using a modulus value or an inverse of the modulus value to generate a product. The product is added to a corresponding source packed data element of the first plurality for a first result and is subtracted from the corresponding source packed data element of the first plurality for the second result.

Integrated circuit (IC) devices having nonplanar transistor structures of complementary conductivity type.An IC device includes first and second transistors with a stack of nanoribbons in a channel region of the first transistor and one or more fins in a channel region of the second transistor, and the one or more fins may be on a trench isolation over the substrate. The nanoribbons may have upper and lower (100) surfaces, and sidewalls of the one or more fins may be (110) surfaces. The fins on the isolation structure may be between stacks of nanoribbons, the nanoribbons may be over subfins of the substrate, and the isolation structure may be between the subfins.The fins may be epitaxially grown as vertical nanoribbons from (and with a same crystal lattice and alignment as) a sidewall of the stack of nanoribbons in the first transistor.

A method and device for generating a shared session secret with forward secrecy between a first device and a second device. The first and second devices perform mutual authentication. The first and second devices establish a first shared secret using a key encapsulation mechanism with a long-term cryptographic key pair of the devices. The first and second devices generate an ephemeral cryptographic key pair comprising an ephemeral public key and an ephemeral private key, respectively, and transfer the ephemeral public key of the device to the other device using the first shared secret. The first and second devices then establish a second shared secret using the key encapsulation mechanism with the ephemeral public keys of the first device and the second device. The second shared secret is used as a temporary shared session secret.

Systems and methods to trigger LLM inference based on the presences of relevant audio, such as a keyword or sound event of interest. A detection head receives acoustic embeddings from an audio encoder and determines whether the audio stream includes relevant sounds (e.g., a selected audio trigger). When the audio stream does not include relevant sounds, multimodal LLM inference is bypassed, thereby saving power and protecting privacy. When relevant sounds are detected in the audio stream by the detector, the acoustic embeddings from the audio encoder are transmitted to the multimodal LLM, which proceeds to perform inference on the acoustic embeddings. The audio encoder and/or detection head can be offloaded in the hardware and implemented before the multimodal LLM in the hardware pipeline, while the multimodal LLM can be implemented in a neural processing unit.

Data-dependent (memory) prefetcher support is described. In some examples, the data-dependent (memory) prefetcher utilizes metadata to predict if a data word is a valid pointer before doing a prefetch. Data words that are not deemed to be valid pointers are not used to prefetch. The metadata may be linear or physical depending on the example.

An integrated circuit die includes an array of memory cells between a first surface and a second surface opposite the first surface. A first memory cell proximate the first surface comprises a first capacitor over a first transistor. A second memory cell under the first memory cell comprises a second capacitor under a second transistor. The first transistor may be stacked on the second transistor. The capacitors may include ferroelectric or antiferroelectric materials. The first capacitor is coupled with a first plate line located between the first surface and the array of memory cells. A via couples the second capacitor with a second plate line between the first surface and the array of memory cells.

Techniques are provided to form semiconductor devices that include forksheet transistors with a self-aligned dielectric spine and nanosheets with a wrapped-around gate dielectric. The dielectric spine may be formed prior to the formation of gate structures. In an example, first and second semiconductor devices have first and second semiconductor regions, respectively, extending in a first direction. The first and second semiconductor regions may include any number of nanosheets. A dielectric spine extends in the first direction centrally aligned between the first and second semiconductor regions. The gate dielectric of the gate structures on either side of the dielectric spine is wrapped around the semiconductor regions, such that the gate dielectric is present between the nanosheets and the dielectric spine along the second direction. The dielectric spine may include a dielectric liner that itself is removed prior to formation of the gate structures, thus provided space for the wrapped-around gate dielectric.

Disclosed are processing apparatuses and methods with a plurality of memory channels that operate at different frequency values to spread EMI emissions over a wider frequency range. The channels may or may not also employ spread spectrum clocking (SSC).

For example, an apparatus may include logic and circuitry configured to cause a non Access Point (AP) (non-AP) station (STA) to set one or more Segment-Association-Information (SAI) queue-size subfields in a control field. For example, the one or more SAI queue-size subfields may indicate queue sizes of one or more SAI queues at the non-AP STA. For example, an SAI queue of the one or more SAI queues may queue packet segments corresponding to a same application layer packet. For example, the non-AP STA may be configured to transmit a frame to an AP, wherein a Media Access Control (MAC) header of the frame includes the control field.

Integrated circuit structures having patterned nanowire thickness scaling are described. For example, a structure includes a first device of a device type including a first vertical arrangement of horizontal nanowires, and a first gate stack having a first conductive layer over a first gate dielectric layer. A second device of the device type includes a second vertical arrangement of horizontal nanowires laterally spaced apart from the first vertical arrangement of horizontal nanowires, and a second gate stack having a second conductive layer over a second gate dielectric layer. Each of the nanowires of the second vertical arrangement of nanowires has a vertical thickness less than a vertical thickness of each of the nanowires of the first vertical arrangement of horizontal nanowires. The nanowires of the second vertical arrangement of nanowires have a vertical spacing greater than a vertical spacing of the nanowires of the first vertical arrangement of horizontal nanowires.

Devices, transistor structures, systems, and techniques are described herein related to silicon on insulator (SOI) substrate integration for gate all around field effect transistors and diode devices. An integrated circuit die includes a diode device having a semiconductor layer, which is on an insulator layer of the SOI substrate, and an integrated gate all around field effect transistor fabricated within a well in the semiconductor layer to form nanoribbons each within a thickness of the semiconductor layer and absent a device subfin.

An apparatus, including: a classifier configured to classify, in real time, an application type of an application traffic stream based on one or more indicators received from one or more components of an edge device and associated with the application traffic stream; and a quality-of-service (QoS) engine configured to assign a priority to the application traffic stream by modifying its packet headers, enabling a network module to dynamically prioritize the application traffic stream based on the classification.

Systems and methods for controlling flexible displays are disclosed herein. An example apparatus includes interface circuitry; machine-readable instructions; and at least one processor circuit to at least one of instantiate or execute the machine-readable instructions to determine a distance of a user relative to a display screen based on outputs of a sensor, the sensor in communication with one or more of the at least one processor circuit; determine a curvature radius of the display screen based on the user distance; and cause an actuator to adjust a curvature of the display screen based on the curvature radius.

Embodiments herein relate to a Static Random-Access Memory (SRAM) cell having a four-level complementary-field effect transistor (CFET) structure. In an example implementation, a first, bottom level includes one or more n-channel metal-oxide-semiconductor field-effect transistors (nMOSs), a second level includes one or more pMOS transistors, a third level includes one or more pMOS transistors and a fourth, top level includes one or more nMOS transistors. The transistors can be connected using conductive paths which extend in bottom metal layers, top metal layers and intermediate metal layers between the two pMOS levels. In an example implementation, a six-transistor memory cell is provided.

An example integrated circuit (100) disclosed herein includes a first die (105) including first microbumps (135) associated with a source-synchronous data interface of a three-dimensional, 3D, die stack, a first one of the first microbumps in circuit with a clock output (125) of the first die, a second one of the first microbumps in circuit with a data output (130) of the first die, the clock output and the data output associated with a transmitter side of the source-synchronous data interface. The example integrated circuit also includes a second die (110) including second microbumps (150) associated with the source-synchronous data interface of the 3D die stack, a first one of the second microbumps in circuit with a clock input of the second die, a second one of the second microbumps in circuit with a data input of the second die, the clock input and the data input associated with a receiver side of the source-synchronous data interface.

Techniques are provided herein to form semiconductor devices having cells that include both forksheet devices and GAA devices to increase cell performance. The techniques can be used in any number of integrated circuit applications and are particularly useful with respect to logic and memory cells. The dielectric spine of the forksheet devices extends in a first direction across the cell and also acts as a gate cut between the GAA devices. Accordingly, forksheet devices are formed on one side of the cell while GAA devices are formed on the opposite side of the cell. Semiconductor material from the nanosheets and nanoribbons has a tapering width (along a second direction orthogonal to the first direction) within a transition zone between the different sides of the cell.

For example, a computing device may be configured to process sound information received from an audio device of a user to identify first ambient sound information and second ambient sound information corresponding to a detected sound event in an environment of the audio device, and to determine direction-based information based on the first ambient sound information and the second ambient sound information. For example, the direction-based information may be based on a direction of a source of the sound event relative to a head of the user. For example, the computing device may be configured to trigger a sound event indication to be provided to the user. For example, the sound event indication may be based on the direction-based information.

An integrated circuit die includes a first surface having conductive features and a second surface opposite the first surface. A device layer is proximate the first surface and includes a plurality of transistors. The device layer is between a memory layer and the first surface. The memory layer includes memory circuitry having a plurality of memory cells memory cells arranged in a cross-bar array. Each memory cell comprises first and second diodes, and a capacitor. Each diode includes an insulator material between electrodes. In some embodiments, the first and second diodes share an electrode. The capacitor includes a ferroelectric or an antiferroelectric material between electrodes.

Systems, apparatus, articles of manufacture, and methods are disclosed to improve inspection techniques for integrated circuits with backside power delivery. An example disclosed apparatus includes at least one programmable circuit to at least one of instantiate or execute the machine readable instructions to modulate first and second bitlines for a bitcell in a memory array of an integrated circuit between first and second voltages at a frequency for a period of time, the modulating of the first and second bitlines to produce a periodic heat signal in the integrated circuit, cause a thermal imaging sensor to capture a series of images of the integrated circuit during the period of time, and determine a location of a defect in the integrated circuit based on the series of images.

It is provided an apparatus comprising interface circuitry, machine-readable instructions, and processing circuitry to execute the machine-readable instructions. The machine-readable instructions include instructions to obtain a migration history log from a first confidential computing environment executing a workload. The migration history log comprising data about one or more performed migrations of the workload. The machine-readable instructions further include instructions to obtain an attestation evidence collection associated with the workload. The attestation evidence collection associated with the workload comprising one or more attestation evidence associated with the workload. The machine-readable instructions further include instructions to obtain a migration image of the workload from the first confidential computing environment. The machine-readable instructions further include instructions to transmit at least one of the migration image, the attestation evidence collection and the migration history log to a second confidential computing environment

Gate-all-around integrated circuit structures having differentiated release layers are described. For example, an integrated circuit structure includes a first set of horizontal nanowires above a sub-fin structure. A first gate structure is over the first set of horizontal nanowires. The first set of horizontal nanowires extends laterally beyond the first gate structure. A second set of horizontal nanowires is over the first set of horizontal nanowires. A second gate structure is over the second set of horizontal nanowires. The second set of horizontal nanowires extends laterally beyond the second gate structure. Dielectric spacers are adjacent to the first gate structure and the second gate structure and vertically between adjacent ones of the first set of horizontal nanowires and the second set of horizontal nanowires. Each of dielectric spacers has a notch at a location vertically between the first set of horizontal nanowires and the second set of horizontal nanowires.

Integrated circuit (IC) devices having transistors with gate electrodes coupled to a source or drain, for example, diode-connected transistors.An IC device may include a metallization level on a transistor (e.g., on and over a device layer), with a continuous first metal body in the metallization level and directly on a source or drain contact and the gate electrode. A second metal body in the metallization level may be on the other of the source or drain contacts. The metallization level (including the first and second metal bodies) may have a lower interface plane that contacts an upper contact plane of the transistor (e.g., gate electrode and source and drain contacts). The metallization level may have an upper interface plane that may be contacted by vias from an interconnect network over the transistor.

Split processing of integrated circuit layers with high accuracy bonding is described. In an example, an integrated circuit structure includes a front-end-of-line (FEOL) stack having an uppermost surface including first conductive features and first dielectric features. A back-end-of-line (BEOL) stack is above the FEOL stack. The BEOL stack has a bottommost surface including second conductive features and second dielectric features in contact with corresponding ones of the first conductive features and first dielectric features of the uppermost surface of the FEOL stack, respectively. The second conductive features are laterally offset from the corresponding first conductive features.

Microelectronic integrated circuit package structures include a package structure comprising a first die on a first dielectric material and a second die on second dielectric material, where the first die is adjacent to the second die. A third die is below the first die and is hybrid bonded to the first die. a fourth die is below the second die, and is hybrid bonded to the second die. A layer comprising nitrogen and silicon is directly on top surfaces of the first die and the second die. A fill dielectric material is between the first die and the second die, and a lid over the fill dielectric material.

A method includes generating a hash comprising a plurality of values based on a geometric pattern within a window that represents a portion of a physical design for a semiconductor mask layer, the window including at least a portion of a polygon; determining a displacement value for a segment of the polygon based on the hash; and modifying a position of a segment of the polygon based on the displacement value.

Embodiments herein relate to Static Random-Access Memory (SRAM) where a column of cells includes first and second sets of bit lines. First and second pre-charge circuits are also provided to allow independent precharging of the sets of bit lines such as for write or read operations. For a read operation, a sense circuit for the column is coupled to one of the sets of bit lines by a multiplexer. The SRAM can be implemented using complementary field-effect transistor (CFET) technology, where n-type and p-type transistors are arranged in a stacked configuration on top and bottom levels, respectively of a stack. Additionally, the first and second sets of bit lines can be provided in top and bottom metal layers, respectively, of the stack. In another option, a third set of bit lines is provided using an intermediate metal layer.

In one embodiment, an apparatus includes a circuit board (e.g., a motherboard) having conductive contacts that are integral with and extend away from a first metal layer of the circuit board. The contacts may extend away from the circuit board at an angle less than 90 degrees (e.g., less than 45 degrees in some embodiments). The contacts may include flat surfaces that are elevated away from and generally parallel with the upper surface of the circuit board.

Protrusions of socket bodies having metal are disclosed. An example apparatus comprises a socket body, the socket body including a plastic material, an array of contacts distributed across a surface of the socket body, and a protrusion extending away from the surface of the socket body, the protrusion to facilitate alignment of an IC package with the array of contacts, the protrusion including metal.

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die having a surface; a second die and a third die, the second die and the third die having a first surface and an opposing second surface, wherein the first surfaces of the second die and the third die are electrically coupled to the surface of the first die; a first material on the surface of the first die and around and between the second die and the third die, the first material having a non-planar surface; and a layer on and in physical contact with the non-planar surface of the first material and with the second surfaces of the second die and the third die, the layer including a second material having a thermal conductivity equal to or greater than 10 watt per meter-kelvin (W/m-K).

Immersion cooling systems are disclosed. An example immersion cooling system includes an immersion tank including a cooling fluid and a reservoir to contain a recirculated portion of the cooling fluid. The reservoir is separated from the immersion tank by a height to generate a liquid surface height variance between the cooling fluid in the immersion tank and the cooling fluid in the reservoir. A supply conduit is to fluidly couple the immersion tank and the reservoir. The cooling fluid to be provided from the reservoir to the immersion tank via gravity.

Devices, transistor structures, systems, and techniques are described herein related to gate all around field effect transistors having a stack of nanoribbons (i.e., semiconductor structures) contacted by epitaxial source and drain structures at opposite ends of the nanoribbons. The transistors include a gate structure vertically between the nanoribbons. The nanoribbons are doped at their opposing ends and/or gaps are laterally between the gate structure and the source and drain structures.

Integrated circuit (IC) devices having dielectric spacers between parallel channel structures (e.g., of nanoribbons, nanowires, etc.). A transistor structure may have first and second channel layers between source and drain bodies, a gate stack with a gate metal and gate dielectric between the channel layers, and a dielectric spacer between the channel layers and between the gate dielectric and one of the source and drain bodies. The dielectric spacer may have a significant (or minimal) curvature such that a width of the dielectric spacer between the channel layers is much greater (or not much greater) than widths of the dielectric spacer at the channel layers or than a minimum distance separating the gate metal between the channel layers from one of the source and drain bodies. An added or altered etch may remove sacrificial dummy gate material from between the channel layers and the gate side of the dielectric spacer.

An integrated circuit (IC) device having complementary dielectric plugs separating gate electrodes. An IC device includes a first gate-cut plug of silicon and nitrogen between and in contact with two gate structures of transistors of a first conductivity type and a second gate-cut plug between and in contact with two gate structures of transistors of a second conductivity type, complementary to the first conductivity type, and the second gate-cut plug has within a liner of silicon and nitrogen either an airgap or a dielectric of silicon and oxygen. Pairs of gate structures of transistors having both of the first and second conductivity types are separated by first and second gate-cut plugs.

An apparatus comprises a first IC die over a substrate comprising a glass core. The glass core comprises a first surface and a second surface opposite the first surface. The first surface comprises an area of at least 5,000 mm². A redistribution layer is on the first surface. The redistribution layer comprises a thickness of 100 µm or less. An electrical component is within a region of the glass core between the first and second surfaces. A through-glass via extends between the first and second surfaces. A second IC die is over and directly bonded to the first IC die.

According to various aspects of the present disclosure, a semiconductor testing equipment may include a thermal head assembly having a body with a recess that is unobstructed and designed to fit over a die on the semiconductor package. A sealing member on the thermal head assembly engages a landing area on the semiconductor package to form a sealed chamber. The semiconductor package may be uniformly loaded by introducing a gas and incrementally increasing the gas pressure in the sealed chamber and increasing mechanical load on the sealing member onto the landing area to prevent leakage. Once the sealed chamber is fully sealed, the combined internal pressure from the circulating gas and a sealing perimeter load enables the proper socketing of the semiconductor package. Thereafter, the gas may be replaced with a circulating liquid refrigerant to remove the heat generated by the die during the testing of the semiconductor package.

Systems and methods for multi-layer optical proximity correction (OPC) metrology. The OPC metrology system accesses three layers of OPC contour data, the layers of OPC data generated for a drawn integrated circuit layout characterized for a foundry process node. The three layers include a first metal layer, a second metal layer, and a via layer. A feature, such as a via, is formed in the three layers. The system receives user input defining a check (geometric analysis) for the feature, and a limit. The system performs the check on the features and generates a flag for the feature when the limit is exceeded. The system can generate output that reflects the integration of multiple checks and predicts risks and yields for the foundry process node.

In embodiments of the present disclosure, an integrated transistor device includes a gate-all-around (GAA) transistor and a FinFET transistor device on the same substrate. The FinFET transistor includes a dielectric region between the channel of the FinFET transistor and the substrate.

In the various aspects, a wafer protection/coating material is provided with luminescent additives and is deposited over a BGA or a plurality of solder bumps as a protective layer during a laser scribe, a laser full cut, and/or plasma singulation process. The inclusion of luminescent additives facilitates assessing, in-line, the coating quality, i.e., thickness, specifically the coverage of the wafer protection material on top of the solder bumps using luminescent detection metrology. In an aspect, the wafer protection material may be water-soluble and may be removed after the laser/plasma process step using water.

The lack of knowledge about a downstream consumer using a resized image can lead to poor inference quality of a machine learning model. Inference quality can be improved when the resizing algorithm to produce resized images closely matches the one used during training of the machine learning model. To achieve this technical task, a resizer can be made aware of downstream consumer information and apply a suitable resizing algorithm. In one scenario, the downstream consumer information is received as metadata from a downstream process. In another scenario, an optimal resizing option can be determined to maximize inference quality. In yet another scenario, a likely resizing option can be determined by assessing a filtering profile determined based on a known original image and a known resized image.

The present disclosure generally relates to a method that includes providing a photomask, wherein the photomask includes a trench defined by two sidewalls which are exposed, introducing the photomask into a controlled environment, and directing (i) one or more reactive gases, (ii) a laser, (iii) one or more reactive gases and a laser, or (iv) one or more reactive gases and an electron beam, to the two sidewalls to render a passivation layer adjacent to and in contact with each sidewall. An apparatus and the photomask are also described.