Intel Patente

Systems and methods for controlling flexible displays are disclosed herein. An example apparatus includes interface circuitry; machine-readable instructions; and at least one processor circuit to at least one of instantiate or execute the machine-readable instructions to determine a distance of a user relative to a display screen based on outputs of a sensor, the sensor in communication with one or more of the at least one processor circuit; determine a curvature radius of the display screen based on the user distance; and cause an actuator to adjust a curvature of the display screen based on the curvature radius.

Data-dependent (memory) prefetcher support is described. In some examples, the data-dependent (memory) prefetcher utilizes metadata to predict if a data word is a valid pointer before doing a prefetch. Data words that are not deemed to be valid pointers are not used to prefetch. The metadata may be linear or physical depending on the example.

Systems and methods to trigger LLM inference based on the presences of relevant audio, such as a keyword or sound event of interest. A detection head receives acoustic embeddings from an audio encoder and determines whether the audio stream includes relevant sounds (e.g., a selected audio trigger). When the audio stream does not include relevant sounds, multimodal LLM inference is bypassed, thereby saving power and protecting privacy. When relevant sounds are detected in the audio stream by the detector, the acoustic embeddings from the audio encoder are transmitted to the multimodal LLM, which proceeds to perform inference on the acoustic embeddings. The audio encoder and/or detection head can be offloaded in the hardware and implemented before the multimodal LLM in the hardware pipeline, while the multimodal LLM can be implemented in a neural processing unit.

Embodiments herein relate to Static Random-Access Memory (SRAM) where a write assist technique is facilitated using power supply lines (Vcc) which extend in a word line direction. The SRAM can be implemented using complementary field-effect transistor (CFET) technology, where n-type and p-type transistors are arranged in a stacked configuration on top and bottom levels, respectively of a stack. In one aspect, a power supply line is shared by a row of adjacent memory cells. In another aspect, a power supply line is shared by a row of memory cells in alternate columns. The configurations avoid disturb of unselected cells due to a Vcc collapse during writing. In another aspect, an eight-transistor SRAM memory cell includes transistor gates to reduce Vmin, the minimum supply voltage at which a memory array can operate without failure.

An integrated circuit die includes an array of memory cells between a first surface and a second surface opposite the first surface. A first memory cell proximate the first surface comprises a first capacitor over a first transistor. A second memory cell under the first memory cell comprises a second capacitor under a second transistor. The first transistor may be stacked on the second transistor. The capacitors may include ferroelectric or antiferroelectric materials. The first capacitor is coupled with a first plate line located between the first surface and the array of memory cells. A via couples the second capacitor with a second plate line between the first surface and the array of memory cells.

Various systems and methods for establishing the management and functions of a software-defined vehicle platform are disclosed. An example technique for configuring power usage and management includes: evaluating data that enumerates characteristics of multiple vehicle electronic control units (ECUs) of the vehicle; determining power usage characteristics of the ECUs, such as power requirements and available power states of the ECUs; determining a power usage policy to apply in the vehicle, based on the power usage characteristics of the ECUs and operational conditions of the vehicle; and generating control signals to change power states used by the ECUs, based on the determined power usage policy (e.g., a power usage policy that includes restrictions for the vehicle and the various ECUs).

Methods and apparatus for semiconductor die fault analysis are disclosed. An example apparatus comprises interface circuitry, machine-readable instructions, and at least one processor circuit to be programmed by the machine-readable instructions to identify a location of a reference feature on a semiconductor die within a first image of the semiconductor die, the first image containing a region of interest on the semiconductor die adjacent to the reference feature, transform a baseline pattern of the semiconductor die to align a location of a baseline feature in the baseline pattern with the location of the reference feature in the first image, and determine a location of the region of interest in the first image based on the transformed baseline pattern.

Techniques are provided to form semiconductor devices that include forksheet transistors with a self-aligned dielectric spine and nanosheets with a wrapped-around gate dielectric. The dielectric spine may be formed prior to the formation of gate structures. In an example, first and second semiconductor devices have first and second semiconductor regions, respectively, extending in a first direction. The first and second semiconductor regions may include any number of nanosheets. A dielectric spine extends in the first direction centrally aligned between the first and second semiconductor regions. The gate dielectric of the gate structures on either side of the dielectric spine is wrapped around the semiconductor regions, such that the gate dielectric is present between the nanosheets and the dielectric spine along the second direction. The dielectric spine may include a dielectric liner that itself is removed prior to formation of the gate structures, thus provided space for the wrapped-around gate dielectric.

An instruction is executed for performing a number theoretic transform (NTT). For example, one embodiment includes decode circuitry to decode the instruction; one or more packed data registers to store a first, a second, and a third plurality of source packed data elements and corresponding result packed data elements; and execution circuitry to perform the NTT using a butterfly operation including: a Montgomery multiplication of a source packed data element of the second plurality of source packed data elements and a corresponding source packed data element of the third plurality of source packed data elements using a modulus value or an inverse of the modulus value to generate a product. The product is added to a corresponding source packed data element of the first plurality for a first result and is subtracted from the corresponding source packed data element of the first plurality for the second result.

It is provided an apparatus comprising interface circuitry, machine-readable instructions, and processing circuitry to execute the machine-readable instructions. The machine-readable instructions include instructions to obtain a first set of data formats. The first set of data formats comprises data formats that are available to an attestation environment of a confidential computing environment for generation of attestation evidence of a confidential computing environment. The machine-readable instructions further comprise instructions to obtain a second set of data formats. The second set of data formats comprises data formats of attestation evidence that are available to an attestation verifier. The machine-readable instructions further comprise instructions to determine an optimal data format for attestation evidence of a confidential computing environment based on the first set of data formats and the second set of data formats and to generate attestation evidence of the confidential computing environment in the determined optimal data format.

Methods and apparatus to disengage a test head from an integrated circuit (IC) device are disclosed. An example apparatus comprises a test head to thermally interface with an IC device, a mounting piece to be coupled to the test head, and a push off tab to be mounted to the mounting piece, the push off tab including an arm to extend underneath the test head, the arm to contact the IC device before the test head is to contact the IC device.

Circuitry and methods for implementing conditional fence instructions are described. In certain examples, a hardware processor (e.g., core) includes a branch predictor to predict one of a taken path and a not taken path for a conditional branch instruction; decoder circuitry to decode an instruction into a decoded instruction, the instruction comprising a field that indicates a condition to be set by execution of another instruction, and an opcode that indicates execution circuitry is to, in response to the condition being satisfied, implement an execution fence to delay execution of the instruction until prior instructions in program order execute and delay execution of instructions after the instruction in program order until the instruction executes; and the execution circuitry to execute the decoded instruction according to the opcode.

Provided is an apparatus including interface circuitry, machine-readable instructions, and processing circuitry to execute the machine-readable instructions to decide on a migration of a workload from a first trusted execution environment (TEE) to a second TEE according to a migration policy. The migration policy is embedded into support infrastructure of the first TEE.

Techniques for reconstructing a die unique wrapping key from non-volatile (NVM) memory by a memory controller circuit are described. In certain examples, a computer system includes a processing circuit to perform one or more operations according to the one or more values; a non-volatile memory; and a memory controller circuit coupled to the non-volatile memory, the memory controller circuit to: read data from the non-volatile memory, read a key mask from the non-volatile memory, perform a hashing operation on the data from the non-volatile memory to generate a digest value, perform a reversible function on the digest value and the key mask to recover a wrapping-key, and decrypt encrypted data of the data with the wrapping-key to recover one or more values for the processing circuit.

Improved breakdown test structures are provided. In some embodiments, multiple test structures may be combined into a single (e.g., two-terminal) test structure for monitoring interconnect voltage breakdown (VBD) of representative interconnect structures within scribe line regions.

Disclosed herein is zero-latency switching between two resolution and frame rate modes. The system includes receiving a trigger to switch a video data stream of frames between a first resolution and frame rate mode and a second resolution and frame rate mode. The system also includes switching, in response to the trigger, the video data stream between the first resolution and frame rate mode and the second resolution and frame rate mode, wherein a total horizontal pixel width of each frame of the video data stream in the first resolution and frame rate mode and of each frame of the video data stream in the second resolution and frame rate mode are the same, wherein a pixel clock rate of the video data stream in the first resolution and frame rate mode and the video data stream in the second resolution and frame rate mode are the same.

An apparatus for managing access to performance counters. one embodiment of a processor comprises: a plurality of cores to execute first program code at a first privilege level and second program code at a second privilege level higher than the first privilege level, a core of the plurality of cores comprising: performance monitoring circuitry including a plurality of performance counter control registers to indicate events to be counted by a corresponding plurality of performance counters; and a processor control register to store a global control value to indicate whether the first program code is permitted to read values from the corresponding plurality of performance counters; wherein each performance counter control register is to store a per-counter control value to indicate whether the first program code executed at the first privilege level is permitted to read a corresponding value from a respective performance counter, regardless of the global control value.

Techniques are provided herein to form semiconductor devices that include forksheet transistors with a self-aligned dielectric spine having an airgap. The airgap may constitute a majority of the total volume of the dielectric spine, this lowering the dielectric constant of the dielectric spine and decreasing parasitic capacitance. In an example, first and second semiconductor devices have first and second semiconductor regions, respectively, extending in a first direction between corresponding source and drain regions. The first and second semiconductor regions may include any number of nanosheets. A dielectric spine extends in the first direction between the first and second semiconductor regions. The dielectric spine includes a dielectric liner adjacent to the sides of the first and second semiconductor regions. A remaining volume of the dielectric spine at least partially bound by the dielectric liner includes an airgap. A dielectric cap structure may be included over the airgap.

In one embodiment, an apparatus includes a circuit board (e.g., a motherboard) having conductive contacts that are integral with and extend away from a first metal layer of the circuit board. The contacts may extend away from the circuit board at an angle less than 90 degrees (e.g., less than 45 degrees in some embodiments). The contacts may include flat surfaces that are elevated away from and generally parallel with the upper surface of the circuit board.

System and techniques for controlling or adjusting the power use of components in a vehicle are described herein. The technique may include obtaining a log of power use that records the power consumption of a component over a specified time period. Context data corresponding to this time period is collected, and a repetition metric is derived from the power consumption data. From this, a scenario context from the context data may be identified based on the repetition metric. A vehicle power profile is generated based on the identified scenario context and is subsequently applied within the vehicle to regulate a power function of the vehicle.

Gate-all-around integrated circuit structures having differentiated release layers are described. For example, an integrated circuit structure includes a first set of horizontal nanowires above a sub-fin structure. A first gate structure is over the first set of horizontal nanowires. The first set of horizontal nanowires extends laterally beyond the first gate structure. A second set of horizontal nanowires is over the first set of horizontal nanowires. A second gate structure is over the second set of horizontal nanowires. The second set of horizontal nanowires extends laterally beyond the second gate structure. Dielectric spacers are adjacent to the first gate structure and the second gate structure and vertically between adjacent ones of the first set of horizontal nanowires and the second set of horizontal nanowires. Each of dielectric spacers has a notch at a location vertically between the first set of horizontal nanowires and the second set of horizontal nanowires.

Systems, apparatus, articles of manufacture, and methods are disclosed to improve inspection techniques for integrated circuits with backside power delivery. An example disclosed apparatus includes at least one programmable circuit to at least one of instantiate or execute the machine readable instructions to modulate first and second bitlines for a bitcell in a memory array of an integrated circuit between first and second voltages at a frequency for a period of time, the modulating of the first and second bitlines to produce a periodic heat signal in the integrated circuit, cause a thermal imaging sensor to capture a series of images of the integrated circuit during the period of time, and determine a location of a defect in the integrated circuit based on the series of images.

For example, a computing device may be configured to process sound information received from an audio device of a user to identify first ambient sound information and second ambient sound information corresponding to a detected sound event in an environment of the audio device, and to determine direction-based information based on the first ambient sound information and the second ambient sound information. For example, the direction-based information may be based on a direction of a source of the sound event relative to a head of the user. For example, the computing device may be configured to trigger a sound event indication to be provided to the user. For example, the sound event indication may be based on the direction-based information.

In embodiments of the present disclosure, enhanced nanoribbons of GAA FETs are formed using a high-temperature diffusion process before the source/drain regions are formed. The diffusion process includes forming an additive material layer (212), for example comprising germanium, around crystalline nanoribbons (210), for example comprising silicon, (Fig. 2D), forming a capping layer (214) around the additive material layer (212) (Fig. 2D), diffusing the additive material into the crystalline nanoribbons via heating, (Fig. 2E), and removing the capping layer (214) (Fig. 2F).

Embodiments herein relate to a Static Random-Access Memory (SRAM) cell having a four-level complementary-field effect transistor (CFET) structure. In an example implementation, a first, bottom level includes one or more n-channel metal-oxide-semiconductor field-effect transistors (nMOSs), a second level includes one or more pMOS transistors, a third level includes one or more pMOS transistors and a fourth, top level includes one or more nMOS transistors. The transistors can be connected using conductive paths which extend in bottom metal layers, top metal layers and intermediate metal layers between the two pMOS levels. In an example implementation, a six-transistor memory cell is provided.

An example integrated circuit (100) disclosed herein includes a first die (105) including first microbumps (135) associated with a source-synchronous data interface of a three-dimensional, 3D, die stack, a first one of the first microbumps in circuit with a clock output (125) of the first die, a second one of the first microbumps in circuit with a data output (130) of the first die, the clock output and the data output associated with a transmitter side of the source-synchronous data interface. The example integrated circuit also includes a second die (110) including second microbumps (150) associated with the source-synchronous data interface of the 3D die stack, a first one of the second microbumps in circuit with a clock input of the second die, a second one of the second microbumps in circuit with a data input of the second die, the clock input and the data input associated with a receiver side of the source-synchronous data interface.

Systems, apparatus, articles of manufacture, and methods are disclosed for inductors of voltage regulators that are built into and/or around mounting holes of a printed circuit board. An example apparatus includes a printed circuit board that includes a plurality of layers and a mounting hole extending through the plurality of layers, and an inductor at least partially in the mounting hole between two or more of the plurality of layers.

An apparatus, including: a classifier configured to classify, in real time, an application type of an application traffic stream based on one or more indicators received from one or more components of an edge device and associated with the application traffic stream; and a quality-of-service (QoS) engine configured to assign a priority to the application traffic stream by modifying its packet headers, enabling a network module to dynamically prioritize the application traffic stream based on the classification.

Integrated circuit structures having patterned nanowire thickness scaling are described. For example, a structure includes a first device of a device type including a first vertical arrangement of horizontal nanowires, and a first gate stack having a first conductive layer over a first gate dielectric layer. A second device of the device type includes a second vertical arrangement of horizontal nanowires laterally spaced apart from the first vertical arrangement of horizontal nanowires, and a second gate stack having a second conductive layer over a second gate dielectric layer. Each of the nanowires of the second vertical arrangement of nanowires has a vertical thickness less than a vertical thickness of each of the nanowires of the first vertical arrangement of horizontal nanowires. The nanowires of the second vertical arrangement of nanowires have a vertical spacing greater than a vertical spacing of the nanowires of the first vertical arrangement of horizontal nanowires.

System and techniques for facility floor modeling are described herein. A scan set that includes depth data and correlated image data from various positions on a facility floor is obtained. This data includes representations of equipment in the factory. A trained model is invoked, receiving the scan set as input and producing, as output, a computer model of the equipment along with associated information. The computer model of the equipment is integrated into a larger computer model of the factory and the information regarding the equipment is stored in a data structure that corresponds to the equipment's representation within the computer model of the factory.

Integrated circuit structures having source or drain structures with vertical trenches having contacts therein are described. In an example, an integrated circuit structure includes a stack of nanowires above a sub-fin. An epitaxial source or drain structure is at an end of the stack of nanowires, the epitaxial source or drain structure having a trench therein. A conductive contact is in the trench and extends above the epitaxial source or drain structure, or an epitaxial layer is along sides and a bottom the trench and a conductive contact is within the epitaxial layer and extends above the epitaxial layer, where the epitaxial layer includes gallium.

Embodiments herein relate to compute-in-memory. In one aspect, memory cells in an array include a larger, primary element and a smaller, secondary element in parallel. The memory cells are phasechange memory (PCM) cells in an example implementation. The second elements are pre-programmed to narrow a conductivity distribution of a column of cells. The pre-programming is based on a measured conductivity distribution of the primary elements of the column. In another aspect, selected memory cells in an array are read using an alternating current (AC) signal which reduces sensing noise. Different bit lines can receive signals with different frequencies and/or amplitudes.

An integrated circuit die includes a first surface having conductive features and a second surface opposite the first surface. A device layer is proximate the first surface and includes a plurality of transistors. The device layer is between a memory layer and the first surface. The memory layer includes memory circuitry having a plurality of memory cells memory cells arranged in a cross-bar array. Each memory cell comprises first and second diodes, and a capacitor. Each diode includes an insulator material between electrodes. In some embodiments, the first and second diodes share an electrode. The capacitor includes a ferroelectric or an antiferroelectric material between electrodes.

It is provided an apparatus comprising interface circuitry, machine-readable instructions, and processing circuitry to execute the machine-readable instructions. The machine-readable instructions include instructions to obtain a migration history log from a first confidential computing environment executing a workload. The migration history log comprising data about one or more performed migrations of the workload. The machine-readable instructions further include instructions to obtain an attestation evidence collection associated with the workload. The attestation evidence collection associated with the workload comprising one or more attestation evidence associated with the workload. The machine-readable instructions further include instructions to obtain a migration image of the workload from the first confidential computing environment. The machine-readable instructions further include instructions to transmit at least one of the migration image, the attestation evidence collection and the migration history log to a second confidential computing environment

Devices, transistor structures, systems, and techniques are described herein related to silicon on insulator (SOI) substrate integration for gate all around field effect transistors and diode devices. An integrated circuit die includes a diode device having a semiconductor layer, which is on an insulator layer of the SOI substrate, and an integrated gate all around field effect transistor fabricated within a well in the semiconductor layer to form nanoribbons each within a thickness of the semiconductor layer and absent a device subfin.

For example, an apparatus may include logic and circuitry configured to cause a non Access Point (AP) (non-AP) station (STA) to set one or more Segment-Association-Information (SAI) queue-size subfields in a control field. For example, the one or more SAI queue-size subfields may indicate queue sizes of one or more SAI queues at the non-AP STA. For example, an SAI queue of the one or more SAI queues may queue packet segments corresponding to a same application layer packet. For example, the non-AP STA may be configured to transmit a frame to an AP, wherein a Media Access Control (MAC) header of the frame includes the control field.

Semiconductor devices and systems with self-aligned backside contacts, and methods of forming the same, are disclosed herein. In one example, a semiconductor device includes a channel, a source and a drain, source and drain contacts, and a gate. The channel includes multiple channel structures arranged vertically and substantially in parallel. The source and the drain are at opposite ends of the channel. The source and drain contacts are coupled to the source and the drain, respectively. Moreover, one of the source contact or the drain contact is above the source or the drain and the other of the source contact or the drain contact is below the source or the drain. The gate is around the channel structures, where a portion of the gate below the channel structures is thicker than respective portions of the gate between the channel structures in cross-section view.

A method and device for generating a shared session secret with forward secrecy between a first device and a second device. The first and second devices perform mutual authentication. The first and second devices establish a first shared secret using a key encapsulation mechanism with a long-term cryptographic key pair of the devices. The first and second devices generate an ephemeral cryptographic key pair comprising an ephemeral public key and an ephemeral private key, respectively, and transfer the ephemeral public key of the device to the other device using the first shared secret. The first and second devices then establish a second shared secret using the key encapsulation mechanism with the ephemeral public keys of the first device and the second device. The second shared secret is used as a temporary shared session secret.

Integrated circuit (IC) devices having nonplanar transistor structures of complementary conductivity type.An IC device includes first and second transistors with a stack of nanoribbons in a channel region of the first transistor and one or more fins in a channel region of the second transistor, and the one or more fins may be on a trench isolation over the substrate. The nanoribbons may have upper and lower (100) surfaces, and sidewalls of the one or more fins may be (110) surfaces. The fins on the isolation structure may be between stacks of nanoribbons, the nanoribbons may be over subfins of the substrate, and the isolation structure may be between the subfins.The fins may be epitaxially grown as vertical nanoribbons from (and with a same crystal lattice and alignment as) a sidewall of the stack of nanoribbons in the first transistor.

An apparatus includes a clock generation circuit coupled to a power train (PTR) circuit. The clock generation circuit includes an adaptive delay circuit to generate a first clock signal and a first clock delay signal based on a regulation clock signal. The clock generation circuit includes a fixed time delay circuit to generate a second clock signal and a second clock delay signal based on the regulation clock signal. The PTR circuit is to receive the first clock signal, the second clock signal, the first clock delay signal, and the second clock delay signal. The PTR circuit generates a voltage output signal based on the first clock signal, the second clock signal, the first clock delay signal, and the second clock delay signal.