Intel Patente

Systems, apparatus, and methods for energy harvesting in data centers are disclosed. An example apparatus includes interface circuitry; machine-readable instructions; and at least one processor circuit to at least one of instantiate or execute the machine-readable instructions to estimate first power consumption values for electronic components of a first rack; estimate second power consumption values for electronic components of a second rack; determine a first selection score for the first rack based on the first power consumption values and a second selection score for the second rack based on the second power consumption values; select a first electronic component of the first rack or a second electronic component of the second rack to receive a workload based on the first selection score and the second selection score; and cause the selected one of the first electronic component or the second electronic component to perform the workload.

Techniques are provided herein to form semiconductor devices with thermal management structures designed to provide additional heat dissipation paths. A semiconductor device includes a gate structure around or otherwise on a semiconductor region that extends from a source region to a drain region. In one example, a subfin region beneath the semiconductor region is removed and replaced with a material having a thermal conductivity of at least 1.5 W/m·K. In another example, a material layer is formed between conductive contacts on the top surfaces of the source and drain regions that has a thermal conductivity of at least 1.5 W/m·K. In another example, the conductive contacts extend through at least 50% of an entire height of the source and drain regions to provide an enhanced thermal path. Any of the above-mentioned structures may also be combined in one or more devices to provide multiple different thermal management structures.

Described herein are nanoribbon transistors with lined cavity spacers deposited near the ends of the nanoribbons, including between the ends of adjacent nanoribbons. The cavity spacers include a liner layer next to the gate stack, and a fill material nested within the liner layer and adjacent to the source or drain. The liner layer is a non-oxide dielectric. For example, the liner may be a low-k nitride. The liner layer may be conformally deposited, and a portion of the liner layer may extend between the gate stack and the source or drain. Using a non-oxide material prevents removal of the liner during an oxide clean step prior to nanoribbon release.

In one example, a microelectronic assembly with disaggregated components includes an interposer over a substrate and conductive interconnects (e.g., one or more of conductive pillars, solder caps, and solder balls) between and coupled with the substrate and the interposer. One or more dies may be coupled with a top side of the interposer. A further die may be coupled with the package side of the interposer. The further die may be, for example, in the bump field between the interposer and the substrate. In some examples, the further die may be embedded in the substrate. In some examples, the further die may be TSV-less, and lack conductive interconnects in direct contact with conductive contacts of the substrate. In some examples, the further die may be embedded within redistribution layers (RDLs) of the interposer and coplanar with conductive pillars between RDLs.

An apparatus is described, where the apparatus may include: an interface configured to communicate with a first further communication device attachable to a communication device and a second further communication device external to the communication device and the first further communication device; and a processor configured to: determine a result representing whether the first further communication device is in an idle mode; instruct, based on the result, the first further communication device to perform channel measurements; obtain channel measurement results of the first further communication device from the interface; and configure the interface with a configuration that is based on the channel measurement results of the first further communication device to communicate with the second further communication device.

A circuitry may include: a first digital-to-time converter, DTC, configured to generate a first output signal by sampling a phase modulation command signal; a second DTC configured to generate a second output signal based on the phase modulation command signal with a programmable delay relative to the first output signal; and a phase inverter configured to invert a phase of one of the first output signal or the second output signal.

Disclosed examples include video frame segmenter circuitry to generate segmentation data of first video frame pixel data, the segmentation data including metadata corresponding to a foreground region and a background region, the foreground region corresponding to the first video frame pixel data. The disclosed examples also include video encoder circuitry to generate a first foreground bounding region and a first background bounding region based on the segmentation data, determine a first virtual tile of the first video frame pixel data, the first virtual tile located in the first foreground bounding region, encode the first virtual tile into a video data bitstream without encoding the first background bounding region, and transmit the video data bitstream via a network.

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a die surrounded by an insulating material, the die having a first conductive contact at a first surface and a second conductive contact at a second surface opposite the first surface, a first redistribution layer (RDL), on the first surface of the die, including a first conductive pathway through a first dielectric material electrically coupled to the first conductive contact of the die by a first solderless metal-metal interconnect; and a second RDL, on second surface of the die, including a second conductive pathway through a second dielectric material electrically coupled to the second conductive contact of the die by a second solderless metal-metal interconnect, wherein a thickness of the die is between 20 microns and 45 microns. In some embodiments, a thickness of the die is between 60 microns and 75 microns.

Integrated circuit (IC) die packages including a glass with conductive features embedded within the glass, such as through-glass vias (TGVs). The embedded features comprise metallization separated from the glass by an intervening multi-layered liner that includes both organic and inorganic material layers. In exemplary embodiments, the organic material has a low elastic (Young's) modulus to accommodate internal stress between the glass and the metallization. An inorganic material layer of the liner may be nitride, such as a metal nitride or silicon nitride, and in direct contact with the glass. The multi-layered liner stack may further comprise another inorganic material layer in contact with the metallization and encapsulating the organic material layer.

Architectures and methods for differential CMOS contact profiles. Architectures include a CMOS isolation layer with a plurality of negative metal oxide semiconductor (NMOS) regions and a plurality of positive metal oxide semiconductor (PMOS) regions. The NMOS regions have a respective NMOS contact characterized by a first cavity formed in an upper surface of the isolation layer, extending orthogonally into the NMOS region to a first depth, and filled with a conductive material. The PMOS regions have a respective PMOS contact characterized by a second cavity formed in the upper surface of the isolation layer, extending orthogonally into the PMOS region to a second depth, and filled with the conductive material. The first depth is more than four times the second depth.

A voltage-mode amplifier, comprising a first filter stage, comprising: a first voltage amplifier, connected to an input trace, and configured to amplify a signal conducted along the input trace; and a first N-path filter, connected to the input trace; wherein the first N-path filter is configured to shunt to a first reference voltage frequency from the signal; and a second filter stage, connected to the input trace in parallel to the first filter stage, comprising: a second voltage amplifier, connected to the input trace, and configured to amplify the signal conducted along the input trace; and a second N-path filter, connected to the input trace; and wherein the second N-path filter is configured to shunt to a second reference voltage frequency from the signal.

Examples of integrated circuit (IC) structures with a merged nanoribbon-based transistor along a nanocomb transistor ribbon path are described herein. In one example, an extra wide "merged" nanoribbon-based transistor can be fabricated along the same ribbon path as a nanocomb transistor to take advantage of the area occupied by the spine of the nanocomb transistor in addition to the extra height made available by a double height cell. In one such example, a merged nanoribbon-based transistor can enable higher current while also improving the ratio of active area to dead space in the IC design.

Described herein are nanoribbon transistors and processes for forming nanoribbon transistors that include a nitride liner to protect the channel material during an oxide anneal. An oxide may be used to fill trenches between stacks of nanoribbons; the oxide is annealed, and then the oxide is recessed, forming isolation regions. Source and drain regions are formed over the isolation regions. In the resulting devices, the isolation regions have a liner layer that includes nitrogen. An additional oxide liner may be around the nitride liner.

Disclosed herein are gate metallization techniques for integrated circuit (IC) structures, and related methods and devices. In one aspect, a resulting IC structure may include a nanoribbon comprising a semiconductor material, and a P-type transistor comprising a gate electrode at least partially wrapping around a portion of the nanoribbon. In such an IC structure, the gate electrode includes a stack of conductive materials, the stack comprising a first conductive material, a second conductive material, and a third conductive material, wherein the second conductive material is between the first conductive material and the third conductive material and includes titanium.

In some embodiments, a trench isolation structure is formed from a first layer with enough carbon to sufficiently resist a dielectric etching process and a second, outer layer with surface wetting properties that allow it to adhere with the dielectric material that is to be etched.

Systems and methods are provided for a neural network for frame interpolation. The systems and methods can be used in real time applications such as gaming platforms, and include receiving two consecutive input image frames and a motion vector, and warping the input image frames to generate an intermediate frame at a new timepoint that lies between the two input image frames. A first network generates optical flow data representing changes between the two consecutive input image frames, such as changes in illumination and/or shading. The system generates optical flow data from each input image frame to the new timepoint as well as motion vectors from each input image to the new timepoint. A second network can use the optical flow data and the motion vector data to generate the intermediate frame. The frame interpolation pipeline can generate intermediate frames in an interactive environment where future frames are unknown.

Embodiments herein relate to techniques by which a Bluetooth low energy (LE) source may identify feedback related to a Bluetooth LE broadcast. The feedback may be provided by an assistant device that is communicatively coupled with a receiver. The feedback may be based on measurements performed by the assistant device and/or the receiver. Based on the feedback, the Bluetooth LE source may alter one or more parameters of a future Bluetooth LE broadcast. Other embodiments may be described and/or claimed.

Disclosed herein are S/D contact metallization techniques for integrated circuit (IC) structures, and related methods and devices. In one aspect, an IC structure fabricated using the S/D contact metallization method described herein may include a transistor including a region, where the region may be either a source region or a drain region of the transistor, and the IC structure may further include a contact structure in conductive contact with the region. In such an IC structure, the contact structure may include a layer (350) including a first metal, a fill material (364) including a second metal, and a semiconductor material (360) at the at least a portion of an interface between the layer and the fill material.

Techniques for using prefix bits to distinguish between loads and stores are described. An embodiment includes instruction decoder and execution circuitry. The instruction decoder circuitry is to decode an extended instruction set including a first and a second instruction. The first and second instructions have a format including an opcode field and a prefix field, and both have a first opcode value, corresponding to a NOP in a non-extended instruction set, in the opcode field. In the prefix field, the first instruction has a first prefix value and the second instruction has a second prefix value in the prefix field. The execution circuitry is to perform a first one or more operations related to the first instruction and a second one or more operations related to the second instruction, the first one or more operations including a load operation and the second one or more operations including a store operation.

Various embodiments herein provide techniques related to electronic device. The electronic device may be configured to store one or more broadcast audio signals received from a broadcast transmitter; identify, based on the one or more broadcast audio signals, a location of the electronic device with respect to the broadcast transmitter; and provide an indication of the location of the electronic device. Other embodiments may be described and/or claimed.

Embodiments herein relate to a voltage regulator (VR) including a measurement circuit to perform a periodic re-calibration which accounts for temperature effects. The measurement circuit compares the output voltage, Vout, to a work point (WP) or target voltage. Based on the comparison, an input to a summing circuit is adjusted. The measurement circuit can include a finite-state machine (FSM) which operates at a clock frequency which is significantly lower than a clock frequency of a main control loop of the VR. The FSM can increment or decrement the input to the multiplier when WP>Vout or WP<Vout, respectively. The WP is modified by the multiplier before being input to the VR.

Techniques for protecting integrated circuits from electrostatic discharge (ESD). A diode structure includes multiple emitter, base, and collector connections across a substrate. The connections are made to either n-doped substrate regions (for collector and emitter in NPN diode) or p-doped regions (for the base in NPN diode). P-doped base regions are arranged adjacent to each other in the substrate and are separated by a dielectric wall (e.g., shallow trench isolation). N-doped emitter regions may be arranged between sets of p-doped base regions. This arrangement effectively enlarges the base area of the diode structure, which decreases the current density. Additionally, the adjacent base regions allow for a wider metal interconnect layer over the adjacent base regions and a greater spacing between adjacent base and emitter interconnect layers. PNP diode structure is similarly configured, but with the dopant scheme reversed (p-doped substrate regions for collector and emitter and n-doped regions for base).

Examples include techniques for use of a distributed throttle architecture to mitigate voltage droop or current spikes The examples include use of circuitry distributed to portions of instruction execution pipeline circuitry capable of being arranged to execute one or more pipeline stages at a processor core, the circuitry to cause a throttle indication to be sent to the portions of the instruction execution pipeline circuitry based on received information that indicate energy events at the portions of instruction execution pipeline circuitry over a period of time.

Methods and apparatus for low latency fail-operational Time Sensitive Networking. An apparatus includes an error detection and path switching (EDPS) circuit comprising circuitry to read data from volatile memory, detect whether read data is errant, the errant data including one or more uncorrectable errors, and send a message to access correct data corresponding to the errant data stored in a non-volatile memory device, the message identifying the correct data to be returned to the EDPS circuit. The apparatus receives the correct data and enables the correct data to be read by circuitry coupled to the EPDS circuit. The EDPS circuit includes Error Correction Code (ECC) logic to detect uncorrectable errors, detect the data has no ECC errors, and detect and correct single-bit errors to obtain corrected data. Data with no ECC errors and corrected data is immediately made available for reading by the circuitry coupled to the EPDS circuit.

A method and system for deterministic communications between a plurality of interconnected semiconductor chips. The system includes a plurality of semiconductor chips, and a controller coupled to each of the plurality of semiconductor chips, respectively. The controller is configured to transfer data from one semiconductor chip to another. Each of the semiconductor chips and the controller include a respective clock, and the controller is configured to synchronize the clocks of the plurality of semiconductor chips. The controller schedules and manages data flows from and to the plurality of semiconductor chips for deterministic communications between the plurality of semiconductor chips. The controller may implement IEEE Time Sensitive Networking (TSN) protocol for scheduling and managing the data flows between the plurality of semiconductor chips.

An apparatus of a communication device, the apparatus may include a processor configured to: estimate noise power characteristics within a frequency band based on a received signal comprising a plurality of subcarriers within the frequency band, wherein the noise power characteristics comprises a plurality of noise samples; estimate a noise covariance matrix by averaging a number of noise samples of the plurality of noise samples; and apply a whitening that is based on the noise covariance matrix to subsequent received signals.

An example apparatus includes interface circuitry, machine-readable instructions, and at least one processor circuit to be programmed by the machine-readable instructions to interface circuitry to obtain a pre-trained detection model, machine-readable instructions, and at least one processor circuit to be programmed by the machine-readable instructions to tune the pre-trained detection model based on first local behavior data and execute the tuned detection model to detect an anomaly in second local behavior data associated with the apparatus.

Nanoribbon-based transistor fabrication techniques that use a sacrificial layer over the nanoribbon stack may enable more uniform deposition of the gate electrode material over the top nanoribbon in addition to protecting the top nanoribbon from damage resulting from subsequent processing. In one example, the technique may involve depositing a sacrificial layer (706), e.g., a dielectric material, over a stack of alternating layers of semiconductor material (702) that will subsequently be patterned into a fin and formed into a nanoribbon stack. After patterning the stack into a fin and releasing the nanoribbons of semiconductor material, the layer of sacrificial material (706) may act as a dummy nanoribbon over the top nanoribbon to enable deposition of the gate electrode material over the top nanoribbon having the same properties as the gate material between the nanoribbons.

An integrated circuit structure, comprises a first plurality of nanoribbons (104) above a first sub-fin region (108); a second plurality of nanoribbons (104) above a second sub-fin region (108), the second plurality of nanoribbons laterally spaced apart from the first plurality of nanoribbons; a dielectric fill (106) adjacent to the first sub-fin region and the second sub-fin region; a first gate layer (118a) around the first plurality of nanoribbons; a second gate layer (118b) around the second plurality of nanoribbons; and a gate cut (120) laterally between the first plurality of nanoribbons and the second plurality of nanoribbons and extending into the dielectric fill between the first sub-fin region and the second sub-fin region, the gate cut in contact with the first gate layer and the second gate layer, wherein the gate cut has a bottom surface above a bottom surface of the dielectric fill, wherein the gate cut has a height-to-width aspect ratio of 5:1 or greater.

There is disclosed, for example, an apparatus comprising a computer platform which includes a swappable first SoC, comprising a first security engine to perform security operations at the first SoC, and a second SoC comprising a second security engine to perform security operations at the second SoC. The first security engine and the second security engine are configured to: establish identity keys using mutual authentication of certificates, which is performed using a Security Protocol and Data Model, SPDM, protocol; use the identity keys to generate session keys; and establish a secure session channel between the swappable first SoC and the second SoC, based on the session keys, to secure data transmitted between the first SoC and the second SoC.

An apparatus for a user equipment, UE, the apparatus may include processing circuitry coupled to a storage, the processing circuitry configured to: generate a header or tag for attachment to a user plane, UP, data packet for in-network computing, wherein the header or tag comprises an operating mode information element representing whether the header or tag is independent of the UP data packet or not; and instruct the UE to transmit data comprising the header or tag attached to the UP data packet.

Workloads for executing a graph neural network (GNN) may be divided among various processing units, such as a central processing unit (CPU) and a neural processing unit (NPU). The NPU may include a data processing unit (DPU) and a digital signal processor (DSP). The CPU may perform precomputation, model optimization, hardware optimization, and compilation. For example, the CPU may precompute a parameter matrix and use the parameter matrix as internal parameters of a GNN. The CPU may also perform node padding, approximation computation, or transfer of DSP operations to DPU to optimize the GNN. The CPU may also perform sparsity data compute and storage, vertical fusion of DSP operations and DPU operations, or data quantization to optimize performance of the NPU. The compiled GNN may be provided to the NPU, and the DPU and DSP may perform the operations in the compiled GNN to produce a prediction of the GNN.

A processor of an aspect includes a decode unit to decode an indirect control flow transfer instruction, the instruction to indicate a register that is to store information to indicate an instruction pointer of a target instruction. An execution unit is to perform operations corresponding to the instruction, including to determine whether at least a first set of bits of an instruction pointer of the indirect control flow transfer instruction are compatible with at least a second set of bits of the instruction pointer of the target instruction. The operations also include to either store the instruction pointer of the target instruction in an instruction pointer storage if the first and second sets of bits are determined to be compatible, or to not store the instruction pointer of the target instruction in the instruction pointer storage if the first and second sets of bits are determined to not be compatible.

An apparatus and method for extending IO device security protocols to integrated processors. For example, an example processor package comprises: a plurality of cores to execute instructions; an interconnect fabric coupled to the plurality of cores; memory interface circuitry coupled to the interconnect fabric, the memory interface circuitry to couple the plurality of cores to one or more memories; a root complex comprising: security circuitry operable as a root of trust (RoT) and a bridge to the interconnect fabric, the security circuitry to establish secure communication with one or more Root Complex Integrated Endpoint (RCiEP) devices integral to the processor package; and a Security Protocol and Data Model (SPDM) engine of the security circuitry to provide RCiEP encryption and SPDM protocol services to establish secure communication channels with each RCiEP device.

A multi-feed antenna device includes a monopole antenna, having an antenna portion; a first antenna extension of a first length, extending from the antenna portion; a second antenna extension of a second length, less than the first length, extending from the antenna portion; a slot antenna, including a first slot of third length; a second slot of a fourth length, greater than the third length; a first antenna feed, coupled to the monopole antenna; a second antenna feed, coupled to the slot antenna; and a ground plane, common to both the monopole antenna and the slot antenna.

Gate-all-around integrated circuit structures having electrostatic discharge (ESD) clamps are described. For example, an integrated circuit structure includes a p channel device having a source structure and a drain structure. An n channel device is vertically stacked with the p channel device, the n channel device having a source structure and a drain structure. The source structure of the n channel device is electrically connected to the source structure of the p channel device. The drain structure of the n channel device is electrically connected to the drain structure of the p channel device.

To support flexible N:M sparsity pattern in a DCiM macro, the DCiM macro is subdivided into multiple sub-macros according to a partitioning factor P. Each sub-macro can support 1:2 sparsity ratio. Leveraging the partitioned design, the sub-macros can be grouped together to support different N:M sparsity patterns. To determine optimal N:N sparsity pattern for each layer of a neural network, an algorithm can determine the value A of a sparsity ratio A/B is based on the number of outliers in a layer, and the value B of the sparsity ratio A/B is based on the locality measure of the outliers representing the spatial distribution of the outliers. Moreover, the optimal N:M sparsity pattern that is aligned with the determined sparsity ratio A/B can be selected based on whether to prioritize latency or accuracy, or to balance both latency and accuracy.

Gate-all-around integrated circuit structures having source or drain structures with substrate connection portions, and methods of fabricating gate-all-around integrated circuit structures having source or drain structures with substrate connection portions, are described. For example, an integrated circuit structure comprises: a sub-fin; a vertical arrangement of nanowires over the sub-fin; a first source or drain structure at a first end of the vertical arrangement of nanowires; a second source or drain structure at a second end of the vertical arrangement of nanowires; a gate stack over and around each of the nanowires of the vertical arrangement of nanowires and laterally between the first source or drain structure and the second source or drain structure; a first conductive contact on the first source or drain structure; and a second conductive contact on the second source or drain structure.

Provided is a non-transitory machine-readable medium including machine-readable instructions. The machine-readable instructions cause, when executed on an apparatus, the apparatus to receive, by a trusted authority, a request for access to user data stored on a distributed network. The machine-readable instructions further cause the apparatus to search, by the trusted authority, an immutable ledger for an entry related to the user data. The machine-readable instructions further cause the apparatus to selectively decide, by the trusted authority and based on an access policy for the user data indicated by the entry, whether to grant access to the user data.

Examples relate to an apparatus comprising processing circuitry comprising a graphics processing unit (GPU) wherein the processing circuitry is configured to transcode one or more textures to a selected format for execution, and cache the transcoded textures for subsequent reuse.