Intel Patente

An apparatus may include: a resonator configured to oscillate at a resonant frequency; and a first oscillator core and a second oscillator core coupled to the resonator in a parallel configuration; wherein the first oscillator core configured to drive the resonator by providing a first drive signal and generate a first oscillator signal based on oscillations of the resonator; and wherein the second oscillator core configured to drive the resonator by providing a second drive signal and generate a second oscillator signal based on the oscillations of the resonator.

An apparatus may include: a common input terminal; a first inductor and a second inductor, each coupled to the common input terminal, wherein the first inductor and the second inductor are disposed in an electromagnetic coupling configuration; a lower frequency band output terminal coupled to the first inductor; a higher frequency band output terminal coupled to the second inductor; wherein the first inductor and the second inductor are to separate signals received from the common input terminal into the lower and the higher frequency band output terminals based on frequencies of the received signals. An apparatus may include: a first transformer magnetically couple a signal within a first frequency band and generate a first magnetic field with a first orientation; and a second transformer configured to magnetically couple a signal within a second frequency band that is different from the first frequency band.

A device has a first diplexer with a first port and a second port, configured to pass a first signal and a second signal, and a third port, configured to pass a first combined signal including the first signal and the second signal. The device has a second diplexer with a fourth port, configured to pass a third signal; a fifth port, configured to pass a fourth signal; and a sixth port, configured to pass a second combined signal including the third signal and the fourth signal. A dual-feed antenna has a first antenna interface, connected to the third port, and a second antenna interface, connected to the sixth port; and concurrently transmits or receives the first combined signal and the second combined signal. One of the first signal or the second signal, and one of the third signal or the fourth signal are in a common frequency band.

Package substrates with components included in cavities of glass cores are disclosed. An example apparatus includes: a glass layer having a first hole and a second hole, the second hole larger than an electronic component disposed therein, a width of the electronic component larger than a width of the first hole. The example apparatus further includes a conductive material that substantially fills the first hole; and a dielectric material that substantially fills a space within the second hole surrounding the electronic component.

Device stacking in integrated circuit layers using high accuracy bonding is described. In an example, an integrated circuit structure includes a first device layer above a first interconnect structure, the first device layer including nanowire-based transistors or fin-based transistors. The integrated circuit structure includes a second device layer below a second interconnect structure, the second device layer including nanowire-based transistors or fin-based transistors, and the second interconnect structure bonded directly to the first interconnect structure.

Embodiments herein relate to techniques by which a Bluetooth low energy (LE) source may identify feedback related to a Bluetooth LE broadcast. The feedback may be provided by an assistant device that is communicatively coupled with a receiver. The feedback may be based on measurements performed by the assistant device and/or the receiver. Based on the feedback, the Bluetooth LE source may alter one or more parameters of a future Bluetooth LE broadcast. Other embodiments may be described and/or claimed.

Techniques for using prefix bits to distinguish between loads and stores are described. An embodiment includes instruction decoder and execution circuitry. The instruction decoder circuitry is to decode an extended instruction set including a first and a second instruction. The first and second instructions have a format including an opcode field and a prefix field, and both have a first opcode value, corresponding to a NOP in a non-extended instruction set, in the opcode field. In the prefix field, the first instruction has a first prefix value and the second instruction has a second prefix value in the prefix field. The execution circuitry is to perform a first one or more operations related to the first instruction and a second one or more operations related to the second instruction, the first one or more operations including a load operation and the second one or more operations including a store operation.

Various embodiments herein provide techniques related to electronic device. The electronic device may be configured to store one or more broadcast audio signals received from a broadcast transmitter; identify, based on the one or more broadcast audio signals, a location of the electronic device with respect to the broadcast transmitter; and provide an indication of the location of the electronic device. Other embodiments may be described and/or claimed.

Embodiments herein relate to a voltage regulator (VR) including a measurement circuit to perform a periodic re-calibration which accounts for temperature effects. The measurement circuit compares the output voltage, Vout, to a work point (WP) or target voltage. Based on the comparison, an input to a summing circuit is adjusted. The measurement circuit can include a finite-state machine (FSM) which operates at a clock frequency which is significantly lower than a clock frequency of a main control loop of the VR. The FSM can increment or decrement the input to the multiplier when WP>Vout or WP<Vout, respectively. The WP is modified by the multiplier before being input to the VR.

Examples include techniques for use of a distributed throttle architecture to mitigate voltage droop or current spikes The examples include use of circuitry distributed to portions of instruction execution pipeline circuitry capable of being arranged to execute one or more pipeline stages at a processor core, the circuitry to cause a throttle indication to be sent to the portions of the instruction execution pipeline circuitry based on received information that indicate energy events at the portions of instruction execution pipeline circuitry over a period of time.

Techniques for protecting integrated circuits from electrostatic discharge (ESD). A diode structure includes multiple emitter, base, and collector connections across a substrate. The connections are made to either n-doped substrate regions (for collector and emitter in NPN diode) or p-doped regions (for the base in NPN diode). P-doped base regions are arranged adjacent to each other in the substrate and are separated by a dielectric wall (e.g., shallow trench isolation). N-doped emitter regions may be arranged between sets of p-doped base regions. This arrangement effectively enlarges the base area of the diode structure, which decreases the current density. Additionally, the adjacent base regions allow for a wider metal interconnect layer over the adjacent base regions and a greater spacing between adjacent base and emitter interconnect layers. PNP diode structure is similarly configured, but with the dopant scheme reversed (p-doped substrate regions for collector and emitter and n-doped regions for base).

A method and system for deterministic communications between a plurality of interconnected semiconductor chips. The system includes a plurality of semiconductor chips, and a controller coupled to each of the plurality of semiconductor chips, respectively. The controller is configured to transfer data from one semiconductor chip to another. Each of the semiconductor chips and the controller include a respective clock, and the controller is configured to synchronize the clocks of the plurality of semiconductor chips. The controller schedules and manages data flows from and to the plurality of semiconductor chips for deterministic communications between the plurality of semiconductor chips. The controller may implement IEEE Time Sensitive Networking (TSN) protocol for scheduling and managing the data flows between the plurality of semiconductor chips.

An example apparatus includes interface circuitry, machine-readable instructions, and at least one processor circuit to be programmed by the machine-readable instructions to interface circuitry to obtain a pre-trained detection model, machine-readable instructions, and at least one processor circuit to be programmed by the machine-readable instructions to tune the pre-trained detection model based on first local behavior data and execute the tuned detection model to detect an anomaly in second local behavior data associated with the apparatus.

An apparatus of a communication device, the apparatus may include a processor configured to: estimate noise power characteristics within a frequency band based on a received signal comprising a plurality of subcarriers within the frequency band, wherein the noise power characteristics comprises a plurality of noise samples; estimate a noise covariance matrix by averaging a number of noise samples of the plurality of noise samples; and apply a whitening that is based on the noise covariance matrix to subsequent received signals.

Workloads for executing a graph neural network (GNN) may be divided among various processing units, such as a central processing unit (CPU) and a neural processing unit (NPU). The NPU may include a data processing unit (DPU) and a digital signal processor (DSP). The CPU may perform precomputation, model optimization, hardware optimization, and compilation. For example, the CPU may precompute a parameter matrix and use the parameter matrix as internal parameters of a GNN. The CPU may also perform node padding, approximation computation, or transfer of DSP operations to DPU to optimize the GNN. The CPU may also perform sparsity data compute and storage, vertical fusion of DSP operations and DPU operations, or data quantization to optimize performance of the NPU. The compiled GNN may be provided to the NPU, and the DPU and DSP may perform the operations in the compiled GNN to produce a prediction of the GNN.

A processor of an aspect includes a decode unit to decode an indirect control flow transfer instruction, the instruction to indicate a register that is to store information to indicate an instruction pointer of a target instruction. An execution unit is to perform operations corresponding to the instruction, including to determine whether at least a first set of bits of an instruction pointer of the indirect control flow transfer instruction are compatible with at least a second set of bits of the instruction pointer of the target instruction. The operations also include to either store the instruction pointer of the target instruction in an instruction pointer storage if the first and second sets of bits are determined to be compatible, or to not store the instruction pointer of the target instruction in the instruction pointer storage if the first and second sets of bits are determined to not be compatible.

An apparatus and method for extending IO device security protocols to integrated processors. For example, an example processor package comprises: a plurality of cores to execute instructions; an interconnect fabric coupled to the plurality of cores; memory interface circuitry coupled to the interconnect fabric, the memory interface circuitry to couple the plurality of cores to one or more memories; a root complex comprising: security circuitry operable as a root of trust (RoT) and a bridge to the interconnect fabric, the security circuitry to establish secure communication with one or more Root Complex Integrated Endpoint (RCiEP) devices integral to the processor package; and a Security Protocol and Data Model (SPDM) engine of the security circuitry to provide RCiEP encryption and SPDM protocol services to establish secure communication channels with each RCiEP device.

A multi-feed antenna device includes a monopole antenna, having an antenna portion; a first antenna extension of a first length, extending from the antenna portion; a second antenna extension of a second length, less than the first length, extending from the antenna portion; a slot antenna, including a first slot of third length; a second slot of a fourth length, greater than the third length; a first antenna feed, coupled to the monopole antenna; a second antenna feed, coupled to the slot antenna; and a ground plane, common to both the monopole antenna and the slot antenna.

An apparatus for a user equipment, UE, the apparatus may include processing circuitry coupled to a storage, the processing circuitry configured to: generate a header or tag for attachment to a user plane, UP, data packet for in-network computing, wherein the header or tag comprises an operating mode information element representing whether the header or tag is independent of the UP data packet or not; and instruct the UE to transmit data comprising the header or tag attached to the UP data packet.

Gate-all-around integrated circuit structures having electrostatic discharge (ESD) clamps are described. For example, an integrated circuit structure includes a p channel device having a source structure and a drain structure. An n channel device is vertically stacked with the p channel device, the n channel device having a source structure and a drain structure. The source structure of the n channel device is electrically connected to the source structure of the p channel device. The drain structure of the n channel device is electrically connected to the drain structure of the p channel device.

To support flexible N:M sparsity pattern in a DCiM macro, the DCiM macro is subdivided into multiple sub-macros according to a partitioning factor P. Each sub-macro can support 1:2 sparsity ratio. Leveraging the partitioned design, the sub-macros can be grouped together to support different N:M sparsity patterns. To determine optimal N:N sparsity pattern for each layer of a neural network, an algorithm can determine the value A of a sparsity ratio A/B is based on the number of outliers in a layer, and the value B of the sparsity ratio A/B is based on the locality measure of the outliers representing the spatial distribution of the outliers. Moreover, the optimal N:M sparsity pattern that is aligned with the determined sparsity ratio A/B can be selected based on whether to prioritize latency or accuracy, or to balance both latency and accuracy.

Provided is a non-transitory machine-readable medium including machine-readable instructions. The machine-readable instructions cause, when executed on an apparatus, the apparatus to receive, by a trusted authority, a request for access to user data stored on a distributed network. The machine-readable instructions further cause the apparatus to search, by the trusted authority, an immutable ledger for an entry related to the user data. The machine-readable instructions further cause the apparatus to selectively decide, by the trusted authority and based on an access policy for the user data indicated by the entry, whether to grant access to the user data.

Gate-all-around integrated circuit structures having source or drain structures with substrate connection portions, and methods of fabricating gate-all-around integrated circuit structures having source or drain structures with substrate connection portions, are described. For example, an integrated circuit structure comprises: a sub-fin; a vertical arrangement of nanowires over the sub-fin; a first source or drain structure at a first end of the vertical arrangement of nanowires; a second source or drain structure at a second end of the vertical arrangement of nanowires; a gate stack over and around each of the nanowires of the vertical arrangement of nanowires and laterally between the first source or drain structure and the second source or drain structure; a first conductive contact on the first source or drain structure; and a second conductive contact on the second source or drain structure.

Provided is a computer-readable medium including computer-readable instructions. When the instructions are executed by a computer, the computer may implement a method. According to this method, contextual information of a plurality of users in a conversation is generated based on messages from the plurality of users over a period of time. Then the contextual information of the plurality of users is sent to a first artificial intelligence (AI) language model as input for training the Al language model and a request is sent to the first Al language model, wherein the request requires a response associated with the contextual information.

Techniques related to accelerated video enhancement using deep learning selectively applied based on video codec information are discussed. Such techniques include applying a deep learning video enhancement network selectively to decoded non-skip blocks that are in low quantization parameter frames, bypassing the deep learning network for decoded skip blocks in low quantization parameter frames, and applying non-deep learning video enhancement to high quantization parameter frames.

Photonic packages and device assemblies that include photonic integrated circuits (PICs) are described. An example integrated circuit (IC) device assembly comprises: a circuit board; a photonic package above the circuit board and a coupling structure between the circuit board and a second surface of a package support. The photonic package comprises: the package support having a first surface and the second surface opposite the first surface; a photonic integrated circuit (PIC) die over a first portion of the second surface of the package support; a processor die over a second portion of the second surface of the package support; a first electronic integrated circuit (EIC) die coupled in a flip-chip configuration with the PIC die; a second EIC die coupled in a flip-chip configuration with the PIC die; an optical coupler at a lateral surface of the PIC die; an adhesive between the optical coupler and the lateral surface of the PIC die; and a heat sink. Each of the PIC die and the processor die is between the package support and the heat sink.

A dual inline memory module (DIMM) connector has pins to connect to pad footprints and signal routing that reduces crosstalk and noise. The shape and placement of ground pads and signal pads can improve grounding of noise signals and improve the signal isolation on the signal pins. The ground pads can have additional ground vias to increase the ground path to the ground plane.

Examples include techniques associated with causing a change to a configuration to access a storage device based on determined bandwidth capabilities for read and write transactions to the storage device and based on a determined needed bandwidth to complete monitored read and write transactions to the storage device. The configuration to be based, at least in part, on coupling to the storage device via a storage interface over a serial bus and the configuration to include a link width for the serial bus, a link speed for the serial bus, or a power state to operate the storage device.

It is provided an anon-transitory computer-readable medium storing instructions that, when executed by one or more processing circuitries, causing the one or more processing circuitries to perform a method for attestation of a running workload in a trusted execution environment. The method comprises generating a first measurement of a workload. The method further comprises capturing one or more snapshots of a trusted execution environment executing the workload. The one or more snapshots are captured based on one or more snapshot triggers. The method comprises generating a second measurement of the workload while the workload is being executed in the trusted execution environment. The method comprises verifying the generated second measurement. The method comprises triggering a verification failure action, if the verification of the second measurement fails.

An apparatus, method, and computer-readable medium for configuring of microservices in a networked system. The method comprising monitoring one or more metrics of the networked system, determining a topology of the networked system based on the one or more metrics, and configuring of the plurality of microservices based on the topology.

Methods and apparatus to mitigate cracking in glass cores are disclosed. An example apparatus comprises a glass core having an opening extending between opposing surfaces of the glass core, and a metal within the opening, a gap between an interface of the metal and a sidewall of the opening.

Nanoribbon-based devices with separate gate, source, and/or drain contacts can enable forming multiple devices having one or more independent contacts from different nanoribbons in a stack. In one example, an integrated circuity structure includes a stack of two or more nanoribbons, a gate electrode material at least partially around portions of the two or more nanoribbons, and source or drain regions, where discontinuities (e.g., including an insulator material) may be present between portions of the gate electrode material and/or between portions of the source or drain regions. Independent contact structures may be coupled with the separate portions of the gate electrode material and/or with the separate portions of the source or drain regions.

An apparatus is disclosed that includes a network interface device comprising processors to implement network interface device functionality and communication protocol engine circuitry, wherein the network interface device is to: receive a request to write data to a memory node communicably coupled to the network interface device; identify network information corresponding to the request, wherein the network information includes at least one of quality of service (QoS), physical function (PF), virtual function (VF), name space identifier (NSID), flow ID, service level objectives (SLOs), or process address space ID (PASID); identify characteristics of the memory node, wherein the characteristics include at least page size of the memory node; and cause the data to be coalesced with other data on the memory node based on the network information and the characteristics.

A method and apparatus for authentication of a user. A user profile is generated during an initial registration. The user profile may include a trusted location of the user. During a subsequent authentication process for the user, it is determined whether the user is located in the trusted location of the user, and an access to a service for the user may be controlled based on a result of the authentication process and the determination whether the user is located in the trusted location of the user. A location-based parameter of the trusted location of the user may be determined and stored in advance, and it is determined whether the user is located in the trusted location of the user by comparing the location-based parameter of the current location of the user and the location-based parameter of the trusted location of the user.

This disclosure describes systems, methods, and devices related to cross-channel interference. A device may detect energy on a non-primary channel to identify adjacent channel interference. The device may adjust transmission parameters based on detected interference. The device may enable communication on available channels within a basic service set bandwidth.

This disclosure describes systems, methods, and devices for remotely controlling device settings for collaboration sessions. A device may identify an alphanumeric handle based on a location identifier of a first location associated with the device and a collaboration session identifier for a collaboration session of a collaboration application executed by the device; generate a Bluetooth Low Energy (BLE) advertising packet including a header and a payload, the header including the alphanumeric handle and a hardware identifier that identifies the device; transmit the BLE advertising packet; identify an authentication request received from a second device in the collaboration session, the authentication request including the alphanumeric handle; authenticate the second device based on the alphanumeric handle; and transmit a BLE notification packet including an indication of a volume at which the second device is to set a speaker for the collaboration session.

An integrated circuit structure (500) comprises: a gate stack structure (308D) comprising a gate dielectric layer and a gate electrode, the gate stack structure having a first side and a second side, the second side laterally opposite the first side; a first trench contact (310B) laterally spaced apart from the first side of the gate stack structure; a first spacer (520) laterally between the first trench contact and the first side of the gate stack structure; a second trench contact (310C) laterally spaced apart from the second side of the gate stack structure; a second spacer (520) laterally between the second trench contact and the second side of the gate stack structure; and an insulating cap layer (322, 522) on a top surface of the first spacer, on a top surface of the gate stack structure, on a top surface of the second spacer, and laterally between the first trench contact and the second trench contact.

Examples described herein relate to a first graphics processing unit (GPU) with at least one integrated communications system, wherein the at least one integrated communications system is to apply a reliability protocol to communicate with a second at least one integrated communications system associated with a second GPU to copy data from a first memory region to a second memory region and wherein the first memory region is associated with the first GPU and the second memory region is associated with the second GPU.

Techniques for reconstructing a die unique wrapping key from non-volatile (NVM) memory by a memory controller circuit are described. In certain examples, a computer system includes a processing circuit to perform one or more operations according to the one or more values; a non-volatile memory; and a memory controller circuit coupled to the non-volatile memory, the memory controller circuit to: read data from the non-volatile memory, read a key mask from the non-volatile memory, perform a hashing operation on the data from the non-volatile memory to generate a digest value, perform a reversible function on the digest value and the key mask to recover a wrapping-key, and decrypt encrypted data of the data with the wrapping-key to recover one or more values for the processing circuit.

Circuitry and methods for implementing conditional fence instructions are described. In certain examples, a hardware processor (e.g., core) includes a branch predictor to predict one of a taken path and a not taken path for a conditional branch instruction; decoder circuitry to decode an instruction into a decoded instruction, the instruction comprising a field that indicates a condition to be set by execution of another instruction, and an opcode that indicates execution circuitry is to, in response to the condition being satisfied, implement an execution fence to delay execution of the instruction until prior instructions in program order execute and delay execution of instructions after the instruction in program order until the instruction executes; and the execution circuitry to execute the decoded instruction according to the opcode.