NXP USA Patente

The regulation and clamping functions are separated at a controller integrated circuit (IC) for a DC-DC converter. The controller IC includes a clamp circuit configured to clamp the voltage at a pin of the controller IC that is connected to external compensation circuitry. The controller IC further includes a different regulation circuit configured to regulate a clamp loop of the controller IC.

A power amplifier device (130, 230, 330, 430, 430', 530, 530') includes a power transistor die (154, 174, 454, 474), an input side signal lead (140, 141, 240, 241, 440, 441) electrically coupled to an input terminal of the power transistor die and extending beyond an input side (131, 231, 331, 431, 1031) of the device, an output side signal lead (144, 145, 244, 245, 444, 445) electrically coupled to an output terminal of the power transistor die and extending beyond an output side (132, 232, 332, 432, 1032) of the device, and an input-to-output bias-conducting structure (133, 135, 433, 435, 533, 535, 1000, 1100, 1200, 1300) that is not physically directly connected to the input side signal lead or to the output side signal lead. The input-to-output bias-conducting structure includes an input side bias lead (142, 143, 242, 243, 342, 343, 442, 443, 542, 543, 1042, 1242, 1342) coupled to an input portion of the device, an output side bias lead (146, 147, 246, 247, 346, 247, 446, 447, 546, 547, 1046, 1246, 1346) coupled to an output portion of the device, and an interior conductive structure (134, 136, 434, 436, 1034, 1134, 1234, 1334) with a first end connected to the input side bias lead, and a second end connected to the output side bias lead.

A device includes a radiofrequency integrated circuit (RFIC) having a radiofrequency (RF) input terminal and an RF output terminal and also includes a field plate electrode having a first end that is electrically-coupled to the RF output terminal and a second end that is suspended above the RFIC. The second end of the field plate electrode is configured to float at an electric potential that is determined by an electric potential of the RF output terminal.

Built-in self-test circuitry is configured to calculate a sensed temperature using an MRAM and a stored set of margin read reference and temperature correlations for a target bit error rate. A current margin read reference is selected, and a sweep through a sequence of addresses of the MRAM is performed using the current margin read reference. At each address of the sequence, a normal read is performed to obtain normal read data and a margin read is performed to obtain margin read data. A bit error count is obtained for the sweep based on comparisons between the normal and margin read data obtained at each address, and the current margin read reference is selectively modified based on whether or not the bit error count achieves the target bit error rate. The selectively modified current margin read reference and the stored set of correlations are used to calculate the sensed temperature.

A processing system including processing cores, a shared memory, a shift table that stores a maximum number of reservations to locations in the memory, and an exclusive monitor that uses the shift table and an eviction policy to enforce core synchronization. The eviction policy is based on priority, age of valid reservations, shift table fullness state, and reservation memory conflict. The shift table may include a memory address and a size value indicative of a flexible amount of reserved memory at the memory address. The exclusive monitor evicts an oldest reservation in the shift table having a same or lower priority level as the new reservation. The exclusive monitor rejects the new reservation when the shift table is full of higher priority reservations. Reservations are shifted to maintain age status. Stale reservations may be invalidated or have their priority lowered. Conflicting reservations may be made with the same priority level.

A pipelined SAR ADC that is connected to receive an analog input voltage includes a first ADC stage, a residue amplifier, a second ADC stage, and calibration circuitry coupled and configured to add first and second ADC conversion results to form an uncalibrated digital value, and to apply calibration values to the uncalibrated digital value to obtain a calibrated digital value corresponding to a calibrated digital representation of the analog input voltage, where the calibration values include a first ADC stage DAC element mismatch calibration value corresponding to the first ADC conversion result, an offset calibration value, and a gain adjustment factor.

A circuit arrangement comprises an output combiner circuit including a first output network having a first amplifier output node for connection to a first output of the main amplifier, a second output network having a second amplifier output node for connection to a second output of the peaking amplifier, and a final summing node. The first output network comprises a first inductive element connected between the first amplifier output node and a first intermediate node, a second inductive element connected between the first intermediate node and the final summing node, and a third inductive element connected between the first intermediate node and ground. The second output network comprises a fourth inductive element connected between the second amplifier output node and a second intermediate node, a fifth inductive element connected between the second intermediate node and ground, and a capacitive element connected between the second intermediate node and the final summing node.

A Doherty power amplifier includes a combining node that combines amplified output signals from first and second amplifiers. A reconfigurable impedance inverter circuit is coupled between the first amplifier and the combining node. The impedance inverter circuit includes an inductive element coupled between a first node and a second node, and a switching circuit coupled between the first node and the second node. A fundamental frequency tuning circuit and a harmonic frequency resonance circuit are coupled between the switching circuit and a ground reference node. When the switching circuit is configured in a first state, the fundamental frequency tuning circuit and the harmonic frequency resonance circuit are electrically coupled through the switching circuit to the first and second nodes. When the switching circuit is configured in a second state, the fundamental frequency tuning circuit and the harmonic frequency resonance circuit are electrically disconnected from the first and second nodes.

A system and method include receiving, by a security controller of a system-on-chip and from a controller of the system-on-chip, an indication that a debugger computing device is connected to a debug port of the system-on-chip. A user debug authorization key and a user debug profile are received and verified by the security controller. The user debug profile identifies a set of requested resources. A configuration of the system-on-chip is modified to allow the debugger computing device to access resources of the set of requested resources.

A method, system, apparatus, and architecture are provided for reacting to resource faults by deploying safety management unit (SMU) instances at a plurality of functional components, where each SMU instance is program code configured to monitor a first set of one or more resources assigned to run a first application; detect a fault at the first set of one or more resources; identify a second set of one or more resources for reallocation to the first application using a ranked listing of candidate resource sets, where each candidate resource set is capable of running the first application; and assign the second set of one or more resources to run the first application, where the ranked listing of candidate resource sets is dynamically updated based on runtime performance and health measures of resources in the candidate resource set.

A non-volatile memory (NVM) controller is configured to control reads from and writes to an NVM array, and includes a write buffer and a buffer control circuit. The write buffer includes a plurality of entries, each configured to store a write access having a corresponding page address of the NVM array and corresponding write data. The buffer control circuit is configured to store a write access having a corresponding page address of the NVM array and corresponding write data, and generate burst writes from the write buffer to the NVM array. The buffer control circuit generates a burst write by sequentially selecting write accesses from the write buffer which have consecutive page addresses, in which the length of the burst write is undefined when the burst write to the NVM array is initiated.

An electronic device has a molded package (e.g., a quad flat no leads package) with attached connectors. The molded package includes one or more semiconductor dies and is pretested prior to attachment of the connectors. Along these lines, such molded packages may be pretested in parallel at high volume due to their relatively small form factor (e.g., at numbers several times greater than those for testing leaded socket assemblies). Following such pretesting, the connectors are attached to the pretested molded package (e.g., by directly fusing the connectors to metallic pads on surfaces of the packaged integrated circuit via laser welding or soldering). Such electronic devices may be further tested if desired (e.g., opens/shorts tested) and encased within housings to form larger modules (e.g., accelerometers, pressure sensors, etc.).

A splitter/combiner having a first port, a second port, and a third port includes a first transmission line coupled between the first port and the second port, a second transmission line coupled between the first port and the third port, a resistor coupled between the second port and the third port, and first and second capacitors each having a first terminal and a second terminal, the first terminal of the first capacitor coupled to the second port, the first terminal of the second capacitor coupled to the third port, the second terminal of each of the first and second capacitors coupled to a common node. At least one of the first capacitor, second capacitor, first transmission line, and second transmission line is adjustable during operation for varying the electrical properties of the splitter/combiner.

A method for delivering data frames from a source device (602) to a Zigbee end device, ZED, (550) via a Zigbee router device, ZR, (510), comprises, at the ZR, receiving (605), a data request and at least one data block (615) from a transmission window of a plurality of data blocks from the source device (602), and placing the received data block in a queue for transmission; receiving (609) a data request from the ZED; transmitting, the received data block from the queue, to the ZED and receiving an acknowledgement from the ZED. The method further includes receiving a re-transmission of the transmission window of the data blocks (625, 630, 635) from the source device (602); and dropping, at least one re-transmitted data block (630), previously received and transmitted by the ZR, and transmitting, by the ZR, the remaining re-transmitted data block(s) (625, 635), to the ZED.

A method of manufacturing a semiconductor device interconnect structure is provided. The method includes forming a copper pillar on a semiconductor die by way of a plating process. A proximal portion of the copper pillar has a first width dimension, and a distal portion of the copper pillar has a second width dimension. The second width dimension of the distal portion of the copper pillar is configured to be smaller than the first width dimension of the proximal portion of the copper pillar. Sidewalls of the distal portion of the copper pillar are selectively roughened. The roughened sidewalls of the distal portion of the copper pillar are configured to promote solder wetting.

A method for delivering data frames from a source device (702) to a Zigbee end device, ZED, (550) via a Zigbee router, ZR, (510), comprises, at the ZR, receiving individual data blocks with a fragmentation window of '1' data block between the ZR and the source, individually transmitting an APS acknowledgement for received data blocks identified by APS transmission parameters. Data blocks are re-transmitted until an acknowledgement of a successful receipt is transmitted to the source. The data block is transmitted to the ZED until an acknowledgement is received. Following a penultimate data block (720) having been transmitted from the ZR and acknowledged by the ZED, the method further comprises at the ZED: transmitting a second data request (762, 772) to the ZR for a final data block; and transmitting an APS acknowledgement of successfully receiving the final data block to the ZR; and to the source.

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A mechanism for making multiple security schemes available in a single embedded system without requiring a firmware update or a hardware extension is provided. Embodiments provide firmware support for storing parameters related to each available security scheme and a selection mechanism to select the desired security scheme for the application utilizing the embedded system. Embodiments can also provide a status register to provide to a user an identification of the security scheme that is presently enabled on the embedded system. Embodiments can further prevent a malicious user from selecting an invalid security scheme.

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An amplifier device includes a first input terminal, a second input terminal, a first transistor having a first control electrode and first and second current-carrying electrodes, wherein the first control electrode is radio frequency (RF) coupled to the first input terminal and DC-coupled to a first bias network electrically coupled to the first control electrode, wherein the first bias network is configured to apply a first direct current (DC) bias to the first control electrode and is RF-isolated from the first control electrode. The amplifier device further includes a second transistor that includes a second control electrode that is RF coupled to the second input terminal and a second bias network electrically coupled to the second transistor, wherein the second bias network is configured to apply a second DC bias to the second transistor and is RF-isolated from the second transistor.

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